Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145268124	1			T1	668262		T3	4080		T4	380844
instr_valid_dis	115437673	1			T1	668262		T3	4080		T5	1962
instr_en	20273597	1			T4	380844		T11	249418		T6	48024

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10007411	1			T4	68626		T11	83638		T6	36830
sram_ifetch_valid_disable	115248835	1			T1	668262		T3	4080		T4	110060
sram_ifetch_enable	20011878	1			T4	202158		T11	254584		T6	159724

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145268124	1			T1	668262		T3	4080		T4	380844
hw_debug_en_valid_off	114917888	1			T1	668262		T3	4080		T4	132018
hw_debug_en_on	20147140	1			T4	163784		T11	196930		T6	120170

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115248835	1			T1	668262		T3	4080		T4	110060
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102388679	1			T1	668262		T3	4080		T5	1962
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8705636	1			T4	110060		T11	66714		T6	48024
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4072527	1			T4	53202		T6	36830		T39	45726
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1764830	1			T6	36830		T39	45726		T24	56010
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1474377	1			T4	53202		T20	22226		T138	336
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4204476	1			T4	6170		T11	81954		T39	26354
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1845656	1			T11	35042		T24	40052		T65	2772
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1640506	1			T4	6170		T11	46912		T39	26354
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7503632	1			T4	76074		T11	57280		T6	70204
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3027710	1			T6	70204		T24	24536		T65	46664
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3114612	1			T4	76074		T11	18656		T39	49940

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7664858	1			T4	202158		T11	134108		T39	58878
lc_exec_en	8439032	1			T4	81540		T11	57696		T6	49966
valid_exec_dis	112385203	1			T1	668262		T3	4080		T4	33986
invalid_exec_dis	30019289	1			T4	270784		T11	338222		T6	196554