Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44816631	1			T1	303830		T3	93		T4	69528
triple_byte_access	2495758	1			T1	6071		T3	247		T4	1357
halfword_access	3743499	1			T1	9080		T3	432		T4	1986
byte_access	4993789	1			T1	12141		T3	818		T4	2872
zero_access	1258280	1			T1	3009		T3	450		T4	651

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28599896

1

T1

167241

T3

958

T4

38211

auto[1]

28708061

1

T1

166890

T3

1082

T4

38183

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22354675	1			T1	152035		T3	6		T4	34812
auto[0]	triple_byte_access	1245816	1			T1	3082		T3	44		T4	646
auto[0]	halfword_access	1868603	1			T1	4498		T3	151		T4	975
auto[0]	byte_access	2497772	1			T1	6119		T3	408		T4	1468
auto[0]	zero_access	633030	1			T1	1507		T3	349		T4	310
auto[1]	word_access	22461956	1			T1	151795		T3	87		T4	34716
auto[1]	triple_byte_access	1249942	1			T1	2989		T3	203		T4	711
auto[1]	halfword_access	1874896	1			T1	4582		T3	281		T4	1011
auto[1]	byte_access	2496017	1			T1	6022		T3	410		T4	1404
auto[1]	zero_access	625250	1			T1	1502		T3	101		T4	341