| T793 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.644931369 |
|
|
Jul 15 05:00:51 PM PDT 24 |
Jul 15 05:01:00 PM PDT 24 |
2251660425 ps |
| T794 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2536161563 |
|
|
Jul 15 04:57:09 PM PDT 24 |
Jul 15 04:59:42 PM PDT 24 |
3325353728 ps |
| T795 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.168185576 |
|
|
Jul 15 04:58:52 PM PDT 24 |
Jul 15 05:12:53 PM PDT 24 |
86558285902 ps |
| T796 |
/workspace/coverage/default/4.sram_ctrl_smoke.917361375 |
|
|
Jul 15 04:56:28 PM PDT 24 |
Jul 15 04:57:10 PM PDT 24 |
157873242 ps |
| T797 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2323682569 |
|
|
Jul 15 05:05:04 PM PDT 24 |
Jul 15 05:10:42 PM PDT 24 |
7972369615 ps |
| T798 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.2950190541 |
|
|
Jul 15 04:59:19 PM PDT 24 |
Jul 15 05:03:51 PM PDT 24 |
5967954879 ps |
| T799 |
/workspace/coverage/default/4.sram_ctrl_stress_all.1732520631 |
|
|
Jul 15 04:56:36 PM PDT 24 |
Jul 15 05:31:25 PM PDT 24 |
33252866223 ps |
| T800 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.508378681 |
|
|
Jul 15 04:56:36 PM PDT 24 |
Jul 15 04:57:26 PM PDT 24 |
1571868241 ps |
| T801 |
/workspace/coverage/default/16.sram_ctrl_bijection.2331460866 |
|
|
Jul 15 04:59:03 PM PDT 24 |
Jul 15 04:59:50 PM PDT 24 |
681552897 ps |
| T802 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.3608619676 |
|
|
Jul 15 04:56:42 PM PDT 24 |
Jul 15 04:57:20 PM PDT 24 |
92319545 ps |
| T803 |
/workspace/coverage/default/15.sram_ctrl_alert_test.4063501309 |
|
|
Jul 15 04:59:04 PM PDT 24 |
Jul 15 04:59:06 PM PDT 24 |
17118339 ps |
| T804 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3833090233 |
|
|
Jul 15 04:58:01 PM PDT 24 |
Jul 15 04:59:03 PM PDT 24 |
883807594 ps |
| T805 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.950355346 |
|
|
Jul 15 05:01:13 PM PDT 24 |
Jul 15 05:10:23 PM PDT 24 |
45661365080 ps |
| T806 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1038261787 |
|
|
Jul 15 05:00:23 PM PDT 24 |
Jul 15 05:22:41 PM PDT 24 |
3566989874 ps |
| T807 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2831238111 |
|
|
Jul 15 04:56:43 PM PDT 24 |
Jul 15 05:25:17 PM PDT 24 |
15422208386 ps |
| T808 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.94557582 |
|
|
Jul 15 04:56:51 PM PDT 24 |
Jul 15 04:56:57 PM PDT 24 |
372295005 ps |
| T809 |
/workspace/coverage/default/32.sram_ctrl_regwen.2490068427 |
|
|
Jul 15 05:02:51 PM PDT 24 |
Jul 15 05:28:51 PM PDT 24 |
8318669478 ps |
| T810 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4125952006 |
|
|
Jul 15 05:01:32 PM PDT 24 |
Jul 15 05:01:35 PM PDT 24 |
478323968 ps |
| T811 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.6796744 |
|
|
Jul 15 05:07:01 PM PDT 24 |
Jul 15 05:07:16 PM PDT 24 |
2225411755 ps |
| T812 |
/workspace/coverage/default/42.sram_ctrl_smoke.3543390 |
|
|
Jul 15 05:05:36 PM PDT 24 |
Jul 15 05:05:59 PM PDT 24 |
9012750169 ps |
| T813 |
/workspace/coverage/default/15.sram_ctrl_executable.1771545836 |
|
|
Jul 15 04:59:00 PM PDT 24 |
Jul 15 05:11:54 PM PDT 24 |
9630136375 ps |
| T814 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1605545482 |
|
|
Jul 15 05:03:07 PM PDT 24 |
Jul 15 05:03:14 PM PDT 24 |
997077216 ps |
| T815 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2857851686 |
|
|
Jul 15 05:02:23 PM PDT 24 |
Jul 15 05:24:08 PM PDT 24 |
15020833460 ps |
| T816 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.2610861972 |
|
|
Jul 15 05:01:00 PM PDT 24 |
Jul 15 05:11:15 PM PDT 24 |
7435201963 ps |
| T817 |
/workspace/coverage/default/35.sram_ctrl_regwen.400128293 |
|
|
Jul 15 05:03:30 PM PDT 24 |
Jul 15 05:33:48 PM PDT 24 |
8352903478 ps |
| T818 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3943720271 |
|
|
Jul 15 05:04:07 PM PDT 24 |
Jul 15 05:08:38 PM PDT 24 |
2617269802 ps |
| T819 |
/workspace/coverage/default/27.sram_ctrl_stress_all.2432847617 |
|
|
Jul 15 05:01:41 PM PDT 24 |
Jul 15 06:31:11 PM PDT 24 |
15782142506 ps |
| T820 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3948365032 |
|
|
Jul 15 04:59:22 PM PDT 24 |
Jul 15 05:18:49 PM PDT 24 |
10111261324 ps |
| T821 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.3880073858 |
|
|
Jul 15 05:04:06 PM PDT 24 |
Jul 15 05:04:29 PM PDT 24 |
281795348 ps |
| T822 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1922596001 |
|
|
Jul 15 05:05:29 PM PDT 24 |
Jul 15 05:46:11 PM PDT 24 |
30267559654 ps |
| T823 |
/workspace/coverage/default/14.sram_ctrl_smoke.2015515545 |
|
|
Jul 15 04:58:35 PM PDT 24 |
Jul 15 04:58:40 PM PDT 24 |
307187324 ps |
| T824 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2571256277 |
|
|
Jul 15 04:57:39 PM PDT 24 |
Jul 15 05:01:15 PM PDT 24 |
47520291252 ps |
| T825 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.3156877977 |
|
|
Jul 15 04:59:10 PM PDT 24 |
Jul 15 04:59:16 PM PDT 24 |
282775242 ps |
| T826 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.4208607648 |
|
|
Jul 15 05:07:02 PM PDT 24 |
Jul 15 05:07:08 PM PDT 24 |
74519172 ps |
| T827 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.4262069473 |
|
|
Jul 15 05:05:38 PM PDT 24 |
Jul 15 05:10:33 PM PDT 24 |
10729313923 ps |
| T828 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2165940606 |
|
|
Jul 15 05:02:51 PM PDT 24 |
Jul 15 05:02:52 PM PDT 24 |
70363943 ps |
| T829 |
/workspace/coverage/default/48.sram_ctrl_executable.680385876 |
|
|
Jul 15 05:07:50 PM PDT 24 |
Jul 15 05:31:10 PM PDT 24 |
7042403081 ps |
| T830 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3523318602 |
|
|
Jul 15 05:06:36 PM PDT 24 |
Jul 15 05:07:58 PM PDT 24 |
1400149107 ps |
| T831 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3152348991 |
|
|
Jul 15 05:01:53 PM PDT 24 |
Jul 15 05:02:33 PM PDT 24 |
1112490518 ps |
| T832 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.148080997 |
|
|
Jul 15 05:05:05 PM PDT 24 |
Jul 15 05:05:44 PM PDT 24 |
103959769 ps |
| T833 |
/workspace/coverage/default/1.sram_ctrl_partial_access.2268795178 |
|
|
Jul 15 04:55:42 PM PDT 24 |
Jul 15 04:55:51 PM PDT 24 |
1370038163 ps |
| T834 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.3966795772 |
|
|
Jul 15 05:02:51 PM PDT 24 |
Jul 15 05:02:52 PM PDT 24 |
31894909 ps |
| T835 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3594875919 |
|
|
Jul 15 04:56:29 PM PDT 24 |
Jul 15 04:56:56 PM PDT 24 |
345260355 ps |
| T836 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3714023760 |
|
|
Jul 15 05:04:34 PM PDT 24 |
Jul 15 05:16:42 PM PDT 24 |
43686393706 ps |
| T837 |
/workspace/coverage/default/47.sram_ctrl_smoke.1827975781 |
|
|
Jul 15 05:07:16 PM PDT 24 |
Jul 15 05:09:13 PM PDT 24 |
773826456 ps |
| T838 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2514052792 |
|
|
Jul 15 05:01:50 PM PDT 24 |
Jul 15 05:13:16 PM PDT 24 |
14564884554 ps |
| T839 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3348702420 |
|
|
Jul 15 05:04:42 PM PDT 24 |
Jul 15 05:09:24 PM PDT 24 |
21234109637 ps |
| T840 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3097352895 |
|
|
Jul 15 04:59:11 PM PDT 24 |
Jul 15 04:59:23 PM PDT 24 |
64470405 ps |
| T841 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.2130927995 |
|
|
Jul 15 04:58:59 PM PDT 24 |
Jul 15 05:00:07 PM PDT 24 |
102840265 ps |
| T842 |
/workspace/coverage/default/33.sram_ctrl_regwen.286371024 |
|
|
Jul 15 05:02:59 PM PDT 24 |
Jul 15 05:24:16 PM PDT 24 |
17317329680 ps |
| T843 |
/workspace/coverage/default/2.sram_ctrl_stress_all.3605870439 |
|
|
Jul 15 04:56:05 PM PDT 24 |
Jul 15 06:01:39 PM PDT 24 |
38827900931 ps |
| T844 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1026876043 |
|
|
Jul 15 04:58:00 PM PDT 24 |
Jul 15 04:58:02 PM PDT 24 |
13771299 ps |
| T845 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2077170180 |
|
|
Jul 15 04:58:25 PM PDT 24 |
Jul 15 04:58:37 PM PDT 24 |
7272734743 ps |
| T846 |
/workspace/coverage/default/14.sram_ctrl_regwen.2985761088 |
|
|
Jul 15 04:58:51 PM PDT 24 |
Jul 15 05:15:19 PM PDT 24 |
150286112628 ps |
| T847 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.1131846331 |
|
|
Jul 15 05:00:31 PM PDT 24 |
Jul 15 05:22:19 PM PDT 24 |
13614118374 ps |
| T848 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4001655728 |
|
|
Jul 15 05:01:15 PM PDT 24 |
Jul 15 05:05:05 PM PDT 24 |
3905626928 ps |
| T849 |
/workspace/coverage/default/3.sram_ctrl_bijection.1205903251 |
|
|
Jul 15 04:56:05 PM PDT 24 |
Jul 15 04:57:35 PM PDT 24 |
5306074960 ps |
| T850 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.2519084249 |
|
|
Jul 15 04:56:04 PM PDT 24 |
Jul 15 04:56:06 PM PDT 24 |
90765237 ps |
| T851 |
/workspace/coverage/default/0.sram_ctrl_bijection.3747020905 |
|
|
Jul 15 04:55:28 PM PDT 24 |
Jul 15 04:56:29 PM PDT 24 |
1641479923 ps |
| T852 |
/workspace/coverage/default/31.sram_ctrl_executable.4026734526 |
|
|
Jul 15 05:02:27 PM PDT 24 |
Jul 15 05:11:27 PM PDT 24 |
4410116381 ps |
| T853 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1864275487 |
|
|
Jul 15 05:04:11 PM PDT 24 |
Jul 15 05:25:01 PM PDT 24 |
16975725611 ps |
| T854 |
/workspace/coverage/default/43.sram_ctrl_smoke.2482597001 |
|
|
Jul 15 05:05:53 PM PDT 24 |
Jul 15 05:06:17 PM PDT 24 |
14788502535 ps |
| T855 |
/workspace/coverage/default/30.sram_ctrl_smoke.3508174865 |
|
|
Jul 15 05:02:06 PM PDT 24 |
Jul 15 05:02:59 PM PDT 24 |
1838239709 ps |
| T856 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.402808331 |
|
|
Jul 15 04:56:51 PM PDT 24 |
Jul 15 05:06:33 PM PDT 24 |
7423149371 ps |
| T857 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3334465162 |
|
|
Jul 15 05:05:04 PM PDT 24 |
Jul 15 05:05:06 PM PDT 24 |
43014541 ps |
| T858 |
/workspace/coverage/default/37.sram_ctrl_partial_access.831133042 |
|
|
Jul 15 05:04:03 PM PDT 24 |
Jul 15 05:05:45 PM PDT 24 |
1242549791 ps |
| T859 |
/workspace/coverage/default/34.sram_ctrl_smoke.237157384 |
|
|
Jul 15 05:03:11 PM PDT 24 |
Jul 15 05:03:41 PM PDT 24 |
791191588 ps |
| T860 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3567345788 |
|
|
Jul 15 04:55:35 PM PDT 24 |
Jul 15 05:22:56 PM PDT 24 |
3847337472 ps |
| T861 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.4077165015 |
|
|
Jul 15 05:01:26 PM PDT 24 |
Jul 15 05:03:15 PM PDT 24 |
6391274389 ps |
| T862 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.660496837 |
|
|
Jul 15 05:03:15 PM PDT 24 |
Jul 15 05:03:23 PM PDT 24 |
58309007 ps |
| T863 |
/workspace/coverage/default/23.sram_ctrl_bijection.2130219342 |
|
|
Jul 15 05:00:33 PM PDT 24 |
Jul 15 05:01:01 PM PDT 24 |
895551413 ps |
| T864 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2696227451 |
|
|
Jul 15 04:56:42 PM PDT 24 |
Jul 15 04:57:57 PM PDT 24 |
244901734 ps |
| T865 |
/workspace/coverage/default/0.sram_ctrl_regwen.3313756114 |
|
|
Jul 15 04:55:34 PM PDT 24 |
Jul 15 05:15:07 PM PDT 24 |
45885205056 ps |
| T866 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.1437779111 |
|
|
Jul 15 05:02:35 PM PDT 24 |
Jul 15 05:24:02 PM PDT 24 |
39888693293 ps |
| T867 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3909253156 |
|
|
Jul 15 04:56:00 PM PDT 24 |
Jul 15 04:56:11 PM PDT 24 |
123127909 ps |
| T868 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.2168899422 |
|
|
Jul 15 04:56:26 PM PDT 24 |
Jul 15 05:18:25 PM PDT 24 |
10143322682 ps |
| T869 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.3027343051 |
|
|
Jul 15 05:03:17 PM PDT 24 |
Jul 15 05:03:18 PM PDT 24 |
48453450 ps |
| T870 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2703668301 |
|
|
Jul 15 04:58:05 PM PDT 24 |
Jul 15 04:58:14 PM PDT 24 |
630310336 ps |
| T871 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3955550092 |
|
|
Jul 15 04:58:43 PM PDT 24 |
Jul 15 05:00:40 PM PDT 24 |
124465691 ps |
| T872 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3533045988 |
|
|
Jul 15 05:01:01 PM PDT 24 |
Jul 15 05:04:12 PM PDT 24 |
27040934134 ps |
| T873 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1679422812 |
|
|
Jul 15 05:07:47 PM PDT 24 |
Jul 15 05:08:17 PM PDT 24 |
354873727 ps |
| T874 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.1621721314 |
|
|
Jul 15 05:01:12 PM PDT 24 |
Jul 15 05:01:14 PM PDT 24 |
26569913 ps |
| T875 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1627241825 |
|
|
Jul 15 04:55:40 PM PDT 24 |
Jul 15 05:02:18 PM PDT 24 |
14229577986 ps |
| T876 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.3510332822 |
|
|
Jul 15 05:00:52 PM PDT 24 |
Jul 15 05:00:55 PM PDT 24 |
389305451 ps |
| T877 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.343762301 |
|
|
Jul 15 04:59:02 PM PDT 24 |
Jul 15 04:59:06 PM PDT 24 |
371715740 ps |
| T878 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2785780155 |
|
|
Jul 15 04:59:13 PM PDT 24 |
Jul 15 05:00:53 PM PDT 24 |
728782211 ps |
| T879 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.390711822 |
|
|
Jul 15 05:08:22 PM PDT 24 |
Jul 15 05:08:37 PM PDT 24 |
1829218329 ps |
| T880 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.733867164 |
|
|
Jul 15 05:04:50 PM PDT 24 |
Jul 15 05:04:56 PM PDT 24 |
449764679 ps |
| T881 |
/workspace/coverage/default/5.sram_ctrl_bijection.3549501698 |
|
|
Jul 15 04:56:41 PM PDT 24 |
Jul 15 04:57:40 PM PDT 24 |
3352254367 ps |
| T882 |
/workspace/coverage/default/14.sram_ctrl_partial_access.377555156 |
|
|
Jul 15 04:58:46 PM PDT 24 |
Jul 15 04:59:43 PM PDT 24 |
1649376638 ps |
| T883 |
/workspace/coverage/default/15.sram_ctrl_regwen.2798958325 |
|
|
Jul 15 04:59:03 PM PDT 24 |
Jul 15 05:14:18 PM PDT 24 |
11055012733 ps |
| T884 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.651101572 |
|
|
Jul 15 04:59:31 PM PDT 24 |
Jul 15 05:02:37 PM PDT 24 |
9476014750 ps |
| T885 |
/workspace/coverage/default/30.sram_ctrl_executable.770349491 |
|
|
Jul 15 05:02:14 PM PDT 24 |
Jul 15 05:07:53 PM PDT 24 |
8388726381 ps |
| T886 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3861967279 |
|
|
Jul 15 04:57:35 PM PDT 24 |
Jul 15 04:57:48 PM PDT 24 |
7368657998 ps |
| T887 |
/workspace/coverage/default/46.sram_ctrl_executable.2481596524 |
|
|
Jul 15 05:07:08 PM PDT 24 |
Jul 15 05:19:02 PM PDT 24 |
2061735449 ps |
| T888 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1696545763 |
|
|
Jul 15 05:08:06 PM PDT 24 |
Jul 15 05:11:17 PM PDT 24 |
2196090949 ps |
| T889 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1714982761 |
|
|
Jul 15 04:57:18 PM PDT 24 |
Jul 15 04:57:24 PM PDT 24 |
1480466100 ps |
| T890 |
/workspace/coverage/default/40.sram_ctrl_regwen.2344950252 |
|
|
Jul 15 05:05:06 PM PDT 24 |
Jul 15 05:08:27 PM PDT 24 |
4828875193 ps |
| T891 |
/workspace/coverage/default/25.sram_ctrl_bijection.3131705199 |
|
|
Jul 15 05:01:01 PM PDT 24 |
Jul 15 05:02:20 PM PDT 24 |
7237216688 ps |
| T892 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2265770809 |
|
|
Jul 15 05:00:32 PM PDT 24 |
Jul 15 05:00:33 PM PDT 24 |
11457642 ps |
| T893 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.433410579 |
|
|
Jul 15 05:06:07 PM PDT 24 |
Jul 15 05:06:09 PM PDT 24 |
30589100 ps |
| T894 |
/workspace/coverage/default/49.sram_ctrl_executable.1092134757 |
|
|
Jul 15 05:08:13 PM PDT 24 |
Jul 15 05:32:35 PM PDT 24 |
128764250218 ps |
| T895 |
/workspace/coverage/default/46.sram_ctrl_alert_test.3362142197 |
|
|
Jul 15 05:07:19 PM PDT 24 |
Jul 15 05:07:23 PM PDT 24 |
19653030 ps |
| T896 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.1066305349 |
|
|
Jul 15 05:03:25 PM PDT 24 |
Jul 15 05:13:19 PM PDT 24 |
72212584969 ps |
| T897 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.811289147 |
|
|
Jul 15 05:04:30 PM PDT 24 |
Jul 15 05:04:46 PM PDT 24 |
248364413 ps |
| T898 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3572093478 |
|
|
Jul 15 04:57:46 PM PDT 24 |
Jul 15 04:57:47 PM PDT 24 |
47993000 ps |
| T899 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.11933534 |
|
|
Jul 15 05:02:34 PM PDT 24 |
Jul 15 05:02:40 PM PDT 24 |
281908318 ps |
| T900 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3519696577 |
|
|
Jul 15 04:57:37 PM PDT 24 |
Jul 15 04:58:19 PM PDT 24 |
1763537827 ps |
| T901 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3572995715 |
|
|
Jul 15 05:07:31 PM PDT 24 |
Jul 15 05:07:41 PM PDT 24 |
100647909 ps |
| T902 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.3257808428 |
|
|
Jul 15 04:59:38 PM PDT 24 |
Jul 15 05:11:15 PM PDT 24 |
11473719160 ps |
| T903 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3872245653 |
|
|
Jul 15 05:01:06 PM PDT 24 |
Jul 15 05:19:33 PM PDT 24 |
23894898664 ps |
| T904 |
/workspace/coverage/default/28.sram_ctrl_alert_test.3863747151 |
|
|
Jul 15 05:01:47 PM PDT 24 |
Jul 15 05:01:50 PM PDT 24 |
26373470 ps |
| T905 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2170543087 |
|
|
Jul 15 05:02:08 PM PDT 24 |
Jul 15 05:02:12 PM PDT 24 |
55570790 ps |
| T906 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1449489148 |
|
|
Jul 15 05:04:21 PM PDT 24 |
Jul 15 05:04:34 PM PDT 24 |
643421863 ps |
| T907 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2480680990 |
|
|
Jul 15 05:02:01 PM PDT 24 |
Jul 15 05:02:14 PM PDT 24 |
1315600519 ps |
| T908 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.61852928 |
|
|
Jul 15 04:58:36 PM PDT 24 |
Jul 15 04:58:50 PM PDT 24 |
684153985 ps |
| T909 |
/workspace/coverage/default/10.sram_ctrl_smoke.3859874716 |
|
|
Jul 15 04:57:53 PM PDT 24 |
Jul 15 04:58:07 PM PDT 24 |
1538090933 ps |
| T910 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4214455332 |
|
|
Jul 15 04:57:29 PM PDT 24 |
Jul 15 04:57:35 PM PDT 24 |
1310832427 ps |
| T911 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1697898478 |
|
|
Jul 15 04:57:44 PM PDT 24 |
Jul 15 04:57:47 PM PDT 24 |
527020840 ps |
| T912 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2886988186 |
|
|
Jul 15 05:01:17 PM PDT 24 |
Jul 15 05:02:03 PM PDT 24 |
1928051187 ps |
| T913 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3285659513 |
|
|
Jul 15 05:05:26 PM PDT 24 |
Jul 15 05:07:38 PM PDT 24 |
148576746 ps |
| T914 |
/workspace/coverage/default/38.sram_ctrl_partial_access.1064663100 |
|
|
Jul 15 05:04:30 PM PDT 24 |
Jul 15 05:04:39 PM PDT 24 |
407297378 ps |
| T915 |
/workspace/coverage/default/6.sram_ctrl_stress_all.972684959 |
|
|
Jul 15 04:57:07 PM PDT 24 |
Jul 15 05:09:54 PM PDT 24 |
46805333824 ps |
| T916 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2327713646 |
|
|
Jul 15 05:08:03 PM PDT 24 |
Jul 15 05:09:24 PM PDT 24 |
717362047 ps |
| T917 |
/workspace/coverage/default/6.sram_ctrl_bijection.1380731957 |
|
|
Jul 15 04:56:50 PM PDT 24 |
Jul 15 04:58:03 PM PDT 24 |
1055745776 ps |
| T918 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2800108203 |
|
|
Jul 15 05:01:05 PM PDT 24 |
Jul 15 05:01:12 PM PDT 24 |
2804821067 ps |
| T919 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.1015126636 |
|
|
Jul 15 04:59:20 PM PDT 24 |
Jul 15 04:59:21 PM PDT 24 |
26444514 ps |
| T920 |
/workspace/coverage/default/33.sram_ctrl_bijection.1831690094 |
|
|
Jul 15 05:02:59 PM PDT 24 |
Jul 15 05:04:11 PM PDT 24 |
3490771666 ps |
| T921 |
/workspace/coverage/default/1.sram_ctrl_smoke.1387421824 |
|
|
Jul 15 04:55:42 PM PDT 24 |
Jul 15 04:58:27 PM PDT 24 |
797870075 ps |
| T922 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2803037646 |
|
|
Jul 15 05:01:25 PM PDT 24 |
Jul 15 05:07:03 PM PDT 24 |
32547820789 ps |
| T923 |
/workspace/coverage/default/49.sram_ctrl_smoke.665920089 |
|
|
Jul 15 05:07:55 PM PDT 24 |
Jul 15 05:08:07 PM PDT 24 |
460499859 ps |
| T924 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.344312940 |
|
|
Jul 15 04:55:49 PM PDT 24 |
Jul 15 04:55:54 PM PDT 24 |
217116758 ps |
| T925 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.1070863768 |
|
|
Jul 15 05:04:30 PM PDT 24 |
Jul 15 05:06:10 PM PDT 24 |
133101655 ps |
| T926 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.205720490 |
|
|
Jul 15 04:56:12 PM PDT 24 |
Jul 15 05:05:25 PM PDT 24 |
698507077 ps |
| T927 |
/workspace/coverage/default/22.sram_ctrl_bijection.408610843 |
|
|
Jul 15 05:00:24 PM PDT 24 |
Jul 15 05:01:27 PM PDT 24 |
7357243503 ps |
| T928 |
/workspace/coverage/default/38.sram_ctrl_regwen.2276068081 |
|
|
Jul 15 05:04:30 PM PDT 24 |
Jul 15 05:17:20 PM PDT 24 |
7721865248 ps |
| T929 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1811861795 |
|
|
Jul 15 05:02:58 PM PDT 24 |
Jul 15 05:04:53 PM PDT 24 |
612234784 ps |
| T930 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4202852059 |
|
|
Jul 15 05:06:46 PM PDT 24 |
Jul 15 05:08:28 PM PDT 24 |
495208672 ps |
| T931 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.4179422092 |
|
|
Jul 15 04:55:42 PM PDT 24 |
Jul 15 05:15:42 PM PDT 24 |
60276532686 ps |
| T932 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.1295149062 |
|
|
Jul 15 05:01:53 PM PDT 24 |
Jul 15 05:02:05 PM PDT 24 |
3648682224 ps |
| T933 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.229318961 |
|
|
Jul 15 05:04:19 PM PDT 24 |
Jul 15 05:04:25 PM PDT 24 |
781247887 ps |
| T934 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.259201278 |
|
|
Jul 15 04:50:22 PM PDT 24 |
Jul 15 04:50:24 PM PDT 24 |
56603692 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.543510146 |
|
|
Jul 15 04:49:40 PM PDT 24 |
Jul 15 04:49:43 PM PDT 24 |
723428870 ps |
| T63 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2087043192 |
|
|
Jul 15 04:50:22 PM PDT 24 |
Jul 15 04:50:23 PM PDT 24 |
54711437 ps |
| T935 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.884222103 |
|
|
Jul 15 04:50:26 PM PDT 24 |
Jul 15 04:50:28 PM PDT 24 |
40523961 ps |
| T64 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.38689899 |
|
|
Jul 15 04:50:26 PM PDT 24 |
Jul 15 04:50:30 PM PDT 24 |
859848819 ps |
| T61 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.954469556 |
|
|
Jul 15 04:50:33 PM PDT 24 |
Jul 15 04:50:37 PM PDT 24 |
712151427 ps |
| T97 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3570486793 |
|
|
Jul 15 04:50:26 PM PDT 24 |
Jul 15 04:50:28 PM PDT 24 |
24784234 ps |
| T77 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.458058278 |
|
|
Jul 15 04:50:33 PM PDT 24 |
Jul 15 04:50:38 PM PDT 24 |
1652047998 ps |
| T936 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3665803715 |
|
|
Jul 15 04:50:19 PM PDT 24 |
Jul 15 04:50:23 PM PDT 24 |
114770031 ps |
| T937 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.115199743 |
|
|
Jul 15 04:50:18 PM PDT 24 |
Jul 15 04:50:23 PM PDT 24 |
128388574 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2508530969 |
|
|
Jul 15 04:49:58 PM PDT 24 |
Jul 15 04:49:59 PM PDT 24 |
29169725 ps |
| T62 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3123695716 |
|
|
Jul 15 04:50:28 PM PDT 24 |
Jul 15 04:50:30 PM PDT 24 |
132415078 ps |
| T121 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2409426919 |
|
|
Jul 15 04:50:18 PM PDT 24 |
Jul 15 04:50:20 PM PDT 24 |
187914887 ps |
| T98 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2819507140 |
|
|
Jul 15 04:50:37 PM PDT 24 |
Jul 15 04:50:39 PM PDT 24 |
22795542 ps |
| T79 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3346163142 |
|
|
Jul 15 04:50:35 PM PDT 24 |
Jul 15 04:50:38 PM PDT 24 |
205496042 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.664078888 |
|
|
Jul 15 04:50:08 PM PDT 24 |
Jul 15 04:50:09 PM PDT 24 |
18944205 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3007581842 |
|
|
Jul 15 04:50:15 PM PDT 24 |
Jul 15 04:50:16 PM PDT 24 |
53579803 ps |
| T125 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1055228314 |
|
|
Jul 15 04:50:14 PM PDT 24 |
Jul 15 04:50:17 PM PDT 24 |
2519910433 ps |
| T938 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3238534336 |
|
|
Jul 15 04:50:33 PM PDT 24 |
Jul 15 04:50:35 PM PDT 24 |
28383218 ps |
| T939 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.931415790 |
|
|
Jul 15 04:51:21 PM PDT 24 |
Jul 15 04:51:25 PM PDT 24 |
163890737 ps |
| T81 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.84417896 |
|
|
Jul 15 04:50:12 PM PDT 24 |
Jul 15 04:50:13 PM PDT 24 |
48117503 ps |
| T129 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2096391635 |
|
|
Jul 15 04:50:18 PM PDT 24 |
Jul 15 04:50:21 PM PDT 24 |
161448908 ps |
| T940 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1720971945 |
|
|
Jul 15 04:50:30 PM PDT 24 |
Jul 15 04:50:32 PM PDT 24 |
43628563 ps |
| T82 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1902715735 |
|
|
Jul 15 04:50:27 PM PDT 24 |
Jul 15 04:50:28 PM PDT 24 |
256016914 ps |
| T83 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1400726236 |
|
|
Jul 15 04:50:03 PM PDT 24 |
Jul 15 04:50:06 PM PDT 24 |
469991748 ps |
| T99 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4265190125 |
|
|
Jul 15 04:50:22 PM PDT 24 |
Jul 15 04:50:24 PM PDT 24 |
39456237 ps |
| T941 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1806944216 |
|
|
Jul 15 04:50:04 PM PDT 24 |
Jul 15 04:50:05 PM PDT 24 |
22854692 ps |
| T132 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1994047219 |
|
|
Jul 15 04:50:33 PM PDT 24 |
Jul 15 04:50:36 PM PDT 24 |
149918394 ps |
| T942 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2192554472 |
|
|
Jul 15 04:50:34 PM PDT 24 |
Jul 15 04:50:36 PM PDT 24 |
38157761 ps |
| T943 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2281460890 |
|
|
Jul 15 04:50:37 PM PDT 24 |
Jul 15 04:50:40 PM PDT 24 |
91042258 ps |
| T944 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2642716891 |
|
|
Jul 15 04:50:26 PM PDT 24 |
Jul 15 04:50:29 PM PDT 24 |
82100051 ps |
| T122 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.511048108 |
|
|
Jul 15 04:50:29 PM PDT 24 |
Jul 15 04:50:33 PM PDT 24 |
347193688 ps |
| T84 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2317206497 |
|
|
Jul 15 04:50:29 PM PDT 24 |
Jul 15 04:50:33 PM PDT 24 |
822465083 ps |
| T130 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2975591427 |
|
|
Jul 15 04:49:54 PM PDT 24 |
Jul 15 04:49:57 PM PDT 24 |
2582217680 ps |
| T85 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.449781013 |
|
|
Jul 15 04:50:15 PM PDT 24 |
Jul 15 04:50:18 PM PDT 24 |
80607199 ps |
| T86 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3425868207 |
|
|
Jul 15 04:50:31 PM PDT 24 |
Jul 15 04:50:32 PM PDT 24 |
29474912 ps |
| T87 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3466124181 |
|
|
Jul 15 04:50:28 PM PDT 24 |
Jul 15 04:50:31 PM PDT 24 |
921550843 ps |
| T945 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.222791203 |
|
|
Jul 15 04:50:13 PM PDT 24 |
Jul 15 04:50:18 PM PDT 24 |
141783467 ps |
| T123 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3359330650 |
|
|
Jul 15 04:50:30 PM PDT 24 |
Jul 15 04:50:33 PM PDT 24 |
893061174 ps |
| T946 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2378912108 |
|
|
Jul 15 04:50:04 PM PDT 24 |
Jul 15 04:50:06 PM PDT 24 |
49420723 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.101106558 |
|
|
Jul 15 04:49:55 PM PDT 24 |
Jul 15 04:49:59 PM PDT 24 |
166131713 ps |
| T948 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3208166060 |
|
|
Jul 15 04:50:27 PM PDT 24 |
Jul 15 04:50:29 PM PDT 24 |
56646926 ps |
| T88 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3650514203 |
|
|
Jul 15 04:49:47 PM PDT 24 |
Jul 15 04:49:48 PM PDT 24 |
13731370 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3083714753 |
|
|
Jul 15 04:50:33 PM PDT 24 |
Jul 15 04:50:36 PM PDT 24 |
147645510 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3107566824 |
|
|
Jul 15 04:50:25 PM PDT 24 |
Jul 15 04:50:27 PM PDT 24 |
78349809 ps |
| T89 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1443222315 |
|
|
Jul 15 04:50:33 PM PDT 24 |
Jul 15 04:50:35 PM PDT 24 |
43457290 ps |
| T90 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1350216317 |
|
|
Jul 15 04:49:56 PM PDT 24 |
Jul 15 04:49:58 PM PDT 24 |
47461920 ps |
| T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1291314171 |
|
|
Jul 15 04:50:00 PM PDT 24 |
Jul 15 04:50:03 PM PDT 24 |
598498316 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2140607564 |
|
|
Jul 15 04:50:28 PM PDT 24 |
Jul 15 04:50:30 PM PDT 24 |
100994810 ps |
| T124 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2998934891 |
|
|
Jul 15 04:50:31 PM PDT 24 |
Jul 15 04:50:34 PM PDT 24 |
706929661 ps |
| T96 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1945356143 |
|
|
Jul 15 04:50:26 PM PDT 24 |
Jul 15 04:50:30 PM PDT 24 |
2186987242 ps |
| T952 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2604866745 |
|
|
Jul 15 04:50:21 PM PDT 24 |
Jul 15 04:50:24 PM PDT 24 |
410405600 ps |
| T953 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2179384525 |
|
|
Jul 15 04:50:35 PM PDT 24 |
Jul 15 04:50:37 PM PDT 24 |
54312425 ps |
| T954 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3558727729 |
|
|
Jul 15 04:50:28 PM PDT 24 |
Jul 15 04:50:30 PM PDT 24 |
21891286 ps |
| T955 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3796499920 |
|
|
Jul 15 04:50:33 PM PDT 24 |
Jul 15 04:50:35 PM PDT 24 |
11553598 ps |
| T134 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.895563143 |
|
|
Jul 15 04:50:31 PM PDT 24 |
Jul 15 04:50:34 PM PDT 24 |
144660620 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3150122556 |
|
|
Jul 15 04:49:48 PM PDT 24 |
Jul 15 04:49:50 PM PDT 24 |
46834476 ps |
| T93 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2428767013 |
|
|
Jul 15 04:50:26 PM PDT 24 |
Jul 15 04:50:28 PM PDT 24 |
55219732 ps |
| T957 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.628354332 |
|
|
Jul 15 04:50:14 PM PDT 24 |
Jul 15 04:50:15 PM PDT 24 |
31594434 ps |
| T958 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3285401816 |
|
|
Jul 15 04:50:27 PM PDT 24 |
Jul 15 04:50:29 PM PDT 24 |
28055235 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4116467671 |
|
|
Jul 15 04:50:04 PM PDT 24 |
Jul 15 04:50:06 PM PDT 24 |
12075365 ps |
| T131 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.704238486 |
|
|
Jul 15 04:50:27 PM PDT 24 |
Jul 15 04:50:30 PM PDT 24 |
141584200 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2392300056 |
|
|
Jul 15 04:50:18 PM PDT 24 |
Jul 15 04:50:20 PM PDT 24 |
35090095 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.671487844 |
|
|
Jul 15 04:49:50 PM PDT 24 |
Jul 15 04:49:52 PM PDT 24 |
65192796 ps |
| T95 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1262527059 |
|
|
Jul 15 04:50:28 PM PDT 24 |
Jul 15 04:50:29 PM PDT 24 |
140865161 ps |
| T962 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3092091570 |
|
|
Jul 15 04:50:18 PM PDT 24 |
Jul 15 04:50:19 PM PDT 24 |
43261723 ps |
| T963 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1051888469 |
|
|
Jul 15 04:50:12 PM PDT 24 |
Jul 15 04:50:13 PM PDT 24 |
34015618 ps |
| T964 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3131788984 |
|
|
Jul 15 04:50:35 PM PDT 24 |
Jul 15 04:50:40 PM PDT 24 |
717935650 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3951659480 |
|
|
Jul 15 04:50:15 PM PDT 24 |
Jul 15 04:50:17 PM PDT 24 |
44897515 ps |
| T966 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.272836597 |
|
|
Jul 15 04:50:32 PM PDT 24 |
Jul 15 04:50:33 PM PDT 24 |
22038331 ps |
| T967 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1269346930 |
|
|
Jul 15 04:50:25 PM PDT 24 |
Jul 15 04:50:26 PM PDT 24 |
16706681 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.256620419 |
|
|
Jul 15 04:49:51 PM PDT 24 |
Jul 15 04:49:52 PM PDT 24 |
19171896 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.531318272 |
|
|
Jul 15 04:50:04 PM PDT 24 |
Jul 15 04:50:05 PM PDT 24 |
26095671 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3614534268 |
|
|
Jul 15 04:50:14 PM PDT 24 |
Jul 15 04:50:16 PM PDT 24 |
213482529 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.199209744 |
|
|
Jul 15 04:50:27 PM PDT 24 |
Jul 15 04:50:32 PM PDT 24 |
175831361 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.390761436 |
|
|
Jul 15 04:50:38 PM PDT 24 |
Jul 15 04:50:40 PM PDT 24 |
48463177 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1326026101 |
|
|
Jul 15 04:51:03 PM PDT 24 |
Jul 15 04:51:06 PM PDT 24 |
106075459 ps |
| T974 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3765140886 |
|
|
Jul 15 04:50:25 PM PDT 24 |
Jul 15 04:50:26 PM PDT 24 |
21026205 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.173415783 |
|
|
Jul 15 04:50:25 PM PDT 24 |
Jul 15 04:50:26 PM PDT 24 |
33757763 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2739202036 |
|
|
Jul 15 04:50:12 PM PDT 24 |
Jul 15 04:50:13 PM PDT 24 |
27000336 ps |
| T127 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2673182116 |
|
|
Jul 15 04:50:21 PM PDT 24 |
Jul 15 04:50:24 PM PDT 24 |
107599128 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1543684699 |
|
|
Jul 15 04:50:03 PM PDT 24 |
Jul 15 04:50:05 PM PDT 24 |
76580551 ps |
| T978 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.510944601 |
|
|
Jul 15 04:50:13 PM PDT 24 |
Jul 15 04:50:17 PM PDT 24 |
1487278615 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4272130437 |
|
|
Jul 15 04:50:05 PM PDT 24 |
Jul 15 04:50:06 PM PDT 24 |
76809953 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2413648470 |
|
|
Jul 15 04:50:15 PM PDT 24 |
Jul 15 04:50:17 PM PDT 24 |
16444773 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1017461813 |
|
|
Jul 15 04:50:15 PM PDT 24 |
Jul 15 04:50:17 PM PDT 24 |
447074125 ps |
| T982 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1878690218 |
|
|
Jul 15 04:50:39 PM PDT 24 |
Jul 15 04:50:41 PM PDT 24 |
18585058 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3195104079 |
|
|
Jul 15 04:50:21 PM PDT 24 |
Jul 15 04:50:23 PM PDT 24 |
15543795 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.268686527 |
|
|
Jul 15 04:50:16 PM PDT 24 |
Jul 15 04:50:17 PM PDT 24 |
22114957 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1979627716 |
|
|
Jul 15 04:49:48 PM PDT 24 |
Jul 15 04:49:50 PM PDT 24 |
419040239 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3576365393 |
|
|
Jul 15 04:50:33 PM PDT 24 |
Jul 15 04:50:35 PM PDT 24 |
28255069 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1811346218 |
|
|
Jul 15 04:50:27 PM PDT 24 |
Jul 15 04:50:29 PM PDT 24 |
14378221 ps |
| T988 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1277765935 |
|
|
Jul 15 04:50:18 PM PDT 24 |
Jul 15 04:50:19 PM PDT 24 |
45454331 ps |
| T128 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1017725198 |
|
|
Jul 15 04:49:56 PM PDT 24 |
Jul 15 04:49:59 PM PDT 24 |
372985114 ps |
| T989 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1708127170 |
|
|
Jul 15 04:50:16 PM PDT 24 |
Jul 15 04:50:17 PM PDT 24 |
25103194 ps |
| T990 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4061604369 |
|
|
Jul 15 04:50:22 PM PDT 24 |
Jul 15 04:50:26 PM PDT 24 |
433221251 ps |
| T991 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.418235208 |
|
|
Jul 15 04:50:06 PM PDT 24 |
Jul 15 04:50:11 PM PDT 24 |
426039082 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3930754998 |
|
|
Jul 15 04:50:00 PM PDT 24 |
Jul 15 04:50:02 PM PDT 24 |
41080180 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1620883438 |
|
|
Jul 15 04:49:45 PM PDT 24 |
Jul 15 04:49:46 PM PDT 24 |
63158169 ps |
| T994 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.419857052 |
|
|
Jul 15 04:50:14 PM PDT 24 |
Jul 15 04:50:16 PM PDT 24 |
45388714 ps |
| T133 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2215627563 |
|
|
Jul 15 04:50:33 PM PDT 24 |
Jul 15 04:50:36 PM PDT 24 |
469035531 ps |
| T995 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2261894546 |
|
|
Jul 15 04:50:20 PM PDT 24 |
Jul 15 04:50:23 PM PDT 24 |
68466610 ps |
| T996 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3610757270 |
|
|
Jul 15 04:50:32 PM PDT 24 |
Jul 15 04:50:36 PM PDT 24 |
1469662882 ps |
| T997 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2903353201 |
|
|
Jul 15 04:50:17 PM PDT 24 |
Jul 15 04:50:18 PM PDT 24 |
66531901 ps |
| T998 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1415555064 |
|
|
Jul 15 04:50:26 PM PDT 24 |
Jul 15 04:50:29 PM PDT 24 |
332905874 ps |
| T999 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1819328536 |
|
|
Jul 15 04:50:32 PM PDT 24 |
Jul 15 04:50:34 PM PDT 24 |
42639813 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3085817001 |
|
|
Jul 15 04:49:58 PM PDT 24 |
Jul 15 04:50:02 PM PDT 24 |
144089789 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2653060756 |
|
|
Jul 15 04:50:14 PM PDT 24 |
Jul 15 04:50:17 PM PDT 24 |
122765918 ps |
| T1002 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2379291258 |
|
|
Jul 15 04:50:27 PM PDT 24 |
Jul 15 04:50:34 PM PDT 24 |
612364648 ps |