SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[sram_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[sram_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 69736166 | 0 | T1 | 126929 | T2 | 148213 | T3 | 1317 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 69735958 | 1 | T1 | 126929 | T2 | 148213 | T3 | 1317 | ||||
values[1] | 29 | 1 | T70 | 2 | T71 | 2 | T126 | 3 | ||||
values[2] | 7 | 1 | T69 | 1 | T71 | 1 | T127 | 1 | ||||
values[3] | 100 | 1 | T69 | 5 | T70 | 6 | T71 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 69735966 | 1 | T1 | 126929 | T2 | 148213 | T3 | 1317 | ||||
values[1] | 22 | 1 | T70 | 2 | T71 | 3 | T128 | 1 | ||||
values[2] | 10 | 1 | T70 | 1 | T126 | 1 | T129 | 2 | ||||
values[3] | 103 | 1 | T69 | 3 | T70 | 3 | T71 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 69735866 | 1 | T1 | 126929 | T2 | 148213 | T3 | 1317 | ||||
auto[TlIntgErrCmd] | 100 | 1 | T69 | 5 | T70 | 3 | T71 | 9 | ||||
auto[TlIntgErrData] | 92 | 1 | T70 | 1 | T71 | 5 | T128 | 1 | ||||
auto[TlIntgErrBoth] | 108 | 1 | T69 | 5 | T70 | 6 | T71 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 385303 | 0 | T1 | 58 | T2 | 4 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 385100 | 1 | T1 | 58 | T2 | 4 | T3 | 1 | ||||
values[1] | 26 | 1 | T69 | 1 | T70 | 1 | T71 | 2 | ||||
values[2] | 2 | 1 | T127 | 1 | T130 | 1 | - | - | ||||
values[3] | 107 | 1 | T69 | 3 | T70 | 4 | T71 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 385107 | 1 | T1 | 58 | T2 | 4 | T3 | 1 | ||||
values[1] | 19 | 1 | T128 | 2 | T129 | 4 | T127 | 1 | ||||
values[2] | 10 | 1 | T71 | 2 | T126 | 2 | T127 | 1 | ||||
values[3] | 117 | 1 | T69 | 8 | T70 | 5 | T71 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 385003 | 1 | T1 | 58 | T2 | 4 | T3 | 1 | ||||
auto[TlIntgErrCmd] | 104 | 1 | T69 | 1 | T70 | 3 | T71 | 4 | ||||
auto[TlIntgErrData] | 97 | 1 | T69 | 5 | T70 | 3 | T71 | 10 | ||||
auto[TlIntgErrBoth] | 99 | 1 | T69 | 4 | T70 | 4 | T71 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |