Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13459161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61502827

1

T1

144128

T2

134686

T3

222

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37374193	1			T1	79248		T2	73655		T3	692
values[0x0]	17449842	1			T1	38284		T2	35804		T3	207
values[0x1]	20137953	1			T1	40901		T2	38754		T3	418

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6705857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68256131

1

T1

151363

T2

141487

T3

786

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	256016	1			T1	627		T2	585		T3	6
valid_sources[0x01]	332638	1			T1	644		T2	607		T3	7
valid_sources[0x02]	282587	1			T1	641		T2	587		T3	3
valid_sources[0x03]	326497	1			T1	617		T2	604		T3	4
valid_sources[0x04]	262449	1			T1	647		T2	583		T3	5
valid_sources[0x05]	321686	1			T1	626		T2	567		T3	3
valid_sources[0x06]	259441	1			T1	614		T2	550		T3	3
valid_sources[0x07]	256541	1			T1	570		T2	559		T3	6
valid_sources[0x08]	270352	1			T1	618		T2	567		T3	3
valid_sources[0x09]	286115	1			T1	593		T2	623		T3	7
valid_sources[0x0a]	389167	1			T1	628		T2	603		T3	5
valid_sources[0x0b]	281686	1			T1	615		T2	604		T3	5
valid_sources[0x0c]	309237	1			T1	595		T2	570		T3	11
valid_sources[0x0d]	275555	1			T1	661		T2	561		T3	6
valid_sources[0x0e]	260987	1			T1	656		T2	584		T3	8
valid_sources[0x0f]	278196	1			T1	612		T2	559		T3	6
valid_sources[0x10]	315583	1			T1	603		T2	580		T3	11
valid_sources[0x11]	276316	1			T1	657		T2	567		T3	8
valid_sources[0x12]	373162	1			T1	670		T2	580		T3	6
valid_sources[0x13]	265155	1			T1	618		T2	567		T3	7
valid_sources[0x14]	326205	1			T1	611		T2	610		T3	5
valid_sources[0x15]	287640	1			T1	618		T2	563		T3	2
valid_sources[0x16]	271670	1			T1	634		T2	550		T3	8
valid_sources[0x17]	283892	1			T1	592		T2	596		T3	6
valid_sources[0x18]	301229	1			T1	637		T2	577		T3	6
valid_sources[0x19]	295029	1			T1	564		T2	596		T3	3
valid_sources[0x1a]	289026	1			T1	631		T2	558		T3	7
valid_sources[0x1b]	274240	1			T1	668		T2	579		T3	7
valid_sources[0x1c]	336022	1			T1	636		T2	550		T3	3
valid_sources[0x1d]	307645	1			T1	704		T2	543		T3	2
valid_sources[0x1e]	274446	1			T1	568		T2	542		T3	6
valid_sources[0x1f]	267233	1			T1	607		T2	599		T3	5
valid_sources[0x20]	285135	1			T1	585		T2	604		T3	6
valid_sources[0x21]	285514	1			T1	573		T2	618		T3	14
valid_sources[0x22]	265701	1			T1	622		T2	577		T3	3
valid_sources[0x23]	277742	1			T1	579		T2	582		T3	5
valid_sources[0x24]	277257	1			T1	598		T2	584		T3	5
valid_sources[0x25]	293860	1			T1	628		T2	586		T3	7
valid_sources[0x26]	265490	1			T1	608		T2	572		T3	5
valid_sources[0x27]	284824	1			T1	627		T2	623		T3	2
valid_sources[0x28]	263729	1			T1	584		T2	602		T3	10
valid_sources[0x29]	287566	1			T1	666		T2	614		T3	3
valid_sources[0x2a]	287683	1			T1	635		T2	611		T3	4
valid_sources[0x2b]	317688	1			T1	629		T2	599		T3	5
valid_sources[0x2c]	296743	1			T1	651		T2	551		T3	6
valid_sources[0x2d]	261169	1			T1	620		T2	606		T3	12
valid_sources[0x2e]	251597	1			T1	624		T2	581		T3	3
valid_sources[0x2f]	269901	1			T1	604		T2	561		T3	7
valid_sources[0x30]	278202	1			T1	634		T2	566		T3	5
valid_sources[0x31]	273788	1			T1	680		T2	580		T3	3
valid_sources[0x32]	274423	1			T1	641		T2	609		T3	9
valid_sources[0x33]	335800	1			T1	604		T2	590		T3	6
valid_sources[0x34]	282443	1			T1	618		T2	614		T3	5
valid_sources[0x35]	279165	1			T1	636		T2	554		T3	5
valid_sources[0x36]	351471	1			T1	660		T2	561		T3	5
valid_sources[0x37]	309145	1			T1	581		T2	582		T3	3
valid_sources[0x38]	324955	1			T1	637		T2	546		T3	5
valid_sources[0x39]	328313	1			T1	597		T2	597		T3	5
valid_sources[0x3a]	318769	1			T1	660		T2	600		T3	9
valid_sources[0x3b]	352390	1			T1	667		T2	558		T3	2
valid_sources[0x3c]	284539	1			T1	588		T2	555		T3	4
valid_sources[0x3d]	347387	1			T1	634		T2	587		T3	5
valid_sources[0x3e]	272871	1			T1	577		T2	602		T3	5
valid_sources[0x3f]	283971	1			T1	614		T2	600		T3	4
valid_sources[0x40]	293777	1			T1	618		T2	626		T3	7
valid_sources[0x41]	293760	1			T1	635		T2	581		T3	3
valid_sources[0x42]	345227	1			T1	633		T2	577		T3	5
valid_sources[0x43]	265555	1			T1	618		T2	627		T3	4
valid_sources[0x44]	275181	1			T1	644		T2	567		T3	4
valid_sources[0x45]	262460	1			T1	633		T2	564		T3	2
valid_sources[0x46]	322559	1			T1	630		T2	519		T3	4
valid_sources[0x47]	278292	1			T1	643		T2	568		T3	5
valid_sources[0x48]	285415	1			T1	600		T2	602		T3	7
valid_sources[0x49]	261919	1			T1	576		T2	566		T3	5
valid_sources[0x4a]	313950	1			T1	633		T2	569		T3	8
valid_sources[0x4b]	277498	1			T1	648		T2	558		T3	5
valid_sources[0x4c]	292526	1			T1	618		T2	583		T3	6
valid_sources[0x4d]	350164	1			T1	639		T2	565		T3	5
valid_sources[0x4e]	272196	1			T1	576		T2	600		T3	7
valid_sources[0x4f]	319510	1			T1	631		T2	562		T3	3
valid_sources[0x50]	287561	1			T1	607		T2	573		T3	9
valid_sources[0x51]	261676	1			T1	576		T2	595		T3	6
valid_sources[0x52]	322035	1			T1	624		T2	569		T3	4
valid_sources[0x53]	261266	1			T1	642		T2	601		T3	10
valid_sources[0x54]	276786	1			T1	600		T2	587		T7	173
valid_sources[0x55]	277555	1			T1	635		T2	585		T3	4
valid_sources[0x56]	295052	1			T1	671		T2	544		T3	3
valid_sources[0x57]	284755	1			T1	615		T2	574		T3	2
valid_sources[0x58]	350567	1			T1	601		T2	589		T3	9
valid_sources[0x59]	275235	1			T1	563		T2	618		T3	8
valid_sources[0x5a]	259736	1			T1	616		T2	589		T3	9
valid_sources[0x5b]	265679	1			T1	636		T2	563		T3	7
valid_sources[0x5c]	386624	1			T1	568		T2	582		T3	2
valid_sources[0x5d]	372076	1			T1	619		T2	614		T3	3
valid_sources[0x5e]	311439	1			T1	586		T2	577		T3	4
valid_sources[0x5f]	273220	1			T1	652		T2	598		T3	2
valid_sources[0x60]	310830	1			T1	611		T2	582		T3	3
valid_sources[0x61]	298355	1			T1	655		T2	546		T3	8
valid_sources[0x62]	262992	1			T1	636		T2	545		T3	3
valid_sources[0x63]	272031	1			T1	582		T2	576		T3	8
valid_sources[0x64]	301466	1			T1	620		T2	552		T3	4
valid_sources[0x65]	304838	1			T1	592		T2	581		T3	5
valid_sources[0x66]	301572	1			T1	569		T2	577		T3	6
valid_sources[0x67]	301587	1			T1	631		T2	552		T3	5
valid_sources[0x68]	315597	1			T1	620		T2	632		T3	5
valid_sources[0x69]	272657	1			T1	583		T2	623		T3	3
valid_sources[0x6a]	298214	1			T1	608		T2	575		T3	7
valid_sources[0x6b]	301491	1			T1	625		T2	581		T3	1
valid_sources[0x6c]	299606	1			T1	654		T2	600		T3	5
valid_sources[0x6d]	280007	1			T1	586		T2	627		T3	5
valid_sources[0x6e]	281436	1			T1	627		T2	546		T3	7
valid_sources[0x6f]	260944	1			T1	633		T2	606		T3	2
valid_sources[0x70]	305067	1			T1	607		T2	561		T3	6
valid_sources[0x71]	272040	1			T1	587		T2	587		T3	7
valid_sources[0x72]	289821	1			T1	592		T2	624		T3	4
valid_sources[0x73]	307334	1			T1	659		T2	540		T3	4
valid_sources[0x74]	271383	1			T1	613		T2	612		T3	7
valid_sources[0x75]	298781	1			T1	596		T2	607		T3	2
valid_sources[0x76]	312239	1			T1	650		T2	541		T3	6
valid_sources[0x77]	290255	1			T1	642		T2	613		T3	4
valid_sources[0x78]	253371	1			T1	601		T2	582		T3	3
valid_sources[0x79]	294484	1			T1	597		T2	551		T3	5
valid_sources[0x7a]	341151	1			T1	581		T2	600		T3	1
valid_sources[0x7b]	285535	1			T1	630		T2	559		T3	8
valid_sources[0x7c]	286093	1			T1	623		T2	545		T3	6
valid_sources[0x7d]	279423	1			T1	642		T2	575		T3	1
valid_sources[0x7e]	289413	1			T1	636		T2	595		T3	3
valid_sources[0x7f]	307714	1			T1	633		T2	570		T3	3
valid_sources[0x80]	281951	1			T1	612		T2	545		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30647461

1

T1

72030

T2

66993

T3

121

values[0x0]

all_enables

biggest_size

15429077

1

T1

36111

T2

33698

T3

48

values[0x1]

all_enables

biggest_size

15426289

1

T1

35987

T2

33995

T3

53

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37060	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

136146

1

T1

18

T2

1

T7

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50520	1			T1	12		T4	2		T5	20
values[0x0]	59220	1			T1	20		T2	3		T7	3
values[0x1]	63466	1			T1	26		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28113	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145093

1

T1

26

T2

1

T7

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	673	1			T25	5		T62	5		T26	5
valid_sources[0x01]	540	1			T19	1		T6	1		T25	4
valid_sources[0x02]	535	1			T90	1		T25	6		T51	1
valid_sources[0x03]	560	1			T25	2		T22	1		T26	6
valid_sources[0x04]	773	1			T1	1		T2	4		T6	4
valid_sources[0x05]	647	1			T6	2		T90	1		T25	6
valid_sources[0x06]	636	1			T6	2		T90	1		T25	3
valid_sources[0x07]	578	1			T19	3		T25	2		T59	35
valid_sources[0x08]	631	1			T19	2		T25	3		T26	7
valid_sources[0x09]	559	1			T25	2		T78	1		T22	3
valid_sources[0x0a]	515	1			T25	3		T26	10		T59	41
valid_sources[0x0b]	880	1			T19	2		T25	1		T45	1
valid_sources[0x0c]	702	1			T25	2		T22	1		T26	5
valid_sources[0x0d]	543	1			T6	2		T25	1		T26	4
valid_sources[0x0e]	704	1			T11	1		T6	2		T25	5
valid_sources[0x0f]	931	1			T25	1		T45	1		T22	1
valid_sources[0x10]	589	1			T19	2		T6	1		T25	3
valid_sources[0x11]	498	1			T6	1		T25	2		T22	5
valid_sources[0x12]	542	1			T139	1		T25	5		T78	1
valid_sources[0x13]	691	1			T25	4		T22	129		T26	7
valid_sources[0x14]	463	1			T6	1		T90	1		T139	2
valid_sources[0x15]	743	1			T1	1		T25	3		T22	92
valid_sources[0x16]	566	1			T25	7		T45	1		T15	1
valid_sources[0x17]	707	1			T6	1		T90	1		T25	3
valid_sources[0x18]	847	1			T19	1		T90	2		T25	1
valid_sources[0x19]	624	1			T5	1		T19	4		T25	2
valid_sources[0x1a]	763	1			T25	4		T22	102		T26	8
valid_sources[0x1b]	907	1			T12	1		T19	3		T90	1
valid_sources[0x1c]	638	1			T1	1		T25	1		T140	1
valid_sources[0x1d]	732	1			T6	2		T25	7		T22	5
valid_sources[0x1e]	542	1			T41	2		T6	1		T25	1
valid_sources[0x1f]	678	1			T25	5		T22	2		T26	4
valid_sources[0x20]	860	1			T19	1		T25	5		T62	1
valid_sources[0x21]	588	1			T90	3		T25	3		T62	7
valid_sources[0x22]	748	1			T25	4		T26	8		T43	1
valid_sources[0x23]	804	1			T1	2		T12	1		T6	1
valid_sources[0x24]	622	1			T5	1		T19	4		T25	3
valid_sources[0x25]	832	1			T6	3		T25	3		T27	1
valid_sources[0x26]	661	1			T25	1		T22	4		T26	4
valid_sources[0x27]	521	1			T1	6		T6	1		T25	3
valid_sources[0x28]	657	1			T25	5		T63	1		T22	4
valid_sources[0x29]	471	1			T19	2		T90	1		T25	3
valid_sources[0x2a]	704	1			T1	1		T25	2		T26	4
valid_sources[0x2b]	454	1			T25	2		T22	2		T26	5
valid_sources[0x2c]	559	1			T25	5		T22	57		T26	9
valid_sources[0x2d]	613	1			T19	1		T25	5		T22	50
valid_sources[0x2e]	737	1			T90	1		T25	7		T26	8
valid_sources[0x2f]	1091	1			T1	1		T19	4		T6	1
valid_sources[0x30]	534	1			T25	2		T22	3		T26	4
valid_sources[0x31]	899	1			T90	2		T25	1		T51	1
valid_sources[0x32]	741	1			T19	2		T6	1		T25	3
valid_sources[0x33]	625	1			T1	1		T19	1		T6	1
valid_sources[0x34]	960	1			T12	1		T6	1		T25	3
valid_sources[0x35]	813	1			T19	2		T25	2		T62	4
valid_sources[0x36]	676	1			T25	4		T62	2		T22	3
valid_sources[0x37]	491	1			T25	3		T52	3		T26	2
valid_sources[0x38]	574	1			T25	2		T22	3		T26	10
valid_sources[0x39]	672	1			T1	2		T25	2		T22	2
valid_sources[0x3a]	548	1			T19	2		T90	1		T25	5
valid_sources[0x3b]	658	1			T19	2		T25	6		T22	100
valid_sources[0x3c]	851	1			T19	2		T25	2		T22	4
valid_sources[0x3d]	675	1			T25	2		T22	3		T26	7
valid_sources[0x3e]	700	1			T6	1		T115	1		T25	2
valid_sources[0x3f]	455	1			T25	5		T22	12		T26	9
valid_sources[0x40]	683	1			T6	1		T25	4		T22	5
valid_sources[0x41]	880	1			T25	5		T141	1		T22	193
valid_sources[0x42]	774	1			T1	1		T12	1		T6	1
valid_sources[0x43]	610	1			T1	1		T22	3		T26	5
valid_sources[0x44]	796	1			T12	1		T5	1		T19	2
valid_sources[0x45]	517	1			T12	1		T5	1		T6	1
valid_sources[0x46]	696	1			T12	1		T19	5		T6	3
valid_sources[0x47]	624	1			T5	1		T6	1		T90	1
valid_sources[0x48]	680	1			T6	2		T25	2		T26	6
valid_sources[0x49]	814	1			T19	2		T6	2		T25	4
valid_sources[0x4a]	568	1			T12	1		T19	2		T25	5
valid_sources[0x4b]	749	1			T6	1		T25	3		T22	1
valid_sources[0x4c]	702	1			T7	2		T25	3		T51	1
valid_sources[0x4d]	668	1			T1	3		T25	1		T26	7
valid_sources[0x4e]	751	1			T1	1		T25	1		T22	94
valid_sources[0x4f]	525	1			T9	20		T25	4		T78	1
valid_sources[0x50]	595	1			T6	1		T25	1		T22	2
valid_sources[0x51]	690	1			T1	1		T5	1		T25	4
valid_sources[0x52]	626	1			T19	2		T25	4		T79	15
valid_sources[0x53]	842	1			T1	1		T19	1		T90	1
valid_sources[0x54]	910	1			T19	4		T6	1		T90	1
valid_sources[0x55]	920	1			T6	1		T25	3		T22	102
valid_sources[0x56]	566	1			T5	1		T19	3		T6	1
valid_sources[0x57]	525	1			T19	1		T25	2		T62	2
valid_sources[0x58]	747	1			T19	3		T6	1		T25	1
valid_sources[0x59]	657	1			T1	1		T25	2		T78	1
valid_sources[0x5a]	565	1			T90	1		T25	2		T62	3
valid_sources[0x5b]	701	1			T25	2		T22	6		T26	1
valid_sources[0x5c]	708	1			T6	1		T90	2		T25	3
valid_sources[0x5d]	806	1			T19	1		T25	4		T22	15
valid_sources[0x5e]	526	1			T5	2		T19	2		T6	1
valid_sources[0x5f]	877	1			T6	1		T25	3		T22	2
valid_sources[0x60]	651	1			T1	1		T25	1		T26	6
valid_sources[0x61]	630	1			T25	1		T51	1		T22	1
valid_sources[0x62]	613	1			T19	1		T25	5		T22	3
valid_sources[0x63]	931	1			T5	2		T139	3		T25	4
valid_sources[0x64]	560	1			T1	2		T7	2		T19	1
valid_sources[0x65]	558	1			T5	1		T73	2		T6	1
valid_sources[0x66]	1249	1			T19	1		T6	1		T25	5
valid_sources[0x67]	763	1			T6	2		T25	2		T45	1
valid_sources[0x68]	590	1			T5	1		T25	2		T79	3
valid_sources[0x69]	819	1			T19	2		T6	1		T25	2
valid_sources[0x6a]	631	1			T5	1		T6	2		T22	1
valid_sources[0x6b]	656	1			T1	1		T19	2		T6	3
valid_sources[0x6c]	539	1			T19	2		T90	1		T139	1
valid_sources[0x6d]	742	1			T5	2		T139	2		T25	3
valid_sources[0x6e]	516	1			T6	1		T25	3		T26	8
valid_sources[0x6f]	580	1			T19	1		T25	1		T22	2
valid_sources[0x70]	498	1			T25	3		T45	1		T22	6
valid_sources[0x71]	583	1			T25	1		T26	3		T57	28
valid_sources[0x72]	660	1			T1	2		T10	48		T25	5
valid_sources[0x73]	522	1			T1	1		T25	4		T62	1
valid_sources[0x74]	517	1			T25	3		T62	1		T26	10
valid_sources[0x75]	496	1			T25	2		T26	8		T57	7
valid_sources[0x76]	540	1			T6	1		T25	2		T22	2
valid_sources[0x77]	582	1			T6	4		T25	1		T78	1
valid_sources[0x78]	692	1			T7	1		T25	3		T26	2
valid_sources[0x79]	599	1			T6	2		T25	1		T63	1
valid_sources[0x7a]	855	1			T1	1		T4	2		T6	1
valid_sources[0x7b]	631	1			T6	2		T44	2		T25	1
valid_sources[0x7c]	475	1			T6	1		T25	2		T22	1
valid_sources[0x7d]	868	1			T5	1		T72	185		T25	1
valid_sources[0x7e]	785	1			T19	2		T90	1		T139	2
valid_sources[0x7f]	851	1			T19	3		T6	1		T90	1
valid_sources[0x80]	835	1			T19	4		T90	1		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37530

1

T1

8

T4

1

T5

8

values[0x0]

all_enables

biggest_size

50453

1

T1

6

T2

1

T7

1

values[0x1]

all_enables

biggest_size

48163

1

T1

4

T7

1

T8

3