Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
13144902 |
1 |
|
|
T1 |
11380 |
|
T2 |
13527 |
|
T3 |
1095 |
full_word |
56591264 |
1 |
|
|
T1 |
115549 |
|
T2 |
134686 |
|
T3 |
222 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
69735866 |
1 |
|
|
T1 |
126929 |
|
T2 |
148213 |
|
T3 |
1317 |
auto[TlIntgErrCmd] |
100 |
1 |
|
|
T69 |
5 |
|
T70 |
3 |
|
T71 |
9 |
auto[TlIntgErrData] |
92 |
1 |
|
|
T70 |
1 |
|
T71 |
5 |
|
T128 |
1 |
auto[TlIntgErrBoth] |
108 |
1 |
|
|
T69 |
5 |
|
T70 |
6 |
|
T71 |
6 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32095675 |
1 |
|
|
T1 |
47744 |
|
T2 |
73655 |
|
T3 |
692 |
auto[1] |
37640491 |
1 |
|
|
T1 |
79185 |
|
T2 |
74558 |
|
T3 |
625 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
6278635 |
1 |
|
|
T1 |
4293 |
|
T2 |
6662 |
|
T3 |
571 |
auto[TlIntgErrNone] |
partial |
auto[1] |
6865994 |
1 |
|
|
T1 |
7087 |
|
T2 |
6865 |
|
T3 |
524 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
25816894 |
1 |
|
|
T1 |
43451 |
|
T2 |
66993 |
|
T3 |
121 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
30774343 |
1 |
|
|
T1 |
72098 |
|
T2 |
67693 |
|
T3 |
101 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
42 |
1 |
|
|
T69 |
2 |
|
T70 |
1 |
|
T71 |
4 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
47 |
1 |
|
|
T69 |
3 |
|
T70 |
1 |
|
T71 |
4 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
5 |
1 |
|
|
T71 |
1 |
|
T129 |
1 |
|
T131 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
6 |
1 |
|
|
T70 |
1 |
|
T129 |
1 |
|
T127 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
49 |
1 |
|
|
T70 |
1 |
|
T71 |
4 |
|
T126 |
5 |
auto[TlIntgErrData] |
partial |
auto[1] |
37 |
1 |
|
|
T71 |
1 |
|
T128 |
1 |
|
T126 |
5 |
auto[TlIntgErrData] |
full_word |
auto[0] |
4 |
1 |
|
|
T127 |
1 |
|
T132 |
2 |
|
T133 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
2 |
1 |
|
|
T131 |
1 |
|
T132 |
1 |
|
- |
- |
auto[TlIntgErrBoth] |
partial |
auto[0] |
42 |
1 |
|
|
T70 |
1 |
|
T71 |
1 |
|
T128 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
56 |
1 |
|
|
T69 |
4 |
|
T70 |
1 |
|
T71 |
5 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
4 |
1 |
|
|
T69 |
1 |
|
T70 |
1 |
|
T127 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
6 |
1 |
|
|
T70 |
3 |
|
T134 |
2 |
|
T133 |
1 |