Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	625201	1			T1	2462		T3	36		T10	26
auto[1]	11244413	1			T1	541		T2	61133		T3	101
auto[2]	524775	1			T1	2265		T3	26		T10	34
auto[3]	11155215	1			T1	334		T2	62160		T3	70

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15794824	1			T1	4335		T2	102561		T3	6
auto[1]	2191260	1			T1	614		T2	10006		T3	24
auto[2]	2213586	1			T1	570		T2	9813		T3	20
auto[3]	3349934	1			T1	83		T2	913		T3	183

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10122641

1

T1

5597

T2

33

T3

233

auto[1]

13426963

1

T1

5

T2

123260

T7

18

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	221837	1			T1	2001		T3	2		T10	20
auto[0]	auto[0]	auto[1]	23149	1			T1	211		T3	7		T10	3
auto[0]	auto[0]	auto[2]	23330	1			T1	218		T10	3		T19	390
auto[0]	auto[0]	auto[3]	8517	1			T1	31		T3	27		T19	56
auto[0]	auto[1]	auto[0]	3957125	1			T1	298		T2	18		T3	3
auto[0]	auto[1]	auto[1]	397483	1			T1	193		T3	15		T7	751
auto[0]	auto[1]	auto[2]	397006	1			T1	29		T2	3		T3	10
auto[0]	auto[1]	auto[3]	71033	1			T1	20		T3	73		T7	81
auto[0]	auto[2]	auto[0]	186123	1			T1	1880		T5	1		T19	3319
auto[0]	auto[2]	auto[1]	19386	1			T1	197		T19	363		T137	68
auto[0]	auto[2]	auto[2]	22769	1			T1	166		T3	3		T10	33
auto[0]	auto[2]	auto[3]	7160	1			T1	19		T3	23		T10	1
auto[0]	auto[3]	auto[0]	3925474	1			T1	151		T2	12		T3	1
auto[0]	auto[3]	auto[1]	392557	1			T1	13		T3	2		T7	735
auto[0]	auto[3]	auto[2]	397338	1			T1	157		T3	7		T7	728
auto[0]	auto[3]	auto[3]	72354	1			T1	13		T3	60		T7	67
auto[1]	auto[0]	auto[0]	11865	1			T1	1		T19	5		T42	504
auto[1]	auto[0]	auto[1]	51765	1			T42	2443		T115	1741		T138	1439
auto[1]	auto[0]	auto[2]	52228	1			T42	2451		T115	1847		T62	1
auto[1]	auto[0]	auto[3]	232510	1			T42	10916		T115	8025		T138	6273
auto[1]	auto[1]	auto[0]	3743347	1			T1	1		T2	50842		T7	9
auto[1]	auto[1]	auto[1]	651481	1			T2	4710		T8	6		T40	8273
auto[1]	auto[1]	auto[2]	632643	1			T2	5088		T8	2		T40	8034
auto[1]	auto[1]	auto[3]	1394295	1			T2	472		T8	1		T40	36608
auto[1]	auto[2]	auto[0]	8433	1			T1	3		T19	4		T42	495
auto[1]	auto[2]	auto[1]	37152	1			T19	2		T42	2201		T115	1565
auto[1]	auto[2]	auto[2]	44529	1			T42	2005		T115	1529		T23	2
auto[1]	auto[2]	auto[3]	199223	1			T42	9162		T115	6715		T138	4237
auto[1]	auto[3]	auto[0]	3740620	1			T2	51689		T7	7		T8	44
auto[1]	auto[3]	auto[1]	618287	1			T2	5296		T7	1		T8	4
auto[1]	auto[3]	auto[2]	643743	1			T2	4722		T7	1		T8	1
auto[1]	auto[3]	auto[3]	1364842	1			T2	441		T40	36677		T42	9420