Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	302487483	195274	0	0
ctrl_regwen_rd_A	302487483	4077	0	0
exec_rd_A	302487483	3988	0	0
exec_regwen_rd_A	302487483	4374	0	0
readback_rd_A	302487483	2640	0	0
readback_regwen_rd_A	302487483	2324	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302487483	195274	0	0
T22	0	12678	0	0
T25	22342	919	0	0
T26	0	1587	0	0
T27	2475	0	0	0
T45	64801	0	0	0
T46	9241	0	0	0
T56	0	4947	0	0
T57	0	3433	0	0
T59	0	9673	0	0
T61	91438	0	0	0
T62	166791	0	0	0
T63	11890	0	0	0
T64	14659	0	0	0
T65	8193	0	0	0
T67	0	1549	0	0
T68	0	3258	0	0
T76	0	3725	0	0
T77	0	4868	0	0
T78	137785	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302487483	4077	0	0
T25	22342	91	0	0
T26	0	102	0	0
T27	2475	0	0	0
T45	64801	0	0	0
T46	9241	0	0	0
T61	91438	0	0	0
T62	166791	0	0	0
T63	11890	0	0	0
T64	14659	0	0	0
T65	8193	0	0	0
T67	0	86	0	0
T68	0	307	0	0
T76	0	308	0	0
T78	137785	0	0	0
T120	0	125	0	0
T121	0	300	0	0
T122	0	96	0	0
T123	0	69	0	0
T124	0	159	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302487483	3988	0	0
T25	22342	86	0	0
T26	0	92	0	0
T27	2475	0	0	0
T45	64801	0	0	0
T46	9241	0	0	0
T61	91438	0	0	0
T62	166791	0	0	0
T63	11890	0	0	0
T64	14659	0	0	0
T65	8193	0	0	0
T67	0	61	0	0
T68	0	266	0	0
T76	0	251	0	0
T78	137785	0	0	0
T120	0	122	0	0
T121	0	310	0	0
T122	0	107	0	0
T123	0	61	0	0
T124	0	104	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302487483	4374	0	0
T25	22342	79	0	0
T26	0	131	0	0
T27	2475	0	0	0
T45	64801	0	0	0
T46	9241	0	0	0
T61	91438	0	0	0
T62	166791	0	0	0
T63	11890	0	0	0
T64	14659	0	0	0
T65	8193	0	0	0
T67	0	60	0	0
T68	0	384	0	0
T76	0	249	0	0
T78	137785	0	0	0
T120	0	154	0	0
T121	0	329	0	0
T122	0	87	0	0
T123	0	104	0	0
T124	0	117	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302487483	2640	0	0
T25	22342	125	0	0
T26	0	145	0	0
T27	2475	0	0	0
T45	64801	0	0	0
T46	9241	0	0	0
T61	91438	0	0	0
T62	166791	0	0	0
T63	11890	0	0	0
T64	14659	0	0	0
T65	8193	0	0	0
T67	0	48	0	0
T68	0	275	0	0
T76	0	287	0	0
T78	137785	0	0	0
T120	0	144	0	0
T121	0	279	0	0
T122	0	88	0	0
T123	0	128	0	0
T124	0	139	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302487483	2324	0	0
T25	22342	42	0	0
T26	0	146	0	0
T27	2475	0	0	0
T45	64801	0	0	0
T46	9241	0	0	0
T61	91438	0	0	0
T62	166791	0	0	0
T63	11890	0	0	0
T64	14659	0	0	0
T65	8193	0	0	0
T67	0	63	0	0
T68	0	236	0	0
T76	0	286	0	0
T78	137785	0	0	0
T120	0	83	0	0
T121	0	248	0	0
T122	0	69	0	0
T123	0	65	0	0
T124	0	180	0	0