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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.98 99.16 94.27 99.72 100.00 95.95 99.12 97.62


Total test records in report: 1030
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T796 /workspace/coverage/default/41.sram_ctrl_multiple_keys.1050171624 Jul 16 07:44:27 PM PDT 24 Jul 16 08:03:24 PM PDT 24 282339463125 ps
T797 /workspace/coverage/default/0.sram_ctrl_partial_access.3353321041 Jul 16 07:41:07 PM PDT 24 Jul 16 07:42:07 PM PDT 24 493437777 ps
T798 /workspace/coverage/default/11.sram_ctrl_partial_access.1896413589 Jul 16 07:41:58 PM PDT 24 Jul 16 07:44:42 PM PDT 24 3304857680 ps
T799 /workspace/coverage/default/7.sram_ctrl_partial_access.3593518880 Jul 16 07:41:23 PM PDT 24 Jul 16 07:42:39 PM PDT 24 1656987223 ps
T800 /workspace/coverage/default/39.sram_ctrl_mem_walk.274320110 Jul 16 07:44:24 PM PDT 24 Jul 16 07:44:31 PM PDT 24 273024059 ps
T801 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2906840662 Jul 16 07:43:42 PM PDT 24 Jul 16 07:49:31 PM PDT 24 4683149582 ps
T802 /workspace/coverage/default/40.sram_ctrl_partial_access.2127984976 Jul 16 07:44:23 PM PDT 24 Jul 16 07:44:47 PM PDT 24 13979691987 ps
T803 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.859247822 Jul 16 07:44:11 PM PDT 24 Jul 16 07:44:33 PM PDT 24 346727811 ps
T804 /workspace/coverage/default/1.sram_ctrl_ram_cfg.242401645 Jul 16 07:41:11 PM PDT 24 Jul 16 07:41:25 PM PDT 24 49577503 ps
T805 /workspace/coverage/default/24.sram_ctrl_stress_all.703262055 Jul 16 07:42:53 PM PDT 24 Jul 16 08:01:27 PM PDT 24 18316306978 ps
T806 /workspace/coverage/default/27.sram_ctrl_max_throughput.885826382 Jul 16 07:42:53 PM PDT 24 Jul 16 07:44:18 PM PDT 24 134361978 ps
T807 /workspace/coverage/default/36.sram_ctrl_multiple_keys.3924640097 Jul 16 07:43:56 PM PDT 24 Jul 16 08:09:36 PM PDT 24 12531347692 ps
T808 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.998224049 Jul 16 07:41:29 PM PDT 24 Jul 16 07:44:51 PM PDT 24 11817813616 ps
T809 /workspace/coverage/default/2.sram_ctrl_smoke.106286913 Jul 16 07:41:13 PM PDT 24 Jul 16 07:41:32 PM PDT 24 309932862 ps
T810 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.669407104 Jul 16 07:41:57 PM PDT 24 Jul 16 07:42:33 PM PDT 24 699439355 ps
T811 /workspace/coverage/default/31.sram_ctrl_stress_all.2973160299 Jul 16 07:43:20 PM PDT 24 Jul 16 08:50:20 PM PDT 24 15058595320 ps
T812 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4101484816 Jul 16 07:45:01 PM PDT 24 Jul 16 07:46:16 PM PDT 24 125147029 ps
T813 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4056816605 Jul 16 07:41:08 PM PDT 24 Jul 16 07:45:00 PM PDT 24 5188671891 ps
T814 /workspace/coverage/default/26.sram_ctrl_smoke.1043226515 Jul 16 07:42:51 PM PDT 24 Jul 16 07:43:18 PM PDT 24 1144308310 ps
T815 /workspace/coverage/default/15.sram_ctrl_ram_cfg.27186488 Jul 16 07:41:51 PM PDT 24 Jul 16 07:42:04 PM PDT 24 44807381 ps
T816 /workspace/coverage/default/6.sram_ctrl_bijection.3800392001 Jul 16 07:41:25 PM PDT 24 Jul 16 07:42:48 PM PDT 24 1863818040 ps
T817 /workspace/coverage/default/34.sram_ctrl_smoke.1074046757 Jul 16 07:43:37 PM PDT 24 Jul 16 07:44:30 PM PDT 24 492368804 ps
T818 /workspace/coverage/default/38.sram_ctrl_ram_cfg.2748356585 Jul 16 07:44:13 PM PDT 24 Jul 16 07:44:16 PM PDT 24 108458060 ps
T819 /workspace/coverage/default/42.sram_ctrl_regwen.423735138 Jul 16 07:44:38 PM PDT 24 Jul 16 07:54:15 PM PDT 24 7023494012 ps
T820 /workspace/coverage/default/1.sram_ctrl_smoke.3149443664 Jul 16 07:41:08 PM PDT 24 Jul 16 07:41:24 PM PDT 24 491689582 ps
T821 /workspace/coverage/default/34.sram_ctrl_alert_test.1786600990 Jul 16 07:43:36 PM PDT 24 Jul 16 07:43:41 PM PDT 24 12919253 ps
T822 /workspace/coverage/default/39.sram_ctrl_lc_escalation.4020340123 Jul 16 07:44:11 PM PDT 24 Jul 16 07:44:19 PM PDT 24 959440222 ps
T823 /workspace/coverage/default/4.sram_ctrl_mem_walk.2365752287 Jul 16 07:41:24 PM PDT 24 Jul 16 07:41:54 PM PDT 24 363890631 ps
T824 /workspace/coverage/default/48.sram_ctrl_mem_walk.2869759967 Jul 16 07:46:21 PM PDT 24 Jul 16 07:46:36 PM PDT 24 1641856757 ps
T825 /workspace/coverage/default/23.sram_ctrl_executable.2282118782 Jul 16 07:42:42 PM PDT 24 Jul 16 08:00:43 PM PDT 24 15864747144 ps
T826 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1263547155 Jul 16 07:43:53 PM PDT 24 Jul 16 07:45:53 PM PDT 24 577212875 ps
T827 /workspace/coverage/default/34.sram_ctrl_stress_all.1214132151 Jul 16 07:43:37 PM PDT 24 Jul 16 08:18:54 PM PDT 24 12254386065 ps
T828 /workspace/coverage/default/45.sram_ctrl_lc_escalation.4205583260 Jul 16 07:45:00 PM PDT 24 Jul 16 07:45:04 PM PDT 24 431820506 ps
T829 /workspace/coverage/default/49.sram_ctrl_multiple_keys.475020689 Jul 16 07:46:18 PM PDT 24 Jul 16 07:59:48 PM PDT 24 12483398141 ps
T830 /workspace/coverage/default/35.sram_ctrl_executable.1212815262 Jul 16 07:43:52 PM PDT 24 Jul 16 08:15:37 PM PDT 24 122713157800 ps
T831 /workspace/coverage/default/46.sram_ctrl_alert_test.2643282949 Jul 16 07:45:34 PM PDT 24 Jul 16 07:45:37 PM PDT 24 23989280 ps
T832 /workspace/coverage/default/28.sram_ctrl_smoke.2819730130 Jul 16 07:43:04 PM PDT 24 Jul 16 07:43:24 PM PDT 24 3934543531 ps
T833 /workspace/coverage/default/27.sram_ctrl_executable.4217840729 Jul 16 07:42:53 PM PDT 24 Jul 16 08:00:28 PM PDT 24 9214201107 ps
T834 /workspace/coverage/default/40.sram_ctrl_max_throughput.1209495436 Jul 16 07:44:27 PM PDT 24 Jul 16 07:45:52 PM PDT 24 462761190 ps
T835 /workspace/coverage/default/24.sram_ctrl_max_throughput.3131054429 Jul 16 07:42:37 PM PDT 24 Jul 16 07:43:57 PM PDT 24 214322632 ps
T836 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3273389390 Jul 16 07:45:32 PM PDT 24 Jul 16 07:45:56 PM PDT 24 346299578 ps
T837 /workspace/coverage/default/12.sram_ctrl_partial_access.3767424050 Jul 16 07:41:49 PM PDT 24 Jul 16 07:43:25 PM PDT 24 180925230 ps
T838 /workspace/coverage/default/11.sram_ctrl_alert_test.3392171580 Jul 16 07:41:57 PM PDT 24 Jul 16 07:42:09 PM PDT 24 34327627 ps
T839 /workspace/coverage/default/14.sram_ctrl_partial_access.4218235908 Jul 16 07:41:57 PM PDT 24 Jul 16 07:42:38 PM PDT 24 342165507 ps
T840 /workspace/coverage/default/12.sram_ctrl_bijection.1289703789 Jul 16 07:41:48 PM PDT 24 Jul 16 07:42:43 PM PDT 24 9970306745 ps
T841 /workspace/coverage/default/34.sram_ctrl_max_throughput.2155657392 Jul 16 07:43:37 PM PDT 24 Jul 16 07:45:29 PM PDT 24 138690683 ps
T842 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3780391811 Jul 16 07:41:54 PM PDT 24 Jul 16 07:50:12 PM PDT 24 6577569863 ps
T843 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3266240909 Jul 16 07:43:21 PM PDT 24 Jul 16 07:47:43 PM PDT 24 3767839413 ps
T844 /workspace/coverage/default/32.sram_ctrl_alert_test.921443827 Jul 16 07:43:34 PM PDT 24 Jul 16 07:43:36 PM PDT 24 30153175 ps
T845 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3159312990 Jul 16 07:43:35 PM PDT 24 Jul 16 07:43:42 PM PDT 24 173141488 ps
T846 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1859586139 Jul 16 07:44:13 PM PDT 24 Jul 16 07:48:31 PM PDT 24 17826251664 ps
T847 /workspace/coverage/default/37.sram_ctrl_stress_all.545937013 Jul 16 07:44:13 PM PDT 24 Jul 16 07:50:18 PM PDT 24 22974938202 ps
T848 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3613624307 Jul 16 07:42:06 PM PDT 24 Jul 16 07:48:43 PM PDT 24 20129287246 ps
T849 /workspace/coverage/default/6.sram_ctrl_multiple_keys.865039827 Jul 16 07:41:27 PM PDT 24 Jul 16 08:13:21 PM PDT 24 36235742295 ps
T850 /workspace/coverage/default/40.sram_ctrl_multiple_keys.2224023219 Jul 16 07:44:24 PM PDT 24 Jul 16 08:01:10 PM PDT 24 31671935862 ps
T851 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2999125401 Jul 16 07:43:55 PM PDT 24 Jul 16 07:48:55 PM PDT 24 47493880338 ps
T852 /workspace/coverage/default/2.sram_ctrl_partial_access.3491499777 Jul 16 07:41:14 PM PDT 24 Jul 16 07:42:40 PM PDT 24 163200151 ps
T853 /workspace/coverage/default/10.sram_ctrl_regwen.2744385781 Jul 16 07:41:50 PM PDT 24 Jul 16 08:01:50 PM PDT 24 13726378782 ps
T854 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2711488760 Jul 16 07:43:52 PM PDT 24 Jul 16 07:45:28 PM PDT 24 594014477 ps
T855 /workspace/coverage/default/6.sram_ctrl_smoke.84498097 Jul 16 07:41:24 PM PDT 24 Jul 16 07:41:57 PM PDT 24 2815224493 ps
T856 /workspace/coverage/default/4.sram_ctrl_regwen.3722777863 Jul 16 07:41:17 PM PDT 24 Jul 16 07:45:20 PM PDT 24 9576673374 ps
T857 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2196356797 Jul 16 07:46:20 PM PDT 24 Jul 16 07:46:28 PM PDT 24 202405786 ps
T858 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3953847191 Jul 16 07:41:20 PM PDT 24 Jul 16 07:48:37 PM PDT 24 61605938967 ps
T859 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.334608083 Jul 16 07:44:24 PM PDT 24 Jul 16 07:44:47 PM PDT 24 876988702 ps
T860 /workspace/coverage/default/44.sram_ctrl_lc_escalation.4260891582 Jul 16 07:45:01 PM PDT 24 Jul 16 07:45:04 PM PDT 24 267644563 ps
T861 /workspace/coverage/default/1.sram_ctrl_regwen.2585233061 Jul 16 07:41:11 PM PDT 24 Jul 16 07:52:20 PM PDT 24 18837247683 ps
T862 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4041036392 Jul 16 07:44:41 PM PDT 24 Jul 16 07:54:17 PM PDT 24 12790418998 ps
T863 /workspace/coverage/default/20.sram_ctrl_smoke.2793352864 Jul 16 07:42:23 PM PDT 24 Jul 16 07:42:43 PM PDT 24 598106910 ps
T864 /workspace/coverage/default/17.sram_ctrl_lc_escalation.2443841262 Jul 16 07:42:08 PM PDT 24 Jul 16 07:42:24 PM PDT 24 8211616702 ps
T865 /workspace/coverage/default/29.sram_ctrl_mem_walk.1039720702 Jul 16 07:43:06 PM PDT 24 Jul 16 07:43:22 PM PDT 24 2265181140 ps
T866 /workspace/coverage/default/34.sram_ctrl_mem_walk.2986968630 Jul 16 07:43:35 PM PDT 24 Jul 16 07:43:42 PM PDT 24 478607195 ps
T867 /workspace/coverage/default/39.sram_ctrl_executable.2577095995 Jul 16 07:44:11 PM PDT 24 Jul 16 07:47:32 PM PDT 24 3199848237 ps
T868 /workspace/coverage/default/37.sram_ctrl_max_throughput.1680682410 Jul 16 07:43:53 PM PDT 24 Jul 16 07:45:30 PM PDT 24 330741618 ps
T869 /workspace/coverage/default/19.sram_ctrl_max_throughput.2645332336 Jul 16 07:42:25 PM PDT 24 Jul 16 07:44:44 PM PDT 24 455117393 ps
T870 /workspace/coverage/default/20.sram_ctrl_mem_walk.2511930814 Jul 16 07:42:26 PM PDT 24 Jul 16 07:42:41 PM PDT 24 2381135803 ps
T871 /workspace/coverage/default/30.sram_ctrl_lc_escalation.2836494152 Jul 16 07:43:08 PM PDT 24 Jul 16 07:43:19 PM PDT 24 566339293 ps
T872 /workspace/coverage/default/48.sram_ctrl_max_throughput.3788537536 Jul 16 07:46:19 PM PDT 24 Jul 16 07:46:49 PM PDT 24 111598072 ps
T873 /workspace/coverage/default/41.sram_ctrl_smoke.1232199651 Jul 16 07:44:26 PM PDT 24 Jul 16 07:44:38 PM PDT 24 628173698 ps
T874 /workspace/coverage/default/3.sram_ctrl_max_throughput.2185261034 Jul 16 07:41:23 PM PDT 24 Jul 16 07:42:18 PM PDT 24 180913931 ps
T875 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1250492954 Jul 16 07:41:48 PM PDT 24 Jul 16 07:52:35 PM PDT 24 24497841938 ps
T876 /workspace/coverage/default/47.sram_ctrl_multiple_keys.1492524345 Jul 16 07:45:34 PM PDT 24 Jul 16 08:01:12 PM PDT 24 14820062251 ps
T877 /workspace/coverage/default/38.sram_ctrl_partial_access.1788945218 Jul 16 07:44:10 PM PDT 24 Jul 16 07:44:30 PM PDT 24 1947545731 ps
T878 /workspace/coverage/default/5.sram_ctrl_max_throughput.149163517 Jul 16 07:41:24 PM PDT 24 Jul 16 07:43:42 PM PDT 24 264273219 ps
T879 /workspace/coverage/default/21.sram_ctrl_regwen.375321036 Jul 16 07:42:27 PM PDT 24 Jul 16 07:51:21 PM PDT 24 13089190889 ps
T880 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2685602243 Jul 16 07:44:23 PM PDT 24 Jul 16 07:44:28 PM PDT 24 47580977 ps
T881 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2829221266 Jul 16 07:41:24 PM PDT 24 Jul 16 07:43:29 PM PDT 24 605640254 ps
T882 /workspace/coverage/default/23.sram_ctrl_lc_escalation.2153630605 Jul 16 07:42:28 PM PDT 24 Jul 16 07:42:40 PM PDT 24 1376020289 ps
T883 /workspace/coverage/default/43.sram_ctrl_mem_walk.1398281385 Jul 16 07:44:56 PM PDT 24 Jul 16 07:45:01 PM PDT 24 146888364 ps
T884 /workspace/coverage/default/18.sram_ctrl_multiple_keys.220685800 Jul 16 07:42:09 PM PDT 24 Jul 16 08:04:00 PM PDT 24 5020845484 ps
T885 /workspace/coverage/default/2.sram_ctrl_ram_cfg.2548914419 Jul 16 07:41:09 PM PDT 24 Jul 16 07:41:22 PM PDT 24 124098029 ps
T886 /workspace/coverage/default/17.sram_ctrl_stress_all.2011229509 Jul 16 07:42:07 PM PDT 24 Jul 16 08:58:43 PM PDT 24 54730076641 ps
T887 /workspace/coverage/default/6.sram_ctrl_max_throughput.1639260446 Jul 16 07:41:21 PM PDT 24 Jul 16 07:42:04 PM PDT 24 304791209 ps
T888 /workspace/coverage/default/26.sram_ctrl_max_throughput.1684103721 Jul 16 07:42:53 PM PDT 24 Jul 16 07:44:59 PM PDT 24 516966590 ps
T889 /workspace/coverage/default/28.sram_ctrl_bijection.3140493783 Jul 16 07:43:11 PM PDT 24 Jul 16 07:44:26 PM PDT 24 20298377048 ps
T890 /workspace/coverage/default/27.sram_ctrl_lc_escalation.314187373 Jul 16 07:42:52 PM PDT 24 Jul 16 07:43:01 PM PDT 24 368257350 ps
T891 /workspace/coverage/default/7.sram_ctrl_alert_test.3659985805 Jul 16 07:41:26 PM PDT 24 Jul 16 07:41:47 PM PDT 24 14976077 ps
T892 /workspace/coverage/default/40.sram_ctrl_lc_escalation.2967062683 Jul 16 07:44:22 PM PDT 24 Jul 16 07:44:25 PM PDT 24 99372920 ps
T893 /workspace/coverage/default/26.sram_ctrl_partial_access.3779843087 Jul 16 07:42:51 PM PDT 24 Jul 16 07:43:12 PM PDT 24 300243079 ps
T894 /workspace/coverage/default/13.sram_ctrl_alert_test.1744036110 Jul 16 07:41:56 PM PDT 24 Jul 16 07:42:08 PM PDT 24 16251451 ps
T895 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2308223764 Jul 16 07:46:18 PM PDT 24 Jul 16 07:50:22 PM PDT 24 9521076425 ps
T896 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3981054471 Jul 16 07:41:23 PM PDT 24 Jul 16 08:14:12 PM PDT 24 12122450286 ps
T897 /workspace/coverage/default/40.sram_ctrl_regwen.3251642176 Jul 16 07:44:22 PM PDT 24 Jul 16 07:48:05 PM PDT 24 2297003096 ps
T898 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.28477147 Jul 16 07:44:27 PM PDT 24 Jul 16 08:14:09 PM PDT 24 45664205382 ps
T899 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2376528482 Jul 16 07:42:23 PM PDT 24 Jul 16 07:42:36 PM PDT 24 1188531353 ps
T900 /workspace/coverage/default/33.sram_ctrl_stress_all.112860347 Jul 16 07:43:36 PM PDT 24 Jul 16 08:14:03 PM PDT 24 26702153571 ps
T901 /workspace/coverage/default/13.sram_ctrl_partial_access.1186958123 Jul 16 07:41:52 PM PDT 24 Jul 16 07:42:11 PM PDT 24 1629400882 ps
T902 /workspace/coverage/default/8.sram_ctrl_alert_test.1571824055 Jul 16 07:41:23 PM PDT 24 Jul 16 07:41:45 PM PDT 24 30271172 ps
T903 /workspace/coverage/default/19.sram_ctrl_lc_escalation.561178735 Jul 16 07:42:24 PM PDT 24 Jul 16 07:42:35 PM PDT 24 203420346 ps
T904 /workspace/coverage/default/6.sram_ctrl_lc_escalation.1224489756 Jul 16 07:41:25 PM PDT 24 Jul 16 07:41:54 PM PDT 24 2606652884 ps
T905 /workspace/coverage/default/5.sram_ctrl_multiple_keys.1603032028 Jul 16 07:41:23 PM PDT 24 Jul 16 07:59:05 PM PDT 24 11823904768 ps
T30 /workspace/coverage/default/4.sram_ctrl_sec_cm.552968664 Jul 16 07:41:20 PM PDT 24 Jul 16 07:41:44 PM PDT 24 230512506 ps
T906 /workspace/coverage/default/23.sram_ctrl_bijection.2335751783 Jul 16 07:42:35 PM PDT 24 Jul 16 07:43:47 PM PDT 24 4476764344 ps
T907 /workspace/coverage/default/37.sram_ctrl_alert_test.1829373464 Jul 16 07:44:13 PM PDT 24 Jul 16 07:44:16 PM PDT 24 31611864 ps
T908 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.4194292067 Jul 16 07:42:27 PM PDT 24 Jul 16 07:43:02 PM PDT 24 288638770 ps
T909 /workspace/coverage/default/35.sram_ctrl_regwen.3177105062 Jul 16 07:43:56 PM PDT 24 Jul 16 07:44:24 PM PDT 24 1882860582 ps
T910 /workspace/coverage/default/47.sram_ctrl_stress_all.3261031428 Jul 16 07:45:32 PM PDT 24 Jul 16 08:17:59 PM PDT 24 10687736334 ps
T911 /workspace/coverage/default/32.sram_ctrl_ram_cfg.1757458106 Jul 16 07:43:35 PM PDT 24 Jul 16 07:43:38 PM PDT 24 41427844 ps
T912 /workspace/coverage/default/44.sram_ctrl_ram_cfg.3027769677 Jul 16 07:44:57 PM PDT 24 Jul 16 07:44:59 PM PDT 24 36810598 ps
T913 /workspace/coverage/default/19.sram_ctrl_multiple_keys.2975088965 Jul 16 07:42:22 PM PDT 24 Jul 16 07:49:20 PM PDT 24 21710408490 ps
T914 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1094374621 Jul 16 07:43:05 PM PDT 24 Jul 16 07:55:35 PM PDT 24 15620331811 ps
T915 /workspace/coverage/default/49.sram_ctrl_executable.4004300006 Jul 16 07:46:19 PM PDT 24 Jul 16 07:48:01 PM PDT 24 2312501547 ps
T916 /workspace/coverage/default/14.sram_ctrl_regwen.3711869375 Jul 16 07:41:57 PM PDT 24 Jul 16 07:52:54 PM PDT 24 6816330696 ps
T917 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2485563891 Jul 16 07:46:22 PM PDT 24 Jul 16 08:04:02 PM PDT 24 6408492066 ps
T918 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3225161871 Jul 16 07:45:01 PM PDT 24 Jul 16 07:48:55 PM PDT 24 12042458226 ps
T919 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1609429082 Jul 16 07:42:52 PM PDT 24 Jul 16 07:44:01 PM PDT 24 456416234 ps
T920 /workspace/coverage/default/46.sram_ctrl_bijection.528978761 Jul 16 07:45:33 PM PDT 24 Jul 16 07:46:37 PM PDT 24 2812176502 ps
T921 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2330735008 Jul 16 07:42:36 PM PDT 24 Jul 16 07:42:59 PM PDT 24 601380083 ps
T922 /workspace/coverage/default/17.sram_ctrl_max_throughput.2589500275 Jul 16 07:42:08 PM PDT 24 Jul 16 07:42:32 PM PDT 24 69520149 ps
T923 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3457892927 Jul 16 07:41:24 PM PDT 24 Jul 16 07:43:51 PM PDT 24 311843128 ps
T924 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1916974241 Jul 16 07:43:21 PM PDT 24 Jul 16 07:44:29 PM PDT 24 335907785 ps
T925 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.162168132 Jul 16 07:44:42 PM PDT 24 Jul 16 07:45:59 PM PDT 24 498682562 ps
T926 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3932723312 Jul 16 07:42:23 PM PDT 24 Jul 16 07:52:27 PM PDT 24 3007809860 ps
T927 /workspace/coverage/default/27.sram_ctrl_mem_walk.2227664915 Jul 16 07:43:04 PM PDT 24 Jul 16 07:43:13 PM PDT 24 787116859 ps
T928 /workspace/coverage/default/46.sram_ctrl_regwen.586754592 Jul 16 07:45:35 PM PDT 24 Jul 16 07:55:17 PM PDT 24 8169016104 ps
T929 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2593661062 Jul 16 07:42:11 PM PDT 24 Jul 16 07:43:22 PM PDT 24 421028053 ps
T930 /workspace/coverage/default/25.sram_ctrl_smoke.1843620927 Jul 16 07:42:43 PM PDT 24 Jul 16 07:43:01 PM PDT 24 708424096 ps
T931 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1425393765 Jul 16 07:43:05 PM PDT 24 Jul 16 07:49:02 PM PDT 24 15212855895 ps
T932 /workspace/coverage/default/38.sram_ctrl_lc_escalation.3557476667 Jul 16 07:44:12 PM PDT 24 Jul 16 07:44:15 PM PDT 24 127192560 ps
T933 /workspace/coverage/default/29.sram_ctrl_partial_access.3479690896 Jul 16 07:43:06 PM PDT 24 Jul 16 07:43:32 PM PDT 24 293039894 ps
T934 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3338615983 Jul 16 07:45:32 PM PDT 24 Jul 16 07:50:05 PM PDT 24 2643579464 ps
T935 /workspace/coverage/default/31.sram_ctrl_regwen.2137017219 Jul 16 07:43:22 PM PDT 24 Jul 16 07:51:15 PM PDT 24 12194906769 ps
T936 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3718211895 Jul 16 07:42:23 PM PDT 24 Jul 16 07:43:08 PM PDT 24 427082342 ps
T937 /workspace/coverage/default/0.sram_ctrl_regwen.373672739 Jul 16 07:41:05 PM PDT 24 Jul 16 08:07:16 PM PDT 24 87671176781 ps
T938 /workspace/coverage/default/28.sram_ctrl_mem_walk.1374597417 Jul 16 07:43:04 PM PDT 24 Jul 16 07:43:17 PM PDT 24 599845269 ps
T939 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3713061501 Jul 16 07:42:07 PM PDT 24 Jul 16 07:42:19 PM PDT 24 62903115 ps
T940 /workspace/coverage/default/8.sram_ctrl_partial_access.374140845 Jul 16 07:41:29 PM PDT 24 Jul 16 07:41:55 PM PDT 24 527635251 ps
T941 /workspace/coverage/default/4.sram_ctrl_smoke.1700485772 Jul 16 07:41:19 PM PDT 24 Jul 16 07:41:55 PM PDT 24 2559931332 ps
T74 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2185976319 Jul 16 07:10:34 PM PDT 24 Jul 16 07:10:36 PM PDT 24 59708908 ps
T69 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2349674665 Jul 16 07:10:32 PM PDT 24 Jul 16 07:10:35 PM PDT 24 196159526 ps
T75 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.248256551 Jul 16 07:10:36 PM PDT 24 Jul 16 07:10:40 PM PDT 24 14045495 ps
T70 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3732493454 Jul 16 07:10:19 PM PDT 24 Jul 16 07:10:22 PM PDT 24 136375403 ps
T81 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1761528085 Jul 16 07:10:10 PM PDT 24 Jul 16 07:10:12 PM PDT 24 19041883 ps
T117 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3425661198 Jul 16 07:10:21 PM PDT 24 Jul 16 07:10:23 PM PDT 24 45800288 ps
T82 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3581224743 Jul 16 07:10:20 PM PDT 24 Jul 16 07:10:22 PM PDT 24 24357551 ps
T83 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.928981708 Jul 16 07:10:36 PM PDT 24 Jul 16 07:10:40 PM PDT 24 79122734 ps
T942 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1054210567 Jul 16 07:10:33 PM PDT 24 Jul 16 07:10:35 PM PDT 24 40493501 ps
T71 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1322284118 Jul 16 07:10:11 PM PDT 24 Jul 16 07:10:14 PM PDT 24 241818265 ps
T84 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1382401906 Jul 16 07:10:37 PM PDT 24 Jul 16 07:10:42 PM PDT 24 413143994 ps
T112 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2822285540 Jul 16 07:10:11 PM PDT 24 Jul 16 07:10:12 PM PDT 24 25279338 ps
T85 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3836746028 Jul 16 07:10:28 PM PDT 24 Jul 16 07:10:32 PM PDT 24 800571127 ps
T128 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2996761117 Jul 16 07:10:36 PM PDT 24 Jul 16 07:10:40 PM PDT 24 204687355 ps
T86 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3866114591 Jul 16 07:10:16 PM PDT 24 Jul 16 07:10:18 PM PDT 24 42222820 ps
T118 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3949978592 Jul 16 07:10:19 PM PDT 24 Jul 16 07:10:21 PM PDT 24 25131492 ps
T943 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.6072683 Jul 16 07:10:38 PM PDT 24 Jul 16 07:10:42 PM PDT 24 58374399 ps
T944 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1651584094 Jul 16 07:10:37 PM PDT 24 Jul 16 07:10:44 PM PDT 24 501337510 ps
T945 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4110744568 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:39 PM PDT 24 83451970 ps
T113 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2918851500 Jul 16 07:10:37 PM PDT 24 Jul 16 07:10:42 PM PDT 24 327395061 ps
T126 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2257926082 Jul 16 07:10:26 PM PDT 24 Jul 16 07:10:30 PM PDT 24 693989371 ps
T946 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2177899316 Jul 16 07:10:33 PM PDT 24 Jul 16 07:10:36 PM PDT 24 440203133 ps
T129 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2426641775 Jul 16 07:10:25 PM PDT 24 Jul 16 07:10:29 PM PDT 24 193275560 ps
T87 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4152104813 Jul 16 07:10:32 PM PDT 24 Jul 16 07:10:37 PM PDT 24 456900266 ps
T88 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2334545790 Jul 16 07:10:26 PM PDT 24 Jul 16 07:10:28 PM PDT 24 12091554 ps
T114 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1600489286 Jul 16 07:10:39 PM PDT 24 Jul 16 07:10:42 PM PDT 24 75398001 ps
T947 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3820713142 Jul 16 07:10:32 PM PDT 24 Jul 16 07:10:34 PM PDT 24 30868003 ps
T89 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3544011656 Jul 16 07:10:20 PM PDT 24 Jul 16 07:10:22 PM PDT 24 15575587 ps
T948 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2394140261 Jul 16 07:10:26 PM PDT 24 Jul 16 07:10:30 PM PDT 24 41795175 ps
T91 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.98335631 Jul 16 07:10:21 PM PDT 24 Jul 16 07:10:26 PM PDT 24 403704177 ps
T949 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.702601590 Jul 16 07:10:26 PM PDT 24 Jul 16 07:10:31 PM PDT 24 146791261 ps
T950 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3215606544 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:38 PM PDT 24 59158665 ps
T951 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3081619109 Jul 16 07:10:25 PM PDT 24 Jul 16 07:10:27 PM PDT 24 32461586 ps
T952 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.599037770 Jul 16 07:10:26 PM PDT 24 Jul 16 07:10:30 PM PDT 24 23662695 ps
T953 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.659383619 Jul 16 07:10:25 PM PDT 24 Jul 16 07:10:28 PM PDT 24 38029390 ps
T954 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.452680330 Jul 16 07:10:28 PM PDT 24 Jul 16 07:10:31 PM PDT 24 340405890 ps
T127 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2950073051 Jul 16 07:10:21 PM PDT 24 Jul 16 07:10:25 PM PDT 24 287741054 ps
T955 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1508733420 Jul 16 07:10:38 PM PDT 24 Jul 16 07:10:41 PM PDT 24 16393097 ps
T956 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3195553650 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:40 PM PDT 24 85888674 ps
T957 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4197628141 Jul 16 07:10:36 PM PDT 24 Jul 16 07:10:40 PM PDT 24 208080363 ps
T958 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3400910329 Jul 16 07:10:34 PM PDT 24 Jul 16 07:10:37 PM PDT 24 26374031 ps
T92 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.308175213 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:39 PM PDT 24 14535112 ps
T959 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3805597574 Jul 16 07:10:10 PM PDT 24 Jul 16 07:10:11 PM PDT 24 40432813 ps
T960 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2576353255 Jul 16 07:10:25 PM PDT 24 Jul 16 07:10:33 PM PDT 24 314120489 ps
T101 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1280493506 Jul 16 07:10:12 PM PDT 24 Jul 16 07:10:16 PM PDT 24 175804641 ps
T961 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3965449003 Jul 16 07:10:14 PM PDT 24 Jul 16 07:10:16 PM PDT 24 27500966 ps
T93 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3798774885 Jul 16 07:10:12 PM PDT 24 Jul 16 07:10:15 PM PDT 24 238444374 ps
T962 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3601262505 Jul 16 07:10:19 PM PDT 24 Jul 16 07:10:22 PM PDT 24 98395780 ps
T963 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2595082830 Jul 16 07:10:32 PM PDT 24 Jul 16 07:10:37 PM PDT 24 1459425235 ps
T131 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3735196192 Jul 16 07:10:21 PM PDT 24 Jul 16 07:10:24 PM PDT 24 337829464 ps
T134 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.484528971 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:40 PM PDT 24 146872929 ps
T964 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4081868374 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:39 PM PDT 24 35746226 ps
T965 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3081326895 Jul 16 07:10:29 PM PDT 24 Jul 16 07:10:31 PM PDT 24 367323348 ps
T966 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3731799406 Jul 16 07:10:36 PM PDT 24 Jul 16 07:10:42 PM PDT 24 1614776507 ps
T967 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2810218157 Jul 16 07:10:26 PM PDT 24 Jul 16 07:10:29 PM PDT 24 31175445 ps
T94 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.706314006 Jul 16 07:10:38 PM PDT 24 Jul 16 07:10:41 PM PDT 24 25974484 ps
T968 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2578328473 Jul 16 07:10:39 PM PDT 24 Jul 16 07:10:42 PM PDT 24 55719011 ps
T969 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3387301689 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:40 PM PDT 24 38821140 ps
T970 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4067619445 Jul 16 07:10:37 PM PDT 24 Jul 16 07:10:41 PM PDT 24 17622475 ps
T971 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1621109767 Jul 16 07:10:25 PM PDT 24 Jul 16 07:10:28 PM PDT 24 99718230 ps
T95 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3822960809 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:41 PM PDT 24 444376481 ps
T972 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1087193111 Jul 16 07:10:18 PM PDT 24 Jul 16 07:10:22 PM PDT 24 2155734122 ps
T105 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2960436792 Jul 16 07:10:34 PM PDT 24 Jul 16 07:10:39 PM PDT 24 243537696 ps
T973 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3500808401 Jul 16 07:10:12 PM PDT 24 Jul 16 07:10:14 PM PDT 24 79263898 ps
T974 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3952531145 Jul 16 07:10:16 PM PDT 24 Jul 16 07:10:18 PM PDT 24 116059974 ps
T110 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3249286373 Jul 16 07:10:25 PM PDT 24 Jul 16 07:10:29 PM PDT 24 345773721 ps
T132 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2396864344 Jul 16 07:10:38 PM PDT 24 Jul 16 07:10:43 PM PDT 24 261001591 ps
T975 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2426751481 Jul 16 07:10:21 PM PDT 24 Jul 16 07:10:23 PM PDT 24 223128972 ps
T976 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3046483036 Jul 16 07:10:19 PM PDT 24 Jul 16 07:10:22 PM PDT 24 166488136 ps
T102 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1820451248 Jul 16 07:10:18 PM PDT 24 Jul 16 07:10:19 PM PDT 24 85203340 ps
T977 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.169888500 Jul 16 07:10:12 PM PDT 24 Jul 16 07:10:17 PM PDT 24 44782843 ps
T103 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1276840927 Jul 16 07:10:34 PM PDT 24 Jul 16 07:10:38 PM PDT 24 1575085749 ps
T978 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3073392968 Jul 16 07:10:28 PM PDT 24 Jul 16 07:10:31 PM PDT 24 43367705 ps
T979 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2234561305 Jul 16 07:10:31 PM PDT 24 Jul 16 07:10:33 PM PDT 24 152212175 ps
T104 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2117924626 Jul 16 07:10:37 PM PDT 24 Jul 16 07:10:41 PM PDT 24 18748194 ps
T111 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1848012989 Jul 16 07:10:34 PM PDT 24 Jul 16 07:10:36 PM PDT 24 41654569 ps
T980 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1442501770 Jul 16 07:10:26 PM PDT 24 Jul 16 07:10:30 PM PDT 24 70642352 ps
T981 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.14859189 Jul 16 07:10:16 PM PDT 24 Jul 16 07:10:19 PM PDT 24 654686212 ps
T982 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3494759659 Jul 16 07:10:24 PM PDT 24 Jul 16 07:10:26 PM PDT 24 28245187 ps
T130 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2192855696 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:39 PM PDT 24 542214185 ps
T983 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3426514220 Jul 16 07:10:32 PM PDT 24 Jul 16 07:10:33 PM PDT 24 18565094 ps
T984 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3863032747 Jul 16 07:10:34 PM PDT 24 Jul 16 07:10:41 PM PDT 24 589699949 ps
T985 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3728813543 Jul 16 07:10:39 PM PDT 24 Jul 16 07:10:43 PM PDT 24 464265592 ps
T986 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3409231114 Jul 16 07:10:33 PM PDT 24 Jul 16 07:10:39 PM PDT 24 285379493 ps
T106 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.753010000 Jul 16 07:10:33 PM PDT 24 Jul 16 07:10:38 PM PDT 24 425466760 ps
T987 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3688321723 Jul 16 07:10:10 PM PDT 24 Jul 16 07:10:15 PM PDT 24 356436464 ps
T988 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2772696910 Jul 16 07:10:16 PM PDT 24 Jul 16 07:10:17 PM PDT 24 198739152 ps
T989 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1839205795 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:42 PM PDT 24 1517197195 ps
T990 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1223297895 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:38 PM PDT 24 41957222 ps
T991 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.845328235 Jul 16 07:10:29 PM PDT 24 Jul 16 07:10:31 PM PDT 24 196850664 ps
T992 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1295212530 Jul 16 07:10:14 PM PDT 24 Jul 16 07:10:19 PM PDT 24 483179988 ps
T993 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.406524333 Jul 16 07:10:36 PM PDT 24 Jul 16 07:10:40 PM PDT 24 145366330 ps
T994 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3155720691 Jul 16 07:10:32 PM PDT 24 Jul 16 07:10:37 PM PDT 24 137167693 ps
T995 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1525172055 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:38 PM PDT 24 33531621 ps
T996 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4068888381 Jul 16 07:10:32 PM PDT 24 Jul 16 07:10:35 PM PDT 24 35321744 ps
T997 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.662137392 Jul 16 07:10:18 PM PDT 24 Jul 16 07:10:19 PM PDT 24 17819332 ps
T998 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.877692528 Jul 16 07:10:25 PM PDT 24 Jul 16 07:10:27 PM PDT 24 23802706 ps
T999 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.35368160 Jul 16 07:10:25 PM PDT 24 Jul 16 07:10:27 PM PDT 24 20889755 ps
T1000 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2698215522 Jul 16 07:10:28 PM PDT 24 Jul 16 07:10:31 PM PDT 24 43037663 ps
T1001 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3567432445 Jul 16 07:10:32 PM PDT 24 Jul 16 07:10:34 PM PDT 24 20235498 ps
T1002 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2301383681 Jul 16 07:10:29 PM PDT 24 Jul 16 07:10:32 PM PDT 24 215107911 ps
T1003 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4153896482 Jul 16 07:10:40 PM PDT 24 Jul 16 07:10:43 PM PDT 24 144183017 ps
T1004 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.590637057 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:39 PM PDT 24 485871183 ps
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