Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.98	99.16	94.27	99.72	100.00	95.95	99.12	97.62

Total test records in report: 1030

T1005	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3536865754	Jul 16 07:10:19 PM PDT 24	Jul 16 07:10:21 PM PDT 24	21897665 ps
T107	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3843971941	Jul 16 07:10:18 PM PDT 24	Jul 16 07:10:21 PM PDT 24	296575343 ps
T1006	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3215506192	Jul 16 07:10:38 PM PDT 24	Jul 16 07:10:43 PM PDT 24	133549117 ps
T1007	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2861659181	Jul 16 07:10:11 PM PDT 24	Jul 16 07:10:12 PM PDT 24	19282681 ps
T1008	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2964505581	Jul 16 07:10:18 PM PDT 24	Jul 16 07:10:20 PM PDT 24	15769277 ps
T1009	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4121369197	Jul 16 07:10:34 PM PDT 24	Jul 16 07:10:37 PM PDT 24	216851809 ps
T1010	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1928271083	Jul 16 07:10:21 PM PDT 24	Jul 16 07:10:24 PM PDT 24	28930296 ps
T1011	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2395753556	Jul 16 07:10:32 PM PDT 24	Jul 16 07:10:33 PM PDT 24	35227088 ps
T1012	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.690568402	Jul 16 07:10:32 PM PDT 24	Jul 16 07:10:38 PM PDT 24	518052952 ps
T1013	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1857020958	Jul 16 07:10:35 PM PDT 24	Jul 16 07:10:39 PM PDT 24	81340966 ps
T1014	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1655194251	Jul 16 07:10:26 PM PDT 24	Jul 16 07:10:31 PM PDT 24	42217457 ps
T1015	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2506201457	Jul 16 07:10:34 PM PDT 24	Jul 16 07:10:39 PM PDT 24	41412353 ps
T1016	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3595275769	Jul 16 07:10:28 PM PDT 24	Jul 16 07:10:30 PM PDT 24	111330070 ps
T1017	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1894962396	Jul 16 07:10:10 PM PDT 24	Jul 16 07:10:13 PM PDT 24	115275215 ps
T108	/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3000355951	Jul 16 07:10:28 PM PDT 24	Jul 16 07:10:33 PM PDT 24	509298878 ps
T1018	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.909632663	Jul 16 07:10:36 PM PDT 24	Jul 16 07:10:41 PM PDT 24	108105111 ps
T1019	/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3254266472	Jul 16 07:10:26 PM PDT 24	Jul 16 07:10:32 PM PDT 24	595061016 ps
T1020	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3352443173	Jul 16 07:10:11 PM PDT 24	Jul 16 07:10:16 PM PDT 24	755369745 ps
T1021	/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.488765326	Jul 16 07:10:26 PM PDT 24	Jul 16 07:10:28 PM PDT 24	18164775 ps
T1022	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.379191106	Jul 16 07:10:14 PM PDT 24	Jul 16 07:10:18 PM PDT 24	122364011 ps
T1023	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.428879522	Jul 16 07:10:13 PM PDT 24	Jul 16 07:10:15 PM PDT 24	316964038 ps
T109	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.104952734	Jul 16 07:10:16 PM PDT 24	Jul 16 07:10:19 PM PDT 24	57672839 ps
T1024	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2480419724	Jul 16 07:10:36 PM PDT 24	Jul 16 07:10:41 PM PDT 24	101828041 ps
T133	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3750418872	Jul 16 07:10:25 PM PDT 24	Jul 16 07:10:29 PM PDT 24	189010122 ps
T1025	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3546625443	Jul 16 07:10:18 PM PDT 24	Jul 16 07:10:21 PM PDT 24	363374726 ps
T1026	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2958209961	Jul 16 07:10:17 PM PDT 24	Jul 16 07:10:20 PM PDT 24	70431000 ps
T1027	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3319360950	Jul 16 07:10:25 PM PDT 24	Jul 16 07:10:27 PM PDT 24	57129256 ps
T1028	/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4190339351	Jul 16 07:10:26 PM PDT 24	Jul 16 07:10:28 PM PDT 24	28069480 ps
T1029	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3539468506	Jul 16 07:10:32 PM PDT 24	Jul 16 07:10:39 PM PDT 24	450665250 ps
T1030	/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3835578382	Jul 16 07:10:12 PM PDT 24	Jul 16 07:10:15 PM PDT 24	247827941 ps

Test location	/workspace/coverage/default/24.sram_ctrl_executable.4154373
Short name	T10
Test name
Test status
Simulation time	17097568897 ps
CPU time	1009.93 seconds
Started	Jul 16 07:42:41 PM PDT 24
Finished	Jul 16 07:59:36 PM PDT 24
Peak memory	374060 kb
Host	smart-f0da8e8a-e697-4440-ae82-00ab1673cba6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.4154373
Directory	/workspace/24.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1392600837
Short name	T22
Test name
Test status
Simulation time	10271573562 ps
CPU time	637.44 seconds
Started	Jul 16 07:44:40 PM PDT 24
Finished	Jul 16 07:55:19 PM PDT 24
Peak memory	380992 kb
Host	smart-eda1c32d-eccd-4682-bf34-0cac5d4a3d8c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1392600837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1392600837
Directory	/workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all.1038846716
Short name	T6
Test name
Test status
Simulation time	21595239881 ps
CPU time	4526.81 seconds
Started	Jul 16 07:42:20 PM PDT 24
Finished	Jul 16 08:57:56 PM PDT 24
Peak memory	382636 kb
Host	smart-a3807f4a-8cc5-42bb-8789-06441a73c76b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038846716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.1038846716
Directory	/workspace/18.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2868662401
Short name	T54
Test name
Test status
Simulation time	2263122812 ps
CPU time	5.99 seconds
Started	Jul 16 07:44:24 PM PDT 24
Finished	Jul 16 07:44:33 PM PDT 24
Peak memory	211220 kb
Host	smart-7c3b4f21-438c-4e08-8356-df7c6693bdba
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868662401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.2868662401
Directory	/workspace/39.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2077212326
Short name	T25
Test name
Test status
Simulation time	930984715 ps
CPU time	7.95 seconds
Started	Jul 16 07:41:07 PM PDT 24
Finished	Jul 16 07:41:26 PM PDT 24
Peak memory	211280 kb
Host	smart-3d803abd-79bf-44be-8b4a-67d098f7effd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2077212326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2077212326
Directory	/workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1322284118
Short name	T71
Test name
Test status
Simulation time	241818265 ps
CPU time	2.13 seconds
Started	Jul 16 07:10:11 PM PDT 24
Finished	Jul 16 07:10:14 PM PDT 24
Peak memory	210420 kb
Host	smart-69408536-5a99-4449-875a-b75ce3333e1a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322284118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1322284118
Directory	/workspace/1.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/22.sram_ctrl_access_during_key_req.860264995
Short name	T8
Test name
Test status
Simulation time	16227537318 ps
CPU time	1218.18 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 08:02:49 PM PDT 24
Peak memory	375728 kb
Host	smart-0488b704-50a6-420e-a02f-42cbbe10da06
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860264995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 22.sram_ctrl_access_during_key_req.860264995
Directory	/workspace/22.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/0.sram_ctrl_sec_cm.507957586
Short name	T16
Test name
Test status
Simulation time	1294531559 ps
CPU time	2.1 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:41:22 PM PDT 24
Peak memory	222012 kb
Host	smart-276e5929-be5b-481b-b745-29aad80f80da
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507957586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_sec_cm.507957586
Directory	/workspace/0.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3630494770
Short name	T42
Test name
Test status
Simulation time	121948785249 ps
CPU time	252.72 seconds
Started	Jul 16 07:42:19 PM PDT 24
Finished	Jul 16 07:46:39 PM PDT 24
Peak memory	202876 kb
Host	smart-d4e563f9-e19d-4480-9957-78c79d9ddae7
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630494770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.3630494770
Directory	/workspace/19.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/30.sram_ctrl_alert_test.105825033
Short name	T14
Test name
Test status
Simulation time	31105960 ps
CPU time	0.63 seconds
Started	Jul 16 07:43:19 PM PDT 24
Finished	Jul 16 07:43:22 PM PDT 24
Peak memory	202608 kb
Host	smart-1e8d2dc8-8cc3-40e9-b8fa-de5f6ae733a8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105825033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.105825033
Directory	/workspace/30.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1382401906
Short name	T84
Test name
Test status
Simulation time	413143994 ps
CPU time	1.89 seconds
Started	Jul 16 07:10:37 PM PDT 24
Finished	Jul 16 07:10:42 PM PDT 24
Peak memory	202056 kb
Host	smart-90e85027-2ec2-49c3-abf3-723e32b2c7de
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382401906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1382401906
Directory	/workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all.2544439226
Short name	T23
Test name
Test status
Simulation time	33713832265 ps
CPU time	1997.39 seconds
Started	Jul 16 07:46:11 PM PDT 24
Finished	Jul 16 08:19:29 PM PDT 24
Peak memory	383100 kb
Host	smart-e86cbc95-226b-4f16-8153-0f93358d12e6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544439226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.2544439226
Directory	/workspace/48.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.sram_ctrl_ram_cfg.2392510280
Short name	T11
Test name
Test status
Simulation time	46436736 ps
CPU time	0.75 seconds
Started	Jul 16 07:45:36 PM PDT 24
Finished	Jul 16 07:45:39 PM PDT 24
Peak memory	202876 kb
Host	smart-61cfd06b-5f9c-4711-92dd-ab4d18a9173a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392510280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2392510280
Directory	/workspace/47.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3750418872
Short name	T133
Test name
Test status
Simulation time	189010122 ps
CPU time	2.53 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:29 PM PDT 24
Peak memory	210360 kb
Host	smart-9dae180f-6a21-45fe-965d-d8e0f885940c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750418872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.3750418872
Directory	/workspace/10.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4056816605
Short name	T813
Test name
Test status
Simulation time	5188671891 ps
CPU time	219.6 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:45:00 PM PDT 24
Peak memory	367408 kb
Host	smart-09122d78-4d0f-474a-be03-663c0a0dd14b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4056816605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.4056816605
Directory	/workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3617785041
Short name	T52
Test name
Test status
Simulation time	1993034321 ps
CPU time	6.15 seconds
Started	Jul 16 07:41:07 PM PDT 24
Finished	Jul 16 07:41:23 PM PDT 24
Peak memory	211048 kb
Host	smart-d1e2d795-7c55-4606-a619-70691e4d31c8
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617785041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.3617785041
Directory	/workspace/1.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2950073051
Short name	T127
Test name
Test status
Simulation time	287741054 ps
CPU time	2.5 seconds
Started	Jul 16 07:10:21 PM PDT 24
Finished	Jul 16 07:10:25 PM PDT 24
Peak memory	210352 kb
Host	smart-779d62e8-3db5-4a03-95fc-8d831eee0628
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950073051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.2950073051
Directory	/workspace/2.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all.1565683462
Short name	T72
Test name
Test status
Simulation time	14956513992 ps
CPU time	6030.18 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 09:23:37 PM PDT 24
Peak memory	376796 kb
Host	smart-a05ac66c-8666-42d2-a176-d804dac6757c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565683462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.1565683462
Directory	/workspace/28.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2396864344
Short name	T132
Test name
Test status
Simulation time	261001591 ps
CPU time	2.2 seconds
Started	Jul 16 07:10:38 PM PDT 24
Finished	Jul 16 07:10:43 PM PDT 24
Peak memory	210352 kb
Host	smart-0ef271a4-a9bf-4d6a-a943-a0f3cc8e61be
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396864344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.2396864344
Directory	/workspace/14.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3822960809
Short name	T95
Test name
Test status
Simulation time	444376481 ps
CPU time	3.06 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:41 PM PDT 24
Peak memory	202220 kb
Host	smart-d30aff72-284e-4e93-a217-ef1db9160749
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822960809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.3822960809
Directory	/workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/default/16.sram_ctrl_multiple_keys.1707820827
Short name	T142
Test name
Test status
Simulation time	45730086362 ps
CPU time	1092.11 seconds
Started	Jul 16 07:42:06 PM PDT 24
Finished	Jul 16 08:00:26 PM PDT 24
Peak memory	369664 kb
Host	smart-0022d7f4-01ad-4151-80d1-9dd9529a880c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707820827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.1707820827
Directory	/workspace/16.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3500808401
Short name	T973
Test name
Test status
Simulation time	79263898 ps
CPU time	0.68 seconds
Started	Jul 16 07:10:12 PM PDT 24
Finished	Jul 16 07:10:14 PM PDT 24
Peak memory	201916 kb
Host	smart-b16b8524-f9d7-49be-8f5d-946adf4f2c97
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500808401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.3500808401
Directory	/workspace/0.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.428879522
Short name	T1023
Test name
Test status
Simulation time	316964038 ps
CPU time	1.45 seconds
Started	Jul 16 07:10:13 PM PDT 24
Finished	Jul 16 07:10:15 PM PDT 24
Peak memory	202180 kb
Host	smart-4279404d-4e97-4b96-af32-661ba81c58e8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428879522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.428879522
Directory	/workspace/0.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3425661198
Short name	T117
Test name
Test status
Simulation time	45800288 ps
CPU time	0.72 seconds
Started	Jul 16 07:10:21 PM PDT 24
Finished	Jul 16 07:10:23 PM PDT 24
Peak memory	201904 kb
Host	smart-c0a3a88d-6fb5-49a6-b9eb-66e98fb2fd2c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425661198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.3425661198
Directory	/workspace/0.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3546625443
Short name	T1025
Test name
Test status
Simulation time	363374726 ps
CPU time	0.98 seconds
Started	Jul 16 07:10:18 PM PDT 24
Finished	Jul 16 07:10:21 PM PDT 24
Peak memory	210188 kb
Host	smart-91375cd4-74e4-40d1-a35f-4cc667d91b21
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546625443 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3546625443
Directory	/workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2964505581
Short name	T1008
Test name
Test status
Simulation time	15769277 ps
CPU time	0.67 seconds
Started	Jul 16 07:10:18 PM PDT 24
Finished	Jul 16 07:10:20 PM PDT 24
Peak memory	201800 kb
Host	smart-9375c904-8412-4a33-a6a5-1092bea7048c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964505581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.2964505581
Directory	/workspace/0.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1087193111
Short name	T972
Test name
Test status
Simulation time	2155734122 ps
CPU time	2.15 seconds
Started	Jul 16 07:10:18 PM PDT 24
Finished	Jul 16 07:10:22 PM PDT 24
Peak memory	202184 kb
Host	smart-5e03ef6b-5889-447c-aae1-ab26e16309ec
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087193111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1087193111
Directory	/workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3866114591
Short name	T86
Test name
Test status
Simulation time	42222820 ps
CPU time	0.75 seconds
Started	Jul 16 07:10:16 PM PDT 24
Finished	Jul 16 07:10:18 PM PDT 24
Peak memory	201960 kb
Host	smart-bc7129f1-2803-49af-9ba5-c2213bf153c5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866114591 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3866114591
Directory	/workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3352443173
Short name	T1020
Test name
Test status
Simulation time	755369745 ps
CPU time	4.03 seconds
Started	Jul 16 07:10:11 PM PDT 24
Finished	Jul 16 07:10:16 PM PDT 24
Peak memory	210380 kb
Host	smart-172c760e-8612-4c65-82db-d83bca2dfd3f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352443173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.3352443173
Directory	/workspace/0.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.14859189
Short name	T981
Test name
Test status
Simulation time	654686212 ps
CPU time	2.36 seconds
Started	Jul 16 07:10:16 PM PDT 24
Finished	Jul 16 07:10:19 PM PDT 24
Peak memory	210372 kb
Host	smart-5abeb63b-abb0-472c-9718-be3b23181ef1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14859189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.sram_ctrl_tl_intg_err.14859189
Directory	/workspace/0.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3949978592
Short name	T118
Test name
Test status
Simulation time	25131492 ps
CPU time	0.66 seconds
Started	Jul 16 07:10:19 PM PDT 24
Finished	Jul 16 07:10:21 PM PDT 24
Peak memory	201832 kb
Host	smart-4b7b8c27-668a-4715-bd2d-5df8a3ff5cf0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949978592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.3949978592
Directory	/workspace/1.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1280493506
Short name	T101
Test name
Test status
Simulation time	175804641 ps
CPU time	2.22 seconds
Started	Jul 16 07:10:12 PM PDT 24
Finished	Jul 16 07:10:16 PM PDT 24
Peak memory	202044 kb
Host	smart-d8808bbc-8645-4512-b970-a906097e5a80
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280493506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.1280493506
Directory	/workspace/1.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2861659181
Short name	T1007
Test name
Test status
Simulation time	19282681 ps
CPU time	0.69 seconds
Started	Jul 16 07:10:11 PM PDT 24
Finished	Jul 16 07:10:12 PM PDT 24
Peak memory	201932 kb
Host	smart-d0f84966-da44-4fc3-8ffd-e8cdf709ba25
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861659181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2861659181
Directory	/workspace/1.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3601262505
Short name	T962
Test name
Test status
Simulation time	98395780 ps
CPU time	1.67 seconds
Started	Jul 16 07:10:19 PM PDT 24
Finished	Jul 16 07:10:22 PM PDT 24
Peak memory	210352 kb
Host	smart-6f81785e-2d2d-4bdb-830e-5be1fece24f1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601262505 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3601262505
Directory	/workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3581224743
Short name	T82
Test name
Test status
Simulation time	24357551 ps
CPU time	0.62 seconds
Started	Jul 16 07:10:20 PM PDT 24
Finished	Jul 16 07:10:22 PM PDT 24
Peak memory	201896 kb
Host	smart-318cf851-8e1b-4e05-9902-29db7682ef03
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581224743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.3581224743
Directory	/workspace/1.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.98335631
Short name	T91
Test name
Test status
Simulation time	403704177 ps
CPU time	3.31 seconds
Started	Jul 16 07:10:21 PM PDT 24
Finished	Jul 16 07:10:26 PM PDT 24
Peak memory	202276 kb
Host	smart-0b1fce83-e87d-4e25-8dfb-48c0994f06f7
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98335631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.98335631
Directory	/workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3952531145
Short name	T974
Test name
Test status
Simulation time	116059974 ps
CPU time	0.77 seconds
Started	Jul 16 07:10:16 PM PDT 24
Finished	Jul 16 07:10:18 PM PDT 24
Peak memory	201968 kb
Host	smart-6e30c8bc-0fda-4ede-8676-6dc7fb59f9eb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952531145 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3952531145
Directory	/workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3688321723
Short name	T987
Test name
Test status
Simulation time	356436464 ps
CPU time	4.18 seconds
Started	Jul 16 07:10:10 PM PDT 24
Finished	Jul 16 07:10:15 PM PDT 24
Peak memory	210432 kb
Host	smart-50cf99db-1c9f-4389-bbf8-c7f25f6aace5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688321723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.3688321723
Directory	/workspace/1.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1054210567
Short name	T942
Test name
Test status
Simulation time	40493501 ps
CPU time	1.26 seconds
Started	Jul 16 07:10:33 PM PDT 24
Finished	Jul 16 07:10:35 PM PDT 24
Peak memory	210252 kb
Host	smart-68dea4bd-9879-4573-ac3f-95fb223b48fa
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054210567 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1054210567
Directory	/workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3081619109
Short name	T951
Test name
Test status
Simulation time	32461586 ps
CPU time	0.64 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:27 PM PDT 24
Peak memory	201868 kb
Host	smart-ea611322-012d-469f-8400-f4568a52da8d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081619109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.3081619109
Directory	/workspace/10.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3836746028
Short name	T85
Test name
Test status
Simulation time	800571127 ps
CPU time	2.02 seconds
Started	Jul 16 07:10:28 PM PDT 24
Finished	Jul 16 07:10:32 PM PDT 24
Peak memory	202020 kb
Host	smart-e98aebd7-9805-4a87-a84e-22a4d8f4116a
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836746028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.3836746028
Directory	/workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.488765326
Short name	T1021
Test name
Test status
Simulation time	18164775 ps
CPU time	0.76 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:28 PM PDT 24
Peak memory	201988 kb
Host	smart-1a6b5e1a-b553-483e-a952-e4dd933476a8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488765326 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.488765326
Directory	/workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.599037770
Short name	T952
Test name
Test status
Simulation time	23662695 ps
CPU time	2.05 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:30 PM PDT 24
Peak memory	202244 kb
Host	smart-e5acc8f9-6ba9-40d1-ab6b-40eb11789fa4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599037770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.599037770
Directory	/workspace/10.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1857020958
Short name	T1013
Test name
Test status
Simulation time	81340966 ps
CPU time	1.53 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	210396 kb
Host	smart-a2527750-5f89-45c1-b71b-30d53198d49e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857020958 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1857020958
Directory	/workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3426514220
Short name	T983
Test name
Test status
Simulation time	18565094 ps
CPU time	0.63 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:33 PM PDT 24
Peak memory	201888 kb
Host	smart-ccc1ad22-ed30-4df5-b332-769a17492440
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426514220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.3426514220
Directory	/workspace/11.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1276840927
Short name	T103
Test name
Test status
Simulation time	1575085749 ps
CPU time	2.94 seconds
Started	Jul 16 07:10:34 PM PDT 24
Finished	Jul 16 07:10:38 PM PDT 24
Peak memory	202224 kb
Host	smart-bce7cd52-6b8f-4877-ac56-9ee71c47a995
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276840927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1276840927
Directory	/workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3400910329
Short name	T958
Test name
Test status
Simulation time	26374031 ps
CPU time	0.85 seconds
Started	Jul 16 07:10:34 PM PDT 24
Finished	Jul 16 07:10:37 PM PDT 24
Peak memory	201992 kb
Host	smart-ca685ff4-e840-4575-b87c-3809ced8aa46
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400910329 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.3400910329
Directory	/workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3539468506
Short name	T1029
Test name
Test status
Simulation time	450665250 ps
CPU time	5.35 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	210420 kb
Host	smart-4d8f61af-6f90-4557-968a-8f7ccbeef66d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539468506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.3539468506
Directory	/workspace/11.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4121369197
Short name	T1009
Test name
Test status
Simulation time	216851809 ps
CPU time	1.85 seconds
Started	Jul 16 07:10:34 PM PDT 24
Finished	Jul 16 07:10:37 PM PDT 24
Peak memory	210344 kb
Host	smart-104f903c-b87c-48e0-a625-a7edcac222fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121369197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.4121369197
Directory	/workspace/11.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1223297895
Short name	T990
Test name
Test status
Simulation time	41957222 ps
CPU time	0.64 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:38 PM PDT 24
Peak memory	201916 kb
Host	smart-5127634d-7298-4f58-ac9c-62595b0d8c5a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223297895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.1223297895
Directory	/workspace/12.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1839205795
Short name	T989
Test name
Test status
Simulation time	1517197195 ps
CPU time	3.84 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:42 PM PDT 24
Peak memory	202268 kb
Host	smart-c8543eda-cd98-45d4-bb39-f3e5c43a8d9f
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839205795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1839205795
Directory	/workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3215606544
Short name	T950
Test name
Test status
Simulation time	59158665 ps
CPU time	0.71 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:38 PM PDT 24
Peak memory	201928 kb
Host	smart-ff92bb55-0b4f-4101-816c-34b1aed68e3f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215606544 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3215606544
Directory	/workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1651584094
Short name	T944
Test name
Test status
Simulation time	501337510 ps
CPU time	4.43 seconds
Started	Jul 16 07:10:37 PM PDT 24
Finished	Jul 16 07:10:44 PM PDT 24
Peak memory	210428 kb
Host	smart-54b34675-2bac-4f9b-85b1-148cb0b8e4f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651584094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.1651584094
Directory	/workspace/12.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.484528971
Short name	T134
Test name
Test status
Simulation time	146872929 ps
CPU time	2.28 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:40 PM PDT 24
Peak memory	210284 kb
Host	smart-090069ef-71b9-43a1-a867-6ca90f8b28ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484528971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 12.sram_ctrl_tl_intg_err.484528971
Directory	/workspace/12.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2177899316
Short name	T946
Test name
Test status
Simulation time	440203133 ps
CPU time	1.54 seconds
Started	Jul 16 07:10:33 PM PDT 24
Finished	Jul 16 07:10:36 PM PDT 24
Peak memory	211464 kb
Host	smart-865a16d7-3745-4ded-be0b-74098f917713
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177899316 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2177899316
Directory	/workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4067619445
Short name	T970
Test name
Test status
Simulation time	17622475 ps
CPU time	0.68 seconds
Started	Jul 16 07:10:37 PM PDT 24
Finished	Jul 16 07:10:41 PM PDT 24
Peak memory	201848 kb
Host	smart-d5822736-0256-41a9-bb07-944e30941b85
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067619445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.4067619445
Directory	/workspace/13.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.753010000
Short name	T106
Test name
Test status
Simulation time	425466760 ps
CPU time	3.38 seconds
Started	Jul 16 07:10:33 PM PDT 24
Finished	Jul 16 07:10:38 PM PDT 24
Peak memory	202276 kb
Host	smart-4f392ec4-a153-420c-a0ec-176e0281f953
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753010000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.753010000
Directory	/workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.928981708
Short name	T83
Test name
Test status
Simulation time	79122734 ps
CPU time	0.73 seconds
Started	Jul 16 07:10:36 PM PDT 24
Finished	Jul 16 07:10:40 PM PDT 24
Peak memory	201976 kb
Host	smart-0628d5be-1408-4100-a596-9d2ead5ede5f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928981708 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.928981708
Directory	/workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3863032747
Short name	T984
Test name
Test status
Simulation time	589699949 ps
CPU time	5.1 seconds
Started	Jul 16 07:10:34 PM PDT 24
Finished	Jul 16 07:10:41 PM PDT 24
Peak memory	210404 kb
Host	smart-c8a47e62-d811-4de6-8823-7781b5a7dac9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863032747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3863032747
Directory	/workspace/13.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.406524333
Short name	T993
Test name
Test status
Simulation time	145366330 ps
CPU time	1.4 seconds
Started	Jul 16 07:10:36 PM PDT 24
Finished	Jul 16 07:10:40 PM PDT 24
Peak memory	210320 kb
Host	smart-b1686e90-cdd5-4a55-b602-88656c6740fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406524333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.sram_ctrl_tl_intg_err.406524333
Directory	/workspace/13.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4068888381
Short name	T996
Test name
Test status
Simulation time	35321744 ps
CPU time	1.12 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:35 PM PDT 24
Peak memory	211308 kb
Host	smart-3013aa84-242a-4945-b5bc-6cb21fc4fb52
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068888381 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.4068888381
Directory	/workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4081868374
Short name	T964
Test name
Test status
Simulation time	35746226 ps
CPU time	0.68 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	202112 kb
Host	smart-fe08de5b-91b9-443a-90c5-dc337f05410e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081868374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.4081868374
Directory	/workspace/14.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4197628141
Short name	T957
Test name
Test status
Simulation time	208080363 ps
CPU time	0.76 seconds
Started	Jul 16 07:10:36 PM PDT 24
Finished	Jul 16 07:10:40 PM PDT 24
Peak memory	201940 kb
Host	smart-9a3a6429-19d7-492e-8db3-15a6cec04ab1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197628141 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.4197628141
Directory	/workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3155720691
Short name	T994
Test name
Test status
Simulation time	137167693 ps
CPU time	3.65 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:37 PM PDT 24
Peak memory	210452 kb
Host	smart-9e4df278-351e-47b7-a700-916ae0971a43
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155720691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3155720691
Directory	/workspace/14.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2234561305
Short name	T979
Test name
Test status
Simulation time	152212175 ps
CPU time	1.26 seconds
Started	Jul 16 07:10:31 PM PDT 24
Finished	Jul 16 07:10:33 PM PDT 24
Peak memory	211260 kb
Host	smart-a50599d2-573a-4f08-858d-871dd5ab4a82
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234561305 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2234561305
Directory	/workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1848012989
Short name	T111
Test name
Test status
Simulation time	41654569 ps
CPU time	0.67 seconds
Started	Jul 16 07:10:34 PM PDT 24
Finished	Jul 16 07:10:36 PM PDT 24
Peak memory	201888 kb
Host	smart-6154f3ea-d6b2-4cb5-b39e-28a7eedc34a8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848012989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.1848012989
Directory	/workspace/15.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2918851500
Short name	T113
Test name
Test status
Simulation time	327395061 ps
CPU time	2.25 seconds
Started	Jul 16 07:10:37 PM PDT 24
Finished	Jul 16 07:10:42 PM PDT 24
Peak memory	202056 kb
Host	smart-08098a97-a208-4c26-bd23-58569b968fb8
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918851500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2918851500
Directory	/workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2185976319
Short name	T74
Test name
Test status
Simulation time	59708908 ps
CPU time	0.74 seconds
Started	Jul 16 07:10:34 PM PDT 24
Finished	Jul 16 07:10:36 PM PDT 24
Peak memory	201964 kb
Host	smart-9f7515f6-8ca7-4260-9838-4bafa32e5931
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185976319 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2185976319
Directory	/workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3195553650
Short name	T956
Test name
Test status
Simulation time	85888674 ps
CPU time	3.51 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:40 PM PDT 24
Peak memory	210656 kb
Host	smart-1622a874-45bf-49b9-a79f-380a8e764b00
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195553650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.3195553650
Directory	/workspace/15.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.590637057
Short name	T1004
Test name
Test status
Simulation time	485871183 ps
CPU time	2.18 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	210396 kb
Host	smart-4fb6e447-39a6-4e5c-9784-6beb102ae39c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590637057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.sram_ctrl_tl_intg_err.590637057
Directory	/workspace/15.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.6072683
Short name	T943
Test name
Test status
Simulation time	58374399 ps
CPU time	1.18 seconds
Started	Jul 16 07:10:38 PM PDT 24
Finished	Jul 16 07:10:42 PM PDT 24
Peak memory	210224 kb
Host	smart-22e1e525-20ae-4789-bc75-9738b53922d6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6072683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.6072683
Directory	/workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.248256551
Short name	T75
Test name
Test status
Simulation time	14045495 ps
CPU time	0.65 seconds
Started	Jul 16 07:10:36 PM PDT 24
Finished	Jul 16 07:10:40 PM PDT 24
Peak memory	201860 kb
Host	smart-00bbf4d0-3c1c-4d40-abdc-8779e43ddaac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248256551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_csr_rw.248256551
Directory	/workspace/16.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3820713142
Short name	T947
Test name
Test status
Simulation time	30868003 ps
CPU time	0.82 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:34 PM PDT 24
Peak memory	201972 kb
Host	smart-50044838-ef7f-40f1-91c2-c08bec0366fa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820713142 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3820713142
Directory	/workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2506201457
Short name	T1015
Test name
Test status
Simulation time	41412353 ps
CPU time	2.06 seconds
Started	Jul 16 07:10:34 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	210376 kb
Host	smart-6f74f617-cd81-4279-bd49-1d5a3ac1fb82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506201457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.2506201457
Directory	/workspace/16.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.909632663
Short name	T1018
Test name
Test status
Simulation time	108105111 ps
CPU time	1.53 seconds
Started	Jul 16 07:10:36 PM PDT 24
Finished	Jul 16 07:10:41 PM PDT 24
Peak memory	201968 kb
Host	smart-06ab40bd-e7d4-46da-914e-f4d33100328c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909632663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.sram_ctrl_tl_intg_err.909632663
Directory	/workspace/16.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4153896482
Short name	T1003
Test name
Test status
Simulation time	144183017 ps
CPU time	1.15 seconds
Started	Jul 16 07:10:40 PM PDT 24
Finished	Jul 16 07:10:43 PM PDT 24
Peak memory	211468 kb
Host	smart-3b7a869e-15d8-45f8-a725-e5af09f0c5f9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153896482 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.4153896482
Directory	/workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2117924626
Short name	T104
Test name
Test status
Simulation time	18748194 ps
CPU time	0.66 seconds
Started	Jul 16 07:10:37 PM PDT 24
Finished	Jul 16 07:10:41 PM PDT 24
Peak memory	201860 kb
Host	smart-6373c71b-7d8a-4762-9b7a-6ae2f2293de1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117924626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.2117924626
Directory	/workspace/17.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2960436792
Short name	T105
Test name
Test status
Simulation time	243537696 ps
CPU time	1.93 seconds
Started	Jul 16 07:10:34 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	202084 kb
Host	smart-7871f44a-f1a2-483e-817a-64de8af91db6
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960436792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2960436792
Directory	/workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1525172055
Short name	T995
Test name
Test status
Simulation time	33531621 ps
CPU time	0.77 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:38 PM PDT 24
Peak memory	201968 kb
Host	smart-76bf5d46-3867-4a8e-ae3c-728580721eab
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525172055 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1525172055
Directory	/workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4110744568
Short name	T945
Test name
Test status
Simulation time	83451970 ps
CPU time	2.13 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	202428 kb
Host	smart-3327c974-4b82-41cb-9c8a-46a0b3e37a2d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110744568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.4110744568
Directory	/workspace/17.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2192855696
Short name	T130
Test name
Test status
Simulation time	542214185 ps
CPU time	1.54 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	210304 kb
Host	smart-3957a3d6-b343-4e19-8904-6de67c4d6978
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192855696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.2192855696
Directory	/workspace/17.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2578328473
Short name	T968
Test name
Test status
Simulation time	55719011 ps
CPU time	1.01 seconds
Started	Jul 16 07:10:39 PM PDT 24
Finished	Jul 16 07:10:42 PM PDT 24
Peak memory	210288 kb
Host	smart-a89b148c-3454-47b6-83b5-81e1c39a51a0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578328473 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2578328473
Directory	/workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.308175213
Short name	T92
Test name
Test status
Simulation time	14535112 ps
CPU time	0.64 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	201896 kb
Host	smart-dd9a28e5-e0f8-447b-be50-e0568b1da505
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308175213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_csr_rw.308175213
Directory	/workspace/18.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3728813543
Short name	T985
Test name
Test status
Simulation time	464265592 ps
CPU time	1.98 seconds
Started	Jul 16 07:10:39 PM PDT 24
Finished	Jul 16 07:10:43 PM PDT 24
Peak memory	202144 kb
Host	smart-cc03610e-4fbd-43aa-a7d9-d6cc22a30d0e
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728813543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3728813543
Directory	/workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1508733420
Short name	T955
Test name
Test status
Simulation time	16393097 ps
CPU time	0.75 seconds
Started	Jul 16 07:10:38 PM PDT 24
Finished	Jul 16 07:10:41 PM PDT 24
Peak memory	201972 kb
Host	smart-e141b316-48e6-47e0-83db-09fac52074a9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508733420 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1508733420
Directory	/workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3409231114
Short name	T986
Test name
Test status
Simulation time	285379493 ps
CPU time	4.62 seconds
Started	Jul 16 07:10:33 PM PDT 24
Finished	Jul 16 07:10:39 PM PDT 24
Peak memory	202240 kb
Host	smart-4439f352-e361-4ce8-9f95-751583733259
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409231114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3409231114
Directory	/workspace/18.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2996761117
Short name	T128
Test name
Test status
Simulation time	204687355 ps
CPU time	1.56 seconds
Started	Jul 16 07:10:36 PM PDT 24
Finished	Jul 16 07:10:40 PM PDT 24
Peak memory	202124 kb
Host	smart-8016118d-5f37-43ab-bc9d-7c9e37ab6b35
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996761117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.2996761117
Directory	/workspace/18.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3215506192
Short name	T1006
Test name
Test status
Simulation time	133549117 ps
CPU time	1.81 seconds
Started	Jul 16 07:10:38 PM PDT 24
Finished	Jul 16 07:10:43 PM PDT 24
Peak memory	210432 kb
Host	smart-7c7c1e49-8c0b-4606-a006-630ccb3855ad
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215506192 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3215506192
Directory	/workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.706314006
Short name	T94
Test name
Test status
Simulation time	25974484 ps
CPU time	0.67 seconds
Started	Jul 16 07:10:38 PM PDT 24
Finished	Jul 16 07:10:41 PM PDT 24
Peak memory	201912 kb
Host	smart-f5de2791-ea84-4434-b741-61bdd8263348
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706314006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_csr_rw.706314006
Directory	/workspace/19.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3731799406
Short name	T966
Test name
Test status
Simulation time	1614776507 ps
CPU time	3.33 seconds
Started	Jul 16 07:10:36 PM PDT 24
Finished	Jul 16 07:10:42 PM PDT 24
Peak memory	202208 kb
Host	smart-156455d0-7e35-4968-a829-cb33f5b1b9a9
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731799406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.3731799406
Directory	/workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1600489286
Short name	T114
Test name
Test status
Simulation time	75398001 ps
CPU time	0.76 seconds
Started	Jul 16 07:10:39 PM PDT 24
Finished	Jul 16 07:10:42 PM PDT 24
Peak memory	202024 kb
Host	smart-7be4eaac-2014-4805-909b-db5a4e725369
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600489286 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1600489286
Directory	/workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3387301689
Short name	T969
Test name
Test status
Simulation time	38821140 ps
CPU time	2.35 seconds
Started	Jul 16 07:10:35 PM PDT 24
Finished	Jul 16 07:10:40 PM PDT 24
Peak memory	202200 kb
Host	smart-ce8987cb-256b-4924-978a-662c2568a975
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387301689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.3387301689
Directory	/workspace/19.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2480419724
Short name	T1024
Test name
Test status
Simulation time	101828041 ps
CPU time	1.53 seconds
Started	Jul 16 07:10:36 PM PDT 24
Finished	Jul 16 07:10:41 PM PDT 24
Peak memory	202176 kb
Host	smart-43a295fb-6f33-42cb-9f4e-23e5411e8282
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480419724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.2480419724
Directory	/workspace/19.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3965449003
Short name	T961
Test name
Test status
Simulation time	27500966 ps
CPU time	0.72 seconds
Started	Jul 16 07:10:14 PM PDT 24
Finished	Jul 16 07:10:16 PM PDT 24
Peak memory	201824 kb
Host	smart-edb1a41e-2407-45da-9689-713c321540aa
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965449003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.3965449003
Directory	/workspace/2.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.104952734
Short name	T109
Test name
Test status
Simulation time	57672839 ps
CPU time	1.78 seconds
Started	Jul 16 07:10:16 PM PDT 24
Finished	Jul 16 07:10:19 PM PDT 24
Peak memory	202096 kb
Host	smart-947b1e5b-62b0-4fd7-89f9-89410f3468b8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104952734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.104952734
Directory	/workspace/2.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3536865754
Short name	T1005
Test name
Test status
Simulation time	21897665 ps
CPU time	0.68 seconds
Started	Jul 16 07:10:19 PM PDT 24
Finished	Jul 16 07:10:21 PM PDT 24
Peak memory	201456 kb
Host	smart-a34d9b41-8eef-4dbd-ac91-84899825e4f4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536865754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.3536865754
Directory	/workspace/2.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1928271083
Short name	T1010
Test name
Test status
Simulation time	28930296 ps
CPU time	1.01 seconds
Started	Jul 16 07:10:21 PM PDT 24
Finished	Jul 16 07:10:24 PM PDT 24
Peak memory	202040 kb
Host	smart-b4bb937c-9220-491b-84c6-b2deab6fe4e2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928271083 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1928271083
Directory	/workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3805597574
Short name	T959
Test name
Test status
Simulation time	40432813 ps
CPU time	0.68 seconds
Started	Jul 16 07:10:10 PM PDT 24
Finished	Jul 16 07:10:11 PM PDT 24
Peak memory	201928 kb
Host	smart-efe4f573-41a7-4d83-ac51-a1c9c5c8780d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805597574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.3805597574
Directory	/workspace/2.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1295212530
Short name	T992
Test name
Test status
Simulation time	483179988 ps
CPU time	3.41 seconds
Started	Jul 16 07:10:14 PM PDT 24
Finished	Jul 16 07:10:19 PM PDT 24
Peak memory	202240 kb
Host	smart-0af94717-7f12-46f4-9d03-29f03ccd9603
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295212530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1295212530
Directory	/workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2822285540
Short name	T112
Test name
Test status
Simulation time	25279338 ps
CPU time	0.81 seconds
Started	Jul 16 07:10:11 PM PDT 24
Finished	Jul 16 07:10:12 PM PDT 24
Peak memory	201948 kb
Host	smart-99422223-a0af-4ae5-a2a2-9690c36c135e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822285540 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.2822285540
Directory	/workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.169888500
Short name	T977
Test name
Test status
Simulation time	44782843 ps
CPU time	3.84 seconds
Started	Jul 16 07:10:12 PM PDT 24
Finished	Jul 16 07:10:17 PM PDT 24
Peak memory	202292 kb
Host	smart-001c808f-e334-4ea0-90cb-b7c6c91919bf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169888500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.169888500
Directory	/workspace/2.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1820451248
Short name	T102
Test name
Test status
Simulation time	85203340 ps
CPU time	0.75 seconds
Started	Jul 16 07:10:18 PM PDT 24
Finished	Jul 16 07:10:19 PM PDT 24
Peak memory	201828 kb
Host	smart-b08c64fd-d77c-4430-be47-8609d7d0f7f9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820451248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.1820451248
Directory	/workspace/3.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3843971941
Short name	T107
Test name
Test status
Simulation time	296575343 ps
CPU time	2.25 seconds
Started	Jul 16 07:10:18 PM PDT 24
Finished	Jul 16 07:10:21 PM PDT 24
Peak memory	202020 kb
Host	smart-64b8575a-0568-42de-870c-2a7d63f7b0d2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843971941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3843971941
Directory	/workspace/3.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1761528085
Short name	T81
Test name
Test status
Simulation time	19041883 ps
CPU time	0.68 seconds
Started	Jul 16 07:10:10 PM PDT 24
Finished	Jul 16 07:10:12 PM PDT 24
Peak memory	201864 kb
Host	smart-45882af0-6aac-4845-a712-6a4f9294a4d6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761528085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1761528085
Directory	/workspace/3.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3046483036
Short name	T976
Test name
Test status
Simulation time	166488136 ps
CPU time	1.68 seconds
Started	Jul 16 07:10:19 PM PDT 24
Finished	Jul 16 07:10:22 PM PDT 24
Peak memory	210444 kb
Host	smart-571d8bc2-d742-4c29-a4e0-a8e63dc019e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046483036 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3046483036
Directory	/workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.662137392
Short name	T997
Test name
Test status
Simulation time	17819332 ps
CPU time	0.67 seconds
Started	Jul 16 07:10:18 PM PDT 24
Finished	Jul 16 07:10:19 PM PDT 24
Peak memory	201808 kb
Host	smart-48a2b667-debe-4cf0-a9db-db10dfd3bb01
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662137392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.sram_ctrl_csr_rw.662137392
Directory	/workspace/3.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3798774885
Short name	T93
Test name
Test status
Simulation time	238444374 ps
CPU time	1.84 seconds
Started	Jul 16 07:10:12 PM PDT 24
Finished	Jul 16 07:10:15 PM PDT 24
Peak memory	202052 kb
Host	smart-4c5ddb64-7c3b-4b5c-8875-b86164fd24e1
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798774885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3798774885
Directory	/workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2426751481
Short name	T975
Test name
Test status
Simulation time	223128972 ps
CPU time	0.8 seconds
Started	Jul 16 07:10:21 PM PDT 24
Finished	Jul 16 07:10:23 PM PDT 24
Peak memory	201948 kb
Host	smart-aeb20583-7bdf-4b75-9ac7-1727fb99a72c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426751481 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2426751481
Directory	/workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2958209961
Short name	T1026
Test name
Test status
Simulation time	70431000 ps
CPU time	1.87 seconds
Started	Jul 16 07:10:17 PM PDT 24
Finished	Jul 16 07:10:20 PM PDT 24
Peak memory	202168 kb
Host	smart-f55011e0-90e9-4d5a-9ca3-8c3ba4775dd2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958209961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.2958209961
Directory	/workspace/3.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3735196192
Short name	T131
Test name
Test status
Simulation time	337829464 ps
CPU time	2.36 seconds
Started	Jul 16 07:10:21 PM PDT 24
Finished	Jul 16 07:10:24 PM PDT 24
Peak memory	210344 kb
Host	smart-632aab67-dd1f-4a3d-9752-dc38c1c404c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735196192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.3735196192
Directory	/workspace/3.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2395753556
Short name	T1011
Test name
Test status
Simulation time	35227088 ps
CPU time	0.71 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:33 PM PDT 24
Peak memory	201392 kb
Host	smart-eed2009e-59c9-45d4-91a8-b324d21cdd68
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395753556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.2395753556
Directory	/workspace/4.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.379191106
Short name	T1022
Test name
Test status
Simulation time	122364011 ps
CPU time	2.04 seconds
Started	Jul 16 07:10:14 PM PDT 24
Finished	Jul 16 07:10:18 PM PDT 24
Peak memory	201940 kb
Host	smart-d24c4749-7f52-46db-85a8-0e5e06810972
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379191106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_bash.379191106
Directory	/workspace/4.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3544011656
Short name	T89
Test name
Test status
Simulation time	15575587 ps
CPU time	0.65 seconds
Started	Jul 16 07:10:20 PM PDT 24
Finished	Jul 16 07:10:22 PM PDT 24
Peak memory	201688 kb
Host	smart-acc471cc-b93f-4e37-ad32-bd583ab9b82c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544011656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.3544011656
Directory	/workspace/4.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2698215522
Short name	T1000
Test name
Test status
Simulation time	43037663 ps
CPU time	1.41 seconds
Started	Jul 16 07:10:28 PM PDT 24
Finished	Jul 16 07:10:31 PM PDT 24
Peak memory	210400 kb
Host	smart-f6fc235b-77b8-4739-912b-b2b36b39d820
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698215522 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2698215522
Directory	/workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2772696910
Short name	T988
Test name
Test status
Simulation time	198739152 ps
CPU time	0.63 seconds
Started	Jul 16 07:10:16 PM PDT 24
Finished	Jul 16 07:10:17 PM PDT 24
Peak memory	201908 kb
Host	smart-4519f613-ff6b-486d-86e7-f79767208acc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772696910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.2772696910
Directory	/workspace/4.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3835578382
Short name	T1030
Test name
Test status
Simulation time	247827941 ps
CPU time	1.86 seconds
Started	Jul 16 07:10:12 PM PDT 24
Finished	Jul 16 07:10:15 PM PDT 24
Peak memory	202104 kb
Host	smart-5b597a2c-7931-4f7f-960d-7b40ee7b92df
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835578382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3835578382
Directory	/workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3567432445
Short name	T1001
Test name
Test status
Simulation time	20235498 ps
CPU time	0.69 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:34 PM PDT 24
Peak memory	202000 kb
Host	smart-a4d74600-0403-4498-aab8-94a94d40cb32
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567432445 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3567432445
Directory	/workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1894962396
Short name	T1017
Test name
Test status
Simulation time	115275215 ps
CPU time	2.64 seconds
Started	Jul 16 07:10:10 PM PDT 24
Finished	Jul 16 07:10:13 PM PDT 24
Peak memory	202192 kb
Host	smart-616875f7-6586-4b88-b7e3-61293437b6a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894962396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.1894962396
Directory	/workspace/4.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3732493454
Short name	T70
Test name
Test status
Simulation time	136375403 ps
CPU time	1.44 seconds
Started	Jul 16 07:10:19 PM PDT 24
Finished	Jul 16 07:10:22 PM PDT 24
Peak memory	202156 kb
Host	smart-ccb539d0-5553-48c5-b297-0cdf806e4a83
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732493454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.3732493454
Directory	/workspace/4.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3073392968
Short name	T978
Test name
Test status
Simulation time	43367705 ps
CPU time	1.53 seconds
Started	Jul 16 07:10:28 PM PDT 24
Finished	Jul 16 07:10:31 PM PDT 24
Peak memory	211548 kb
Host	smart-9ee1c434-8756-44e8-9c5f-564c84bd50ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073392968 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3073392968
Directory	/workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3494759659
Short name	T982
Test name
Test status
Simulation time	28245187 ps
CPU time	0.64 seconds
Started	Jul 16 07:10:24 PM PDT 24
Finished	Jul 16 07:10:26 PM PDT 24
Peak memory	201476 kb
Host	smart-6d6a468f-82cb-4fce-9a47-9b24c466ee5a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494759659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.3494759659
Directory	/workspace/5.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3000355951
Short name	T108
Test name
Test status
Simulation time	509298878 ps
CPU time	3.42 seconds
Started	Jul 16 07:10:28 PM PDT 24
Finished	Jul 16 07:10:33 PM PDT 24
Peak memory	202184 kb
Host	smart-d97d828a-2ae4-404c-95fa-42eabcef9c02
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000355951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3000355951
Directory	/workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4190339351
Short name	T1028
Test name
Test status
Simulation time	28069480 ps
CPU time	0.8 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:28 PM PDT 24
Peak memory	201948 kb
Host	smart-92a5d92b-8121-4d86-bea4-cfc73ab74a8e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190339351 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.4190339351
Directory	/workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.702601590
Short name	T949
Test name
Test status
Simulation time	146791261 ps
CPU time	2.62 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:31 PM PDT 24
Peak memory	202248 kb
Host	smart-d3d27e4c-71d1-4c29-842d-160faea383fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702601590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.702601590
Directory	/workspace/5.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2426641775
Short name	T129
Test name
Test status
Simulation time	193275560 ps
CPU time	2.62 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:29 PM PDT 24
Peak memory	210324 kb
Host	smart-1a74a5de-a9f9-4295-b3b8-522cc508fad0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426641775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.2426641775
Directory	/workspace/5.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1655194251
Short name	T1014
Test name
Test status
Simulation time	42217457 ps
CPU time	2.59 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:31 PM PDT 24
Peak memory	210420 kb
Host	smart-6f4c02f6-8d79-457b-a115-ddc45dbb2fdd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655194251 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.1655194251
Directory	/workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.35368160
Short name	T999
Test name
Test status
Simulation time	20889755 ps
CPU time	0.66 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:27 PM PDT 24
Peak memory	201908 kb
Host	smart-c3e004a1-8337-4225-834d-c0b452ef2ef5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35368160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 6.sram_ctrl_csr_rw.35368160
Directory	/workspace/6.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3254266472
Short name	T1019
Test name
Test status
Simulation time	595061016 ps
CPU time	3.7 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:32 PM PDT 24
Peak memory	202304 kb
Host	smart-74295fc1-ef32-4e6f-ab28-4353f4b7ed9d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254266472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3254266472
Directory	/workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.877692528
Short name	T998
Test name
Test status
Simulation time	23802706 ps
CPU time	0.77 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:27 PM PDT 24
Peak memory	201952 kb
Host	smart-3c831335-8daf-4d7a-9a7c-1c1cc6649068
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877692528 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.877692528
Directory	/workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.690568402
Short name	T1012
Test name
Test status
Simulation time	518052952 ps
CPU time	4.57 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:38 PM PDT 24
Peak memory	210436 kb
Host	smart-6122725f-f771-4ca5-a8ee-f1ad095740d4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690568402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.690568402
Directory	/workspace/6.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2349674665
Short name	T69
Test name
Test status
Simulation time	196159526 ps
CPU time	1.59 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:35 PM PDT 24
Peak memory	210364 kb
Host	smart-21be5b9c-f8ce-4818-9fec-f087162703d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349674665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.2349674665
Directory	/workspace/6.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3081326895
Short name	T965
Test name
Test status
Simulation time	367323348 ps
CPU time	1.22 seconds
Started	Jul 16 07:10:29 PM PDT 24
Finished	Jul 16 07:10:31 PM PDT 24
Peak memory	210256 kb
Host	smart-7cde4749-e24c-42e7-8821-0f368b164321
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081326895 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3081326895
Directory	/workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3595275769
Short name	T1016
Test name
Test status
Simulation time	111330070 ps
CPU time	0.63 seconds
Started	Jul 16 07:10:28 PM PDT 24
Finished	Jul 16 07:10:30 PM PDT 24
Peak memory	201876 kb
Host	smart-b89d95ab-ac08-42bb-b59b-0bc88d59a8c3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595275769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.3595275769
Directory	/workspace/7.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2301383681
Short name	T1002
Test name
Test status
Simulation time	215107911 ps
CPU time	1.96 seconds
Started	Jul 16 07:10:29 PM PDT 24
Finished	Jul 16 07:10:32 PM PDT 24
Peak memory	202132 kb
Host	smart-bbb4f93b-1273-4ece-81a0-e0003803ba5c
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301383681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2301383681
Directory	/workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.659383619
Short name	T953
Test name
Test status
Simulation time	38029390 ps
CPU time	0.67 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:28 PM PDT 24
Peak memory	201988 kb
Host	smart-f4805e1f-d4a5-4e49-b9e9-0368bc58d8c7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659383619 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.659383619
Directory	/workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2595082830
Short name	T963
Test name
Test status
Simulation time	1459425235 ps
CPU time	4.74 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:37 PM PDT 24
Peak memory	202300 kb
Host	smart-669284dc-08cc-4db2-827e-c1e69ee2b798
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595082830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.2595082830
Directory	/workspace/7.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.452680330
Short name	T954
Test name
Test status
Simulation time	340405890 ps
CPU time	1.56 seconds
Started	Jul 16 07:10:28 PM PDT 24
Finished	Jul 16 07:10:31 PM PDT 24
Peak memory	210352 kb
Host	smart-537ef33b-2e1c-4d0c-ade8-d8fba26792b1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452680330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.sram_ctrl_tl_intg_err.452680330
Directory	/workspace/7.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2394140261
Short name	T948
Test name
Test status
Simulation time	41795175 ps
CPU time	2.24 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:30 PM PDT 24
Peak memory	210308 kb
Host	smart-e2e19d56-08c9-4ef9-832b-d9141293765b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394140261 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2394140261
Directory	/workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2334545790
Short name	T88
Test name
Test status
Simulation time	12091554 ps
CPU time	0.64 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:28 PM PDT 24
Peak memory	201888 kb
Host	smart-c92706fa-42bd-4747-9853-540b1946ecb7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334545790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.2334545790
Directory	/workspace/8.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4152104813
Short name	T87
Test name
Test status
Simulation time	456900266 ps
CPU time	3.34 seconds
Started	Jul 16 07:10:32 PM PDT 24
Finished	Jul 16 07:10:37 PM PDT 24
Peak memory	202292 kb
Host	smart-9179cc12-8826-4f3e-9c88-64317c4f43f6
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152104813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.4152104813
Directory	/workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2810218157
Short name	T967
Test name
Test status
Simulation time	31175445 ps
CPU time	0.8 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:29 PM PDT 24
Peak memory	201956 kb
Host	smart-a19da1be-6ad5-4996-bacb-899b8ace63fb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810218157 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2810218157
Directory	/workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2576353255
Short name	T960
Test name
Test status
Simulation time	314120489 ps
CPU time	5.86 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:33 PM PDT 24
Peak memory	211496 kb
Host	smart-0b04cbf0-7311-413b-ab3c-4ea2e4109f33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576353255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.2576353255
Directory	/workspace/8.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2257926082
Short name	T126
Test name
Test status
Simulation time	693989371 ps
CPU time	2.41 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:30 PM PDT 24
Peak memory	210308 kb
Host	smart-c2abd236-e8bd-40d2-adad-27f22cc7b54c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257926082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.2257926082
Directory	/workspace/8.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3319360950
Short name	T1027
Test name
Test status
Simulation time	57129256 ps
CPU time	0.68 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:27 PM PDT 24
Peak memory	201464 kb
Host	smart-6e109ed3-09f7-4bb8-b457-1993718a687b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319360950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.3319360950
Directory	/workspace/9.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3249286373
Short name	T110
Test name
Test status
Simulation time	345773721 ps
CPU time	2.02 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:29 PM PDT 24
Peak memory	202100 kb
Host	smart-9c1ca04a-0627-4491-9440-4de17ca092af
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249286373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3249286373
Directory	/workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1621109767
Short name	T971
Test name
Test status
Simulation time	99718230 ps
CPU time	0.78 seconds
Started	Jul 16 07:10:25 PM PDT 24
Finished	Jul 16 07:10:28 PM PDT 24
Peak memory	201976 kb
Host	smart-754f7b42-7213-4381-b066-ba5982e8d9bc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621109767 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1621109767
Directory	/workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1442501770
Short name	T980
Test name
Test status
Simulation time	70642352 ps
CPU time	2.48 seconds
Started	Jul 16 07:10:26 PM PDT 24
Finished	Jul 16 07:10:30 PM PDT 24
Peak memory	210368 kb
Host	smart-01c0c49d-df53-4981-a136-11ecf63d67b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442501770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.1442501770
Directory	/workspace/9.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.845328235
Short name	T991
Test name
Test status
Simulation time	196850664 ps
CPU time	1.39 seconds
Started	Jul 16 07:10:29 PM PDT 24
Finished	Jul 16 07:10:31 PM PDT 24
Peak memory	210412 kb
Host	smart-734bb61f-77fe-452d-ab66-f9858fed80d6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845328235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.sram_ctrl_tl_intg_err.845328235
Directory	/workspace/9.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1982773837
Short name	T649
Test name
Test status
Simulation time	25213206671 ps
CPU time	1135.12 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 08:00:16 PM PDT 24
Peak memory	373724 kb
Host	smart-37efcb5a-9dd9-4583-9b66-ec591bebcbd5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982773837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.1982773837
Directory	/workspace/0.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/0.sram_ctrl_alert_test.694266576
Short name	T338
Test name
Test status
Simulation time	13917616 ps
CPU time	0.66 seconds
Started	Jul 16 07:41:10 PM PDT 24
Finished	Jul 16 07:41:25 PM PDT 24
Peak memory	202580 kb
Host	smart-b5eaa4d5-9086-4c34-9e6b-586514899e6f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694266576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.694266576
Directory	/workspace/0.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.sram_ctrl_bijection.3060342258
Short name	T326
Test name
Test status
Simulation time	26140689155 ps
CPU time	86.72 seconds
Started	Jul 16 07:41:05 PM PDT 24
Finished	Jul 16 07:42:37 PM PDT 24
Peak memory	202880 kb
Host	smart-a3473634-1901-4e82-9bf6-269667e14262
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060342258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 3060342258
Directory	/workspace/0.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/0.sram_ctrl_executable.1615585294
Short name	T244
Test name
Test status
Simulation time	30004328831 ps
CPU time	723.7 seconds
Started	Jul 16 07:41:12 PM PDT 24
Finished	Jul 16 07:53:31 PM PDT 24
Peak memory	375452 kb
Host	smart-3c3976f6-2cb1-4fec-a5c7-08d192030200
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615585294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.1615585294
Directory	/workspace/0.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/0.sram_ctrl_lc_escalation.2978892938
Short name	T5
Test name
Test status
Simulation time	692701279 ps
CPU time	4.32 seconds
Started	Jul 16 07:41:11 PM PDT 24
Finished	Jul 16 07:41:29 PM PDT 24
Peak memory	202868 kb
Host	smart-b0ae8a9f-3586-437b-bdf0-348413251662
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978892938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.2978892938
Directory	/workspace/0.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/0.sram_ctrl_max_throughput.2303499088
Short name	T667
Test name
Test status
Simulation time	123952460 ps
CPU time	98.55 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:42:58 PM PDT 24
Peak memory	340836 kb
Host	smart-ca8dd606-1220-4677-999b-9477a10f6e17
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303499088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.2303499088
Directory	/workspace/0.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2785245270
Short name	T543
Test name
Test status
Simulation time	97182293 ps
CPU time	4.75 seconds
Started	Jul 16 07:41:09 PM PDT 24
Finished	Jul 16 07:41:26 PM PDT 24
Peak memory	211108 kb
Host	smart-32f0be3e-1fbd-487a-a353-32a4a424a372
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785245270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.2785245270
Directory	/workspace/0.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_walk.1552099468
Short name	T55
Test name
Test status
Simulation time	1471989802 ps
CPU time	10.83 seconds
Started	Jul 16 07:41:09 PM PDT 24
Finished	Jul 16 07:41:32 PM PDT 24
Peak memory	211088 kb
Host	smart-cdb9a350-54b5-4108-8baf-d5b88c79a40d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552099468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.1552099468
Directory	/workspace/0.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/0.sram_ctrl_multiple_keys.3085188582
Short name	T164
Test name
Test status
Simulation time	9076887361 ps
CPU time	285.65 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:46:05 PM PDT 24
Peak memory	321480 kb
Host	smart-2fe42ecf-a8ad-4a18-9035-8f1f3ef99f10
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085188582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.3085188582
Directory	/workspace/0.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access.3353321041
Short name	T797
Test name
Test status
Simulation time	493437777 ps
CPU time	50.42 seconds
Started	Jul 16 07:41:07 PM PDT 24
Finished	Jul 16 07:42:07 PM PDT 24
Peak memory	301044 kb
Host	smart-6784efb5-4b01-49d9-a88c-6b205b46c19d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353321041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.3353321041
Directory	/workspace/0.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2180949789
Short name	T714
Test name
Test status
Simulation time	8029779032 ps
CPU time	155.15 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:43:55 PM PDT 24
Peak memory	202932 kb
Host	smart-1f9ff53c-19ef-41ae-9c3f-a22c5c2515e2
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180949789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.2180949789
Directory	/workspace/0.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/0.sram_ctrl_ram_cfg.3834693750
Short name	T776
Test name
Test status
Simulation time	29644178 ps
CPU time	0.78 seconds
Started	Jul 16 07:41:06 PM PDT 24
Finished	Jul 16 07:41:15 PM PDT 24
Peak memory	202880 kb
Host	smart-6e24b0f6-b80d-4395-bf54-38a571299fa4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834693750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3834693750
Directory	/workspace/0.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/0.sram_ctrl_regwen.373672739
Short name	T937
Test name
Test status
Simulation time	87671176781 ps
CPU time	1566.42 seconds
Started	Jul 16 07:41:05 PM PDT 24
Finished	Jul 16 08:07:16 PM PDT 24
Peak memory	374740 kb
Host	smart-25f35283-28c3-4aea-9c79-e72a04a777cc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373672739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.373672739
Directory	/workspace/0.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/0.sram_ctrl_smoke.399795503
Short name	T385
Test name
Test status
Simulation time	183557881 ps
CPU time	10.94 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:41:30 PM PDT 24
Peak memory	202760 kb
Host	smart-6b893879-7c0b-4b0c-bfe0-5809ee43bbc6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399795503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.399795503
Directory	/workspace/0.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all.1616030479
Short name	T365
Test name
Test status
Simulation time	191940353228 ps
CPU time	6272.73 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 09:25:54 PM PDT 24
Peak memory	375736 kb
Host	smart-e4bf95f5-293b-4c84-981f-1f3f1a27513d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616030479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.1616030479
Directory	/workspace/0.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.31487660
Short name	T173
Test name
Test status
Simulation time	10620401827 ps
CPU time	228.38 seconds
Started	Jul 16 07:41:05 PM PDT 24
Finished	Jul 16 07:44:58 PM PDT 24
Peak memory	202900 kb
Host	smart-5c7acbc3-f1d2-4b1a-b711-736fa497fab3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31487660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_stress_pipeline.31487660
Directory	/workspace/0.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4062179191
Short name	T486
Test name
Test status
Simulation time	928436775 ps
CPU time	93.64 seconds
Started	Jul 16 07:41:07 PM PDT 24
Finished	Jul 16 07:42:49 PM PDT 24
Peak memory	361248 kb
Host	smart-854f3617-0c46-420e-95ad-2ca6b378c731
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062179191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.4062179191
Directory	/workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1853575785
Short name	T467
Test name
Test status
Simulation time	21768333737 ps
CPU time	1051.64 seconds
Started	Jul 16 07:41:10 PM PDT 24
Finished	Jul 16 07:58:55 PM PDT 24
Peak memory	372680 kb
Host	smart-ab4da6ba-e09a-4b66-a77b-1a87b6e7232d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853575785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.1853575785
Directory	/workspace/1.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/1.sram_ctrl_alert_test.3487572215
Short name	T286
Test name
Test status
Simulation time	26365532 ps
CPU time	0.64 seconds
Started	Jul 16 07:41:11 PM PDT 24
Finished	Jul 16 07:41:27 PM PDT 24
Peak memory	202288 kb
Host	smart-aa5a1af4-2912-4ff0-ab82-2ff855e62d60
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487572215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.3487572215
Directory	/workspace/1.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.sram_ctrl_bijection.3641820542
Short name	T729
Test name
Test status
Simulation time	3383683166 ps
CPU time	61.85 seconds
Started	Jul 16 07:41:07 PM PDT 24
Finished	Jul 16 07:42:18 PM PDT 24
Peak memory	202896 kb
Host	smart-90bd94c0-9257-42d3-9c4d-dfa2b66e48a6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641820542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 3641820542
Directory	/workspace/1.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/1.sram_ctrl_executable.375164003
Short name	T343
Test name
Test status
Simulation time	20699708082 ps
CPU time	229.44 seconds
Started	Jul 16 07:41:10 PM PDT 24
Finished	Jul 16 07:45:13 PM PDT 24
Peak memory	373024 kb
Host	smart-80b31a7f-43cb-42e4-9e6f-c6bf3b67f5c0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375164003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable .375164003
Directory	/workspace/1.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/1.sram_ctrl_lc_escalation.1363026281
Short name	T163
Test name
Test status
Simulation time	5313909916 ps
CPU time	6.34 seconds
Started	Jul 16 07:41:12 PM PDT 24
Finished	Jul 16 07:41:34 PM PDT 24
Peak memory	202960 kb
Host	smart-1c440b0d-c136-4f41-8c06-7e12bad1509e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363026281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.1363026281
Directory	/workspace/1.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/1.sram_ctrl_max_throughput.2096292456
Short name	T384
Test name
Test status
Simulation time	179143298 ps
CPU time	20.34 seconds
Started	Jul 16 07:41:09 PM PDT 24
Finished	Jul 16 07:41:43 PM PDT 24
Peak memory	286416 kb
Host	smart-1c17c8b7-71e0-4aca-97b9-18ad4e2f72ff
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096292456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.2096292456
Directory	/workspace/1.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_walk.167239194
Short name	T653
Test name
Test status
Simulation time	400847558 ps
CPU time	9.35 seconds
Started	Jul 16 07:41:10 PM PDT 24
Finished	Jul 16 07:41:32 PM PDT 24
Peak memory	211128 kb
Host	smart-e916d8e8-c730-46c2-85a6-649f4cba8163
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167239194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ mem_walk.167239194
Directory	/workspace/1.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/1.sram_ctrl_multiple_keys.3385246361
Short name	T613
Test name
Test status
Simulation time	61904885261 ps
CPU time	441.22 seconds
Started	Jul 16 07:41:12 PM PDT 24
Finished	Jul 16 07:48:49 PM PDT 24
Peak memory	348264 kb
Host	smart-b97a17f0-6dd2-4dd7-befb-adca92802c0b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385246361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.3385246361
Directory	/workspace/1.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access.3412222042
Short name	T634
Test name
Test status
Simulation time	132742668 ps
CPU time	5.64 seconds
Started	Jul 16 07:41:10 PM PDT 24
Finished	Jul 16 07:41:29 PM PDT 24
Peak memory	202796 kb
Host	smart-eea69906-e53f-4e71-9e5e-9a335dbd9b22
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412222042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.3412222042
Directory	/workspace/1.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2340923855
Short name	T432
Test name
Test status
Simulation time	4422064343 ps
CPU time	312.67 seconds
Started	Jul 16 07:41:06 PM PDT 24
Finished	Jul 16 07:46:26 PM PDT 24
Peak memory	202900 kb
Host	smart-cb6ae7da-6eea-4fc1-91bd-30138ecbe04a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340923855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.2340923855
Directory	/workspace/1.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/1.sram_ctrl_ram_cfg.242401645
Short name	T804
Test name
Test status
Simulation time	49577503 ps
CPU time	0.75 seconds
Started	Jul 16 07:41:11 PM PDT 24
Finished	Jul 16 07:41:25 PM PDT 24
Peak memory	202864 kb
Host	smart-0e1356ac-fb7e-4616-93e9-3e8f11eb1c10
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242401645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.242401645
Directory	/workspace/1.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/1.sram_ctrl_regwen.2585233061
Short name	T861
Test name
Test status
Simulation time	18837247683 ps
CPU time	655.08 seconds
Started	Jul 16 07:41:11 PM PDT 24
Finished	Jul 16 07:52:20 PM PDT 24
Peak memory	370604 kb
Host	smart-594f8c65-3878-4501-9e63-25ab48b236b8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585233061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2585233061
Directory	/workspace/1.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/1.sram_ctrl_sec_cm.3917654411
Short name	T18
Test name
Test status
Simulation time	1347298968 ps
CPU time	1.87 seconds
Started	Jul 16 07:41:13 PM PDT 24
Finished	Jul 16 07:41:34 PM PDT 24
Peak memory	221600 kb
Host	smart-5f984804-1ffe-45e3-b8dd-7630e170e2e8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917654411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3917654411
Directory	/workspace/1.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.sram_ctrl_smoke.3149443664
Short name	T820
Test name
Test status
Simulation time	491689582 ps
CPU time	4.96 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:41:24 PM PDT 24
Peak memory	222464 kb
Host	smart-2c3dd0e0-6fb1-44e6-b9a1-c4f57c8954ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149443664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3149443664
Directory	/workspace/1.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all.1663379849
Short name	T565
Test name
Test status
Simulation time	17520797788 ps
CPU time	5972.63 seconds
Started	Jul 16 07:41:10 PM PDT 24
Finished	Jul 16 09:20:58 PM PDT 24
Peak memory	383924 kb
Host	smart-d22ec416-4fa9-45d0-bb5e-a13a26326ff9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663379849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.1663379849
Directory	/workspace/1.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3608246952
Short name	T617
Test name
Test status
Simulation time	632301821 ps
CPU time	153.4 seconds
Started	Jul 16 07:41:13 PM PDT 24
Finished	Jul 16 07:44:04 PM PDT 24
Peak memory	373156 kb
Host	smart-dcbf8956-d677-4767-a793-87aa39638a28
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3608246952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3608246952
Directory	/workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.739543919
Short name	T60
Test name
Test status
Simulation time	3056205921 ps
CPU time	282.12 seconds
Started	Jul 16 07:41:10 PM PDT 24
Finished	Jul 16 07:46:07 PM PDT 24
Peak memory	202904 kb
Host	smart-15cc3969-18cc-4457-83d3-e7b131a28fe7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739543919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. sram_ctrl_stress_pipeline.739543919
Directory	/workspace/1.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.958314619
Short name	T497
Test name
Test status
Simulation time	376862023 ps
CPU time	27.8 seconds
Started	Jul 16 07:41:07 PM PDT 24
Finished	Jul 16 07:41:47 PM PDT 24
Peak memory	285528 kb
Host	smart-cd1c90a3-9d35-432a-bbcf-b392c71ce700
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958314619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.958314619
Directory	/workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1250492954
Short name	T875
Test name
Test status
Simulation time	24497841938 ps
CPU time	633.09 seconds
Started	Jul 16 07:41:48 PM PDT 24
Finished	Jul 16 07:52:35 PM PDT 24
Peak memory	373700 kb
Host	smart-5703f007-85eb-46c5-b6b7-88b62d233710
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250492954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.1250492954
Directory	/workspace/10.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/10.sram_ctrl_alert_test.2028045513
Short name	T402
Test name
Test status
Simulation time	12679149 ps
CPU time	0.66 seconds
Started	Jul 16 07:41:49 PM PDT 24
Finished	Jul 16 07:42:03 PM PDT 24
Peak memory	202656 kb
Host	smart-ad3005c5-d837-4f0c-bbe4-6dc48ffef033
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028045513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.2028045513
Directory	/workspace/10.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.sram_ctrl_bijection.967989110
Short name	T139
Test name
Test status
Simulation time	897345920 ps
CPU time	55.16 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:42:41 PM PDT 24
Peak memory	202816 kb
Host	smart-41170e8f-1b5a-49a1-90b0-c5a1a13f7785
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967989110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection. 967989110
Directory	/workspace/10.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/10.sram_ctrl_executable.1316505210
Short name	T182
Test name
Test status
Simulation time	1088153404 ps
CPU time	12.57 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:42:16 PM PDT 24
Peak memory	232308 kb
Host	smart-d2fe3783-0e90-46fd-9ddd-ce08198e0711
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316505210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.1316505210
Directory	/workspace/10.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/10.sram_ctrl_lc_escalation.3803578598
Short name	T412
Test name
Test status
Simulation time	2652132098 ps
CPU time	7.86 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 07:42:15 PM PDT 24
Peak memory	202852 kb
Host	smart-eab19e93-2278-4d51-864a-170959754e4f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803578598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.3803578598
Directory	/workspace/10.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/10.sram_ctrl_max_throughput.2221468744
Short name	T193
Test name
Test status
Simulation time	145046950 ps
CPU time	123.06 seconds
Started	Jul 16 07:41:27 PM PDT 24
Finished	Jul 16 07:43:52 PM PDT 24
Peak memory	366524 kb
Host	smart-5df9f438-9323-48e8-8bc0-7db8e57527da
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221468744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.2221468744
Directory	/workspace/10.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2343854134
Short name	T575
Test name
Test status
Simulation time	387362861 ps
CPU time	5.93 seconds
Started	Jul 16 07:41:45 PM PDT 24
Finished	Jul 16 07:42:06 PM PDT 24
Peak memory	211012 kb
Host	smart-c2961e12-92fe-47a7-bea7-49f50012c094
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343854134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.2343854134
Directory	/workspace/10.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_walk.1682466303
Short name	T250
Test name
Test status
Simulation time	761091977 ps
CPU time	11.05 seconds
Started	Jul 16 07:41:55 PM PDT 24
Finished	Jul 16 07:42:18 PM PDT 24
Peak memory	211036 kb
Host	smart-1c20bac3-8025-4fa6-a7a0-0a3d52cb5ff9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682466303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.1682466303
Directory	/workspace/10.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/10.sram_ctrl_multiple_keys.2295657765
Short name	T677
Test name
Test status
Simulation time	6560768130 ps
CPU time	637.53 seconds
Started	Jul 16 07:41:27 PM PDT 24
Finished	Jul 16 07:52:26 PM PDT 24
Peak memory	371684 kb
Host	smart-afdb3b1f-afe6-4e62-8c5a-a9a3b762e166
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295657765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2295657765
Directory	/workspace/10.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access.355587163
Short name	T550
Test name
Test status
Simulation time	351496627 ps
CPU time	13.14 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:42:03 PM PDT 24
Peak memory	252072 kb
Host	smart-5cd961d4-d3de-4825-9f6b-a70ddd33cf36
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355587163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.s ram_ctrl_partial_access.355587163
Directory	/workspace/10.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1671147065
Short name	T187
Test name
Test status
Simulation time	56925214815 ps
CPU time	410.3 seconds
Started	Jul 16 07:41:27 PM PDT 24
Finished	Jul 16 07:48:40 PM PDT 24
Peak memory	202940 kb
Host	smart-f3378479-161d-48b3-accc-6dddc727fe60
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671147065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.1671147065
Directory	/workspace/10.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/10.sram_ctrl_ram_cfg.241661006
Short name	T251
Test name
Test status
Simulation time	191107419 ps
CPU time	0.79 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 07:42:07 PM PDT 24
Peak memory	202872 kb
Host	smart-ee708bfe-85d7-4671-a351-4a00dcc43184
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241661006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.241661006
Directory	/workspace/10.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/10.sram_ctrl_regwen.2744385781
Short name	T853
Test name
Test status
Simulation time	13726378782 ps
CPU time	1187.14 seconds
Started	Jul 16 07:41:50 PM PDT 24
Finished	Jul 16 08:01:50 PM PDT 24
Peak memory	368584 kb
Host	smart-f521bb41-03cb-46ed-bc2c-07180326ddcb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744385781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2744385781
Directory	/workspace/10.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/10.sram_ctrl_smoke.2812119166
Short name	T65
Test name
Test status
Simulation time	167212717 ps
CPU time	3.02 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:41:53 PM PDT 24
Peak memory	210308 kb
Host	smart-9540b852-4325-4507-9e3b-c532df1cb67d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812119166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2812119166
Directory	/workspace/10.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all.495028750
Short name	T136
Test name
Test status
Simulation time	15226263884 ps
CPU time	4046.75 seconds
Started	Jul 16 07:41:52 PM PDT 24
Finished	Jul 16 08:49:32 PM PDT 24
Peak memory	375760 kb
Host	smart-9cb80699-6f78-4aaa-87b5-5a2de5c78aa7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495028750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_stress_all.495028750
Directory	/workspace/10.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.904657030
Short name	T26
Test name
Test status
Simulation time	4557411878 ps
CPU time	106.42 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:43:50 PM PDT 24
Peak memory	337024 kb
Host	smart-1b4762e3-9e45-41bf-99b6-f5964c46ffd1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=904657030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.904657030
Directory	/workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3043623949
Short name	T513
Test name
Test status
Simulation time	50179325427 ps
CPU time	295.85 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:46:42 PM PDT 24
Peak memory	202856 kb
Host	smart-2609b3e1-fbfd-4406-a094-c8e55e6bdc39
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043623949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.3043623949
Directory	/workspace/10.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2121494310
Short name	T73
Test name
Test status
Simulation time	535576251 ps
CPU time	9.97 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:41:59 PM PDT 24
Peak memory	240032 kb
Host	smart-84b887b5-4fd0-4570-ada5-f5c7e8d6f11b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121494310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2121494310
Directory	/workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.383766744
Short name	T328
Test name
Test status
Simulation time	8395594252 ps
CPU time	455.72 seconds
Started	Jul 16 07:41:55 PM PDT 24
Finished	Jul 16 07:49:42 PM PDT 24
Peak memory	375844 kb
Host	smart-1e2317ab-4946-44c1-aa53-d01bca5a7a99
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383766744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_access_during_key_req.383766744
Directory	/workspace/11.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/11.sram_ctrl_alert_test.3392171580
Short name	T838
Test name
Test status
Simulation time	34327627 ps
CPU time	0.69 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:09 PM PDT 24
Peak memory	202624 kb
Host	smart-57d16b18-a4fa-4c44-a998-cc2f839ec3a4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392171580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3392171580
Directory	/workspace/11.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.sram_ctrl_bijection.175287926
Short name	T471
Test name
Test status
Simulation time	766732069 ps
CPU time	50.16 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 07:42:58 PM PDT 24
Peak memory	202768 kb
Host	smart-c098cf4f-ed79-4d24-9980-06fcd8f5ac69
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175287926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection. 175287926
Directory	/workspace/11.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/11.sram_ctrl_executable.4097385250
Short name	T635
Test name
Test status
Simulation time	211685904 ps
CPU time	115.65 seconds
Started	Jul 16 07:41:45 PM PDT 24
Finished	Jul 16 07:43:57 PM PDT 24
Peak memory	367268 kb
Host	smart-73955277-a996-4782-a7da-d0f053a6c542
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097385250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.4097385250
Directory	/workspace/11.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/11.sram_ctrl_lc_escalation.1873308783
Short name	T719
Test name
Test status
Simulation time	2467374965 ps
CPU time	3.57 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 07:42:11 PM PDT 24
Peak memory	202756 kb
Host	smart-22c73968-fed4-427d-8aa0-4238f90c531c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873308783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1873308783
Directory	/workspace/11.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/11.sram_ctrl_max_throughput.2578449304
Short name	T424
Test name
Test status
Simulation time	191995783 ps
CPU time	5.09 seconds
Started	Jul 16 07:41:48 PM PDT 24
Finished	Jul 16 07:42:07 PM PDT 24
Peak memory	226972 kb
Host	smart-b0cc9935-8562-4178-a622-b8de85f0df93
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578449304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.2578449304
Directory	/workspace/11.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3715739438
Short name	T538
Test name
Test status
Simulation time	107107117 ps
CPU time	3.17 seconds
Started	Jul 16 07:41:52 PM PDT 24
Finished	Jul 16 07:42:08 PM PDT 24
Peak memory	211100 kb
Host	smart-a952fda5-b466-45e4-b122-d7839bda89cf
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715739438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.3715739438
Directory	/workspace/11.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_walk.1856179547
Short name	T476
Test name
Test status
Simulation time	95512780 ps
CPU time	5.67 seconds
Started	Jul 16 07:41:50 PM PDT 24
Finished	Jul 16 07:42:08 PM PDT 24
Peak memory	211116 kb
Host	smart-e4fc8ed3-fff8-4cad-aa09-b8d72d0bf178
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856179547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.1856179547
Directory	/workspace/11.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/11.sram_ctrl_multiple_keys.661425390
Short name	T748
Test name
Test status
Simulation time	33095505116 ps
CPU time	640.21 seconds
Started	Jul 16 07:41:47 PM PDT 24
Finished	Jul 16 07:52:42 PM PDT 24
Peak memory	358500 kb
Host	smart-831edba4-32c5-459f-8193-125abaf126e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661425390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multip le_keys.661425390
Directory	/workspace/11.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access.1896413589
Short name	T798
Test name
Test status
Simulation time	3304857680 ps
CPU time	153.37 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 07:44:42 PM PDT 24
Peak memory	367056 kb
Host	smart-14bc38df-3c1f-49be-ae89-4766ee7a98f5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896413589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.1896413589
Directory	/workspace/11.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1398012170
Short name	T694
Test name
Test status
Simulation time	14450429354 ps
CPU time	252.97 seconds
Started	Jul 16 07:41:47 PM PDT 24
Finished	Jul 16 07:46:15 PM PDT 24
Peak memory	202900 kb
Host	smart-af8b341d-ab3d-43fb-a81d-74640a6750fc
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398012170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.1398012170
Directory	/workspace/11.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/11.sram_ctrl_ram_cfg.2813063105
Short name	T200
Test name
Test status
Simulation time	134444191 ps
CPU time	0.79 seconds
Started	Jul 16 07:41:49 PM PDT 24
Finished	Jul 16 07:42:04 PM PDT 24
Peak memory	202804 kb
Host	smart-6fe397c7-0892-4e66-83ce-bda16f010e95
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813063105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2813063105
Directory	/workspace/11.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/11.sram_ctrl_regwen.1937087036
Short name	T195
Test name
Test status
Simulation time	6896809456 ps
CPU time	1052.78 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:59:36 PM PDT 24
Peak memory	372480 kb
Host	smart-0bbf1255-1364-49e1-86a7-88f64bd1c4c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937087036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1937087036
Directory	/workspace/11.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/11.sram_ctrl_smoke.2564843371
Short name	T491
Test name
Test status
Simulation time	736307839 ps
CPU time	35.64 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:42:39 PM PDT 24
Peak memory	293336 kb
Host	smart-77cfc9cf-ea7b-48a9-9755-b05c43f08641
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564843371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2564843371
Directory	/workspace/11.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_all.4278260610
Short name	T243
Test name
Test status
Simulation time	11435194184 ps
CPU time	2770.87 seconds
Started	Jul 16 07:41:47 PM PDT 24
Finished	Jul 16 08:28:13 PM PDT 24
Peak memory	376960 kb
Host	smart-ee96347f-db33-472b-b39c-f8e39df18221
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278260610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.4278260610
Directory	/workspace/11.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1349845215
Short name	T121
Test name
Test status
Simulation time	6772231030 ps
CPU time	139.95 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:44:23 PM PDT 24
Peak memory	332444 kb
Host	smart-6c33a8dd-5a49-46a2-800a-88791d432b62
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1349845215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1349845215
Directory	/workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.686846371
Short name	T246
Test name
Test status
Simulation time	2597331458 ps
CPU time	261.93 seconds
Started	Jul 16 07:41:54 PM PDT 24
Finished	Jul 16 07:46:27 PM PDT 24
Peak memory	202880 kb
Host	smart-85fecd22-3827-4c57-981d-9b7ff469a930
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686846371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sram_ctrl_stress_pipeline.686846371
Directory	/workspace/11.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3463504560
Short name	T530
Test name
Test status
Simulation time	238203293 ps
CPU time	104.73 seconds
Started	Jul 16 07:41:46 PM PDT 24
Finished	Jul 16 07:43:46 PM PDT 24
Peak memory	347668 kb
Host	smart-5b058dc6-044d-409e-ab86-32beca180fcc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463504560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3463504560
Directory	/workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3264864082
Short name	T735
Test name
Test status
Simulation time	3807276227 ps
CPU time	838.73 seconds
Started	Jul 16 07:41:55 PM PDT 24
Finished	Jul 16 07:56:05 PM PDT 24
Peak memory	361268 kb
Host	smart-0b987c9b-8383-471c-a64a-e157cb0c0d2f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264864082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.3264864082
Directory	/workspace/12.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/12.sram_ctrl_alert_test.3063414343
Short name	T324
Test name
Test status
Simulation time	154772901 ps
CPU time	0.65 seconds
Started	Jul 16 07:41:50 PM PDT 24
Finished	Jul 16 07:42:03 PM PDT 24
Peak memory	202680 kb
Host	smart-e2d190e0-a9f2-447d-b356-96bd53ef6184
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063414343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3063414343
Directory	/workspace/12.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.sram_ctrl_bijection.1289703789
Short name	T840
Test name
Test status
Simulation time	9970306745 ps
CPU time	40.48 seconds
Started	Jul 16 07:41:48 PM PDT 24
Finished	Jul 16 07:42:43 PM PDT 24
Peak memory	202952 kb
Host	smart-93d551d8-2f9d-45ca-bfb6-5b813ed52a25
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289703789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .1289703789
Directory	/workspace/12.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/12.sram_ctrl_executable.1582727681
Short name	T396
Test name
Test status
Simulation time	9904768158 ps
CPU time	939.05 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 07:57:49 PM PDT 24
Peak memory	375720 kb
Host	smart-704c544c-4f74-4bbc-b09c-eaea64e29ab1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582727681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.1582727681
Directory	/workspace/12.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/12.sram_ctrl_lc_escalation.2266794074
Short name	T658
Test name
Test status
Simulation time	3345638867 ps
CPU time	9.53 seconds
Started	Jul 16 07:41:47 PM PDT 24
Finished	Jul 16 07:42:12 PM PDT 24
Peak memory	202928 kb
Host	smart-8cc0ad9d-22cd-454f-a8c6-761361313b27
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266794074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.2266794074
Directory	/workspace/12.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/12.sram_ctrl_max_throughput.4149326565
Short name	T607
Test name
Test status
Simulation time	123446830 ps
CPU time	61.79 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:43:05 PM PDT 24
Peak memory	344904 kb
Host	smart-d615eba8-a2dc-4b4d-82e1-328252e96796
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149326565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.4149326565
Directory	/workspace/12.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1577791357
Short name	T352
Test name
Test status
Simulation time	342578596 ps
CPU time	4.55 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:42:08 PM PDT 24
Peak memory	211052 kb
Host	smart-f00abc70-f1b5-4b42-a0a4-112edbb26755
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577791357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.1577791357
Directory	/workspace/12.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_walk.595886017
Short name	T235
Test name
Test status
Simulation time	240333673 ps
CPU time	5.73 seconds
Started	Jul 16 07:41:54 PM PDT 24
Finished	Jul 16 07:42:11 PM PDT 24
Peak memory	210996 kb
Host	smart-2528c415-f5c5-45e3-816f-fe8f7d529537
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595886017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _mem_walk.595886017
Directory	/workspace/12.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/12.sram_ctrl_multiple_keys.3553557962
Short name	T540
Test name
Test status
Simulation time	80573541105 ps
CPU time	1566.32 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 08:08:16 PM PDT 24
Peak memory	376088 kb
Host	smart-3a4d4b07-ffaa-41fb-9056-fc6f1749d883
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553557962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.3553557962
Directory	/workspace/12.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access.3767424050
Short name	T837
Test name
Test status
Simulation time	180925230 ps
CPU time	82.61 seconds
Started	Jul 16 07:41:49 PM PDT 24
Finished	Jul 16 07:43:25 PM PDT 24
Peak memory	327720 kb
Host	smart-078ea824-5e7e-44ec-a9d9-82668e147926
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767424050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.3767424050
Directory	/workspace/12.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3780391811
Short name	T842
Test name
Test status
Simulation time	6577569863 ps
CPU time	487.08 seconds
Started	Jul 16 07:41:54 PM PDT 24
Finished	Jul 16 07:50:12 PM PDT 24
Peak memory	202912 kb
Host	smart-7107ebca-ae8c-4b00-8136-b7128a595f34
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780391811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.3780391811
Directory	/workspace/12.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/12.sram_ctrl_ram_cfg.3969343282
Short name	T172
Test name
Test status
Simulation time	84920540 ps
CPU time	0.77 seconds
Started	Jul 16 07:41:55 PM PDT 24
Finished	Jul 16 07:42:06 PM PDT 24
Peak memory	202824 kb
Host	smart-600de95d-53d7-4460-baa9-081225afb43e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969343282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3969343282
Directory	/workspace/12.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/12.sram_ctrl_regwen.1908862651
Short name	T696
Test name
Test status
Simulation time	99351662622 ps
CPU time	829.81 seconds
Started	Jul 16 07:41:48 PM PDT 24
Finished	Jul 16 07:55:52 PM PDT 24
Peak memory	370656 kb
Host	smart-1e71c334-a2ba-4b95-b194-13163b5001b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908862651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1908862651
Directory	/workspace/12.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/12.sram_ctrl_smoke.2791265180
Short name	T421
Test name
Test status
Simulation time	6408495337 ps
CPU time	65.02 seconds
Started	Jul 16 07:41:54 PM PDT 24
Finished	Jul 16 07:43:10 PM PDT 24
Peak memory	340920 kb
Host	smart-f94fcecc-bd67-4402-a306-a36d869218ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791265180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2791265180
Directory	/workspace/12.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all.1702247624
Short name	T229
Test name
Test status
Simulation time	26874482733 ps
CPU time	205.83 seconds
Started	Jul 16 07:41:47 PM PDT 24
Finished	Jul 16 07:45:28 PM PDT 24
Peak memory	301080 kb
Host	smart-07dd6507-1c9f-483b-ba92-d15fe19b2ace
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702247624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.1702247624
Directory	/workspace/12.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2966192771
Short name	T68
Test name
Test status
Simulation time	7612209652 ps
CPU time	232.7 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 07:46:02 PM PDT 24
Peak memory	360512 kb
Host	smart-668050f4-dc65-4375-8205-ff768e942b6a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2966192771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2966192771
Directory	/workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1627136280
Short name	T290
Test name
Test status
Simulation time	2491782361 ps
CPU time	246.63 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 07:46:16 PM PDT 24
Peak memory	202816 kb
Host	smart-16e7e0bd-1a17-4aa2-aabf-64587b9e0b60
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627136280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.1627136280
Directory	/workspace/12.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1652768145
Short name	T730
Test name
Test status
Simulation time	152009099 ps
CPU time	139.43 seconds
Started	Jul 16 07:41:49 PM PDT 24
Finished	Jul 16 07:44:22 PM PDT 24
Peak memory	369472 kb
Host	smart-d480cb7d-0183-43df-983f-afe2b2e45410
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652768145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1652768145
Directory	/workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1598836731
Short name	T637
Test name
Test status
Simulation time	1681997146 ps
CPU time	303.37 seconds
Started	Jul 16 07:41:55 PM PDT 24
Finished	Jul 16 07:47:10 PM PDT 24
Peak memory	369228 kb
Host	smart-874769f0-b88f-4a58-be2b-4e3b0e315a87
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598836731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.1598836731
Directory	/workspace/13.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/13.sram_ctrl_alert_test.1744036110
Short name	T894
Test name
Test status
Simulation time	16251451 ps
CPU time	0.67 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 07:42:08 PM PDT 24
Peak memory	202640 kb
Host	smart-186bb81f-7e43-4177-8c4b-956c8041389d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744036110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1744036110
Directory	/workspace/13.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.sram_ctrl_bijection.2374973
Short name	T478
Test name
Test status
Simulation time	848792673 ps
CPU time	55.4 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:42:59 PM PDT 24
Peak memory	202844 kb
Host	smart-831d7355-3de0-4a44-9beb-218a89ec8acd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijecti on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.2374973
Directory	/workspace/13.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/13.sram_ctrl_executable.4151690692
Short name	T212
Test name
Test status
Simulation time	10394495609 ps
CPU time	489.47 seconds
Started	Jul 16 07:41:52 PM PDT 24
Finished	Jul 16 07:50:14 PM PDT 24
Peak memory	351240 kb
Host	smart-ee202298-e2c0-4512-9ad0-e6ad1b004931
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151690692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.4151690692
Directory	/workspace/13.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/13.sram_ctrl_lc_escalation.227785490
Short name	T585
Test name
Test status
Simulation time	2695413840 ps
CPU time	6.78 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:42:10 PM PDT 24
Peak memory	211168 kb
Host	smart-ca3e73b1-df0f-4b69-9307-746e27783cc3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227785490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_esc alation.227785490
Directory	/workspace/13.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/13.sram_ctrl_max_throughput.3013539792
Short name	T359
Test name
Test status
Simulation time	180702940 ps
CPU time	73.4 seconds
Started	Jul 16 07:41:50 PM PDT 24
Finished	Jul 16 07:43:17 PM PDT 24
Peak memory	318264 kb
Host	smart-679c2e21-942d-4098-9a00-04d093de297e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013539792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.3013539792
Directory	/workspace/13.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1023267244
Short name	T97
Test name
Test status
Simulation time	44775432 ps
CPU time	2.59 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:10 PM PDT 24
Peak memory	211104 kb
Host	smart-66435d86-1215-42a2-b28d-287bda8fabff
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023267244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.1023267244
Directory	/workspace/13.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_walk.3971817274
Short name	T167
Test name
Test status
Simulation time	348081594 ps
CPU time	9.58 seconds
Started	Jul 16 07:41:36 PM PDT 24
Finished	Jul 16 07:42:04 PM PDT 24
Peak memory	202844 kb
Host	smart-9c375c87-ba66-46de-bde5-7c153f2cd7ba
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971817274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.3971817274
Directory	/workspace/13.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/13.sram_ctrl_multiple_keys.3101250014
Short name	T306
Test name
Test status
Simulation time	21481191159 ps
CPU time	1435.91 seconds
Started	Jul 16 07:41:55 PM PDT 24
Finished	Jul 16 08:06:03 PM PDT 24
Peak memory	368552 kb
Host	smart-ede9c3c5-7490-4f48-8568-2d959497fbb4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101250014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.3101250014
Directory	/workspace/13.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access.1186958123
Short name	T901
Test name
Test status
Simulation time	1629400882 ps
CPU time	7.66 seconds
Started	Jul 16 07:41:52 PM PDT 24
Finished	Jul 16 07:42:11 PM PDT 24
Peak memory	202816 kb
Host	smart-be1a2f58-347b-43fc-a439-80fcded92364
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186958123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.1186958123
Directory	/workspace/13.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.758298224
Short name	T363
Test name
Test status
Simulation time	60263670504 ps
CPU time	424.92 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:49:14 PM PDT 24
Peak memory	202944 kb
Host	smart-ee63e8f2-e701-4204-86a7-54d54ece6de0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758298224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.sram_ctrl_partial_access_b2b.758298224
Directory	/workspace/13.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/13.sram_ctrl_ram_cfg.932013598
Short name	T177
Test name
Test status
Simulation time	30452332 ps
CPU time	0.77 seconds
Started	Jul 16 07:41:52 PM PDT 24
Finished	Jul 16 07:42:05 PM PDT 24
Peak memory	202880 kb
Host	smart-7ceab9c1-abf9-46f6-afba-4ac9f5afaef8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932013598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.932013598
Directory	/workspace/13.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/13.sram_ctrl_regwen.2527039606
Short name	T790
Test name
Test status
Simulation time	6355259151 ps
CPU time	200.71 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:45:28 PM PDT 24
Peak memory	340924 kb
Host	smart-b27e4482-4bd5-4756-8635-9923df41600e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527039606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2527039606
Directory	/workspace/13.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/13.sram_ctrl_smoke.23734231
Short name	T299
Test name
Test status
Simulation time	2749605713 ps
CPU time	176.66 seconds
Started	Jul 16 07:41:54 PM PDT 24
Finished	Jul 16 07:45:02 PM PDT 24
Peak memory	367456 kb
Host	smart-a225eae4-c528-4f72-995a-8de1696c4fbb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23734231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.23734231
Directory	/workspace/13.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.669407104
Short name	T810
Test name
Test status
Simulation time	699439355 ps
CPU time	23.82 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:33 PM PDT 24
Peak memory	214304 kb
Host	smart-ccf629ba-5a84-45d7-9987-ccb999b1b154
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=669407104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.669407104
Directory	/workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2981099485
Short name	T349
Test name
Test status
Simulation time	3166484038 ps
CPU time	310.62 seconds
Started	Jul 16 07:41:55 PM PDT 24
Finished	Jul 16 07:47:17 PM PDT 24
Peak memory	202944 kb
Host	smart-b8341c70-4b1a-47f4-a1f1-35de75497169
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981099485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.2981099485
Directory	/workspace/13.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3677355691
Short name	T327
Test name
Test status
Simulation time	305051390 ps
CPU time	115.27 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:43:59 PM PDT 24
Peak memory	371276 kb
Host	smart-b49210f0-8640-4e86-a573-bfb957313962
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677355691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3677355691
Directory	/workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.4214104775
Short name	T652
Test name
Test status
Simulation time	17498020821 ps
CPU time	776.45 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:55:04 PM PDT 24
Peak memory	368280 kb
Host	smart-a89895e7-7d4e-4b06-aa72-a221aa5c96ba
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214104775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.4214104775
Directory	/workspace/14.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/14.sram_ctrl_alert_test.2469148902
Short name	T527
Test name
Test status
Simulation time	60325709 ps
CPU time	0.64 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:08 PM PDT 24
Peak memory	202252 kb
Host	smart-273c7b55-b645-42a1-b8eb-b84a57cad1ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469148902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.2469148902
Directory	/workspace/14.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.sram_ctrl_bijection.1697421602
Short name	T710
Test name
Test status
Simulation time	7662150408 ps
CPU time	69.02 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 07:43:18 PM PDT 24
Peak memory	202936 kb
Host	smart-cce0a48c-fd08-4f21-8610-fed2776e0b05
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697421602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .1697421602
Directory	/workspace/14.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/14.sram_ctrl_executable.2102764765
Short name	T507
Test name
Test status
Simulation time	23033398874 ps
CPU time	1960.01 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 08:14:48 PM PDT 24
Peak memory	375696 kb
Host	smart-f1947f08-9940-4faf-a87e-e5583a07cf11
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102764765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.2102764765
Directory	/workspace/14.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/14.sram_ctrl_lc_escalation.2366255141
Short name	T125
Test name
Test status
Simulation time	2944367071 ps
CPU time	7.73 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 07:42:15 PM PDT 24
Peak memory	202896 kb
Host	smart-8b28489d-3830-4995-92b3-bd9eefbe8b93
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366255141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.2366255141
Directory	/workspace/14.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/14.sram_ctrl_max_throughput.3249492001
Short name	T728
Test name
Test status
Simulation time	437439035 ps
CPU time	131.34 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:44:19 PM PDT 24
Peak memory	371032 kb
Host	smart-7b50dd91-726e-4b09-8404-df70771385b9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249492001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.3249492001
Directory	/workspace/14.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3842160232
Short name	T712
Test name
Test status
Simulation time	633276915 ps
CPU time	6.12 seconds
Started	Jul 16 07:41:59 PM PDT 24
Finished	Jul 16 07:42:16 PM PDT 24
Peak memory	210936 kb
Host	smart-a9623bad-274d-40ae-ac2e-297b9ea634e0
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842160232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3842160232
Directory	/workspace/14.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_walk.855885581
Short name	T45
Test name
Test status
Simulation time	2592111555 ps
CPU time	11.86 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:19 PM PDT 24
Peak memory	211188 kb
Host	smart-a61a2564-9934-4b13-9725-e20daa028372
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855885581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _mem_walk.855885581
Directory	/workspace/14.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/14.sram_ctrl_multiple_keys.1863365421
Short name	T475
Test name
Test status
Simulation time	9733136606 ps
CPU time	971.1 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:58:19 PM PDT 24
Peak memory	374596 kb
Host	smart-4c7f33a7-b1a3-497d-bed2-125a16ca8a75
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863365421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.1863365421
Directory	/workspace/14.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access.4218235908
Short name	T839
Test name
Test status
Simulation time	342165507 ps
CPU time	30.97 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:38 PM PDT 24
Peak memory	284496 kb
Host	smart-717c4357-9dd7-48c3-93e6-81d2ee1baa69
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218235908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.4218235908
Directory	/workspace/14.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.853111381
Short name	T257
Test name
Test status
Simulation time	17559789341 ps
CPU time	395.62 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:48:43 PM PDT 24
Peak memory	202832 kb
Host	smart-eec29525-d661-4fff-97ba-570555a152e0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853111381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.sram_ctrl_partial_access_b2b.853111381
Directory	/workspace/14.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/14.sram_ctrl_ram_cfg.677521640
Short name	T366
Test name
Test status
Simulation time	31923010 ps
CPU time	0.75 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 07:42:07 PM PDT 24
Peak memory	202832 kb
Host	smart-f595d678-8dcd-48f5-aa93-d235ee3787f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677521640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.677521640
Directory	/workspace/14.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/14.sram_ctrl_regwen.3711869375
Short name	T916
Test name
Test status
Simulation time	6816330696 ps
CPU time	646.65 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:52:54 PM PDT 24
Peak memory	367100 kb
Host	smart-613120ae-d121-400d-a9c6-e8f3ea10668b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711869375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3711869375
Directory	/workspace/14.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/14.sram_ctrl_smoke.3197832571
Short name	T401
Test name
Test status
Simulation time	577104548 ps
CPU time	19.37 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:28 PM PDT 24
Peak memory	269172 kb
Host	smart-ba0bafbc-3937-4f31-ae2d-ec861609886f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197832571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3197832571
Directory	/workspace/14.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all.259715289
Short name	T202
Test name
Test status
Simulation time	189276210940 ps
CPU time	1289 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 08:03:36 PM PDT 24
Peak memory	373656 kb
Host	smart-b53910f1-021d-47ec-9abf-0dd5634e9b79
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259715289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_stress_all.259715289
Directory	/workspace/14.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1562723665
Short name	T67
Test name
Test status
Simulation time	537373197 ps
CPU time	41.3 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:49 PM PDT 24
Peak memory	290512 kb
Host	smart-ad6c73cd-3ef9-4653-b7c4-08f1ec8dd56f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1562723665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1562723665
Directory	/workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2771139804
Short name	T201
Test name
Test status
Simulation time	9032043783 ps
CPU time	168.16 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:44:57 PM PDT 24
Peak memory	202752 kb
Host	smart-c131bdb9-b360-42a9-bf1b-c0ddf7943689
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771139804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.2771139804
Directory	/workspace/14.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1140035879
Short name	T495
Test name
Test status
Simulation time	866073982 ps
CPU time	3.49 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:11 PM PDT 24
Peak memory	219132 kb
Host	smart-87f7e04a-85f9-43ca-a23d-fa0148766681
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140035879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1140035879
Directory	/workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2949844653
Short name	T529
Test name
Test status
Simulation time	13030534455 ps
CPU time	1274.54 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 08:03:22 PM PDT 24
Peak memory	372596 kb
Host	smart-3b5d92ff-b00f-4093-9692-962610f2ced0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949844653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.2949844653
Directory	/workspace/15.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/15.sram_ctrl_alert_test.2085243776
Short name	T646
Test name
Test status
Simulation time	40891821 ps
CPU time	0.65 seconds
Started	Jul 16 07:41:52 PM PDT 24
Finished	Jul 16 07:42:05 PM PDT 24
Peak memory	202616 kb
Host	smart-9c39050f-1233-426c-9adb-0d36420f3061
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085243776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.2085243776
Directory	/workspace/15.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.sram_ctrl_bijection.160850316
Short name	T156
Test name
Test status
Simulation time	475650930 ps
CPU time	31.2 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:39 PM PDT 24
Peak memory	202644 kb
Host	smart-6f473175-e243-472e-9681-35613c014ec0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160850316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection. 160850316
Directory	/workspace/15.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/15.sram_ctrl_executable.1869364907
Short name	T669
Test name
Test status
Simulation time	53698239321 ps
CPU time	1108.33 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 08:00:38 PM PDT 24
Peak memory	374328 kb
Host	smart-26f33fac-31ad-46f8-97fa-57bfe02d6a35
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869364907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.1869364907
Directory	/workspace/15.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/15.sram_ctrl_lc_escalation.2322336945
Short name	T522
Test name
Test status
Simulation time	1467507924 ps
CPU time	5.63 seconds
Started	Jul 16 07:41:52 PM PDT 24
Finished	Jul 16 07:42:10 PM PDT 24
Peak memory	202772 kb
Host	smart-0d9563ae-f5e6-4ae2-a9a5-9011c84fd2af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322336945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.2322336945
Directory	/workspace/15.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/15.sram_ctrl_max_throughput.3377915243
Short name	T656
Test name
Test status
Simulation time	136715470 ps
CPU time	115.2 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 07:44:05 PM PDT 24
Peak memory	369376 kb
Host	smart-87709e15-b3ad-47ae-9e29-199574328f70
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377915243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.3377915243
Directory	/workspace/15.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_partial_access.4082760214
Short name	T680
Test name
Test status
Simulation time	1381695951 ps
CPU time	5.49 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 07:42:12 PM PDT 24
Peak memory	211036 kb
Host	smart-863b0aa3-7cad-466a-80c7-7f898716dc3f
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082760214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.4082760214
Directory	/workspace/15.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_walk.2418541586
Short name	T307
Test name
Test status
Simulation time	404392439 ps
CPU time	5.74 seconds
Started	Jul 16 07:41:49 PM PDT 24
Finished	Jul 16 07:42:08 PM PDT 24
Peak memory	211004 kb
Host	smart-fbad5d62-227f-4180-bf80-47511a17fc4c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418541586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.2418541586
Directory	/workspace/15.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/15.sram_ctrl_multiple_keys.2701527920
Short name	T709
Test name
Test status
Simulation time	3208924031 ps
CPU time	874.61 seconds
Started	Jul 16 07:41:59 PM PDT 24
Finished	Jul 16 07:56:45 PM PDT 24
Peak memory	372544 kb
Host	smart-3265e1fa-34d2-4bd2-bd62-192671cd28ec
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701527920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.2701527920
Directory	/workspace/15.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access.1816519843
Short name	T519
Test name
Test status
Simulation time	306118417 ps
CPU time	15.63 seconds
Started	Jul 16 07:41:59 PM PDT 24
Finished	Jul 16 07:42:26 PM PDT 24
Peak memory	202748 kb
Host	smart-3c8b47ec-0e3c-4242-8d7b-2031dbe0ccc0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816519843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.1816519843
Directory	/workspace/15.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2855353641
Short name	T262
Test name
Test status
Simulation time	21239763304 ps
CPU time	385.63 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 07:48:35 PM PDT 24
Peak memory	202816 kb
Host	smart-885eb6bc-4197-4b21-9690-3963d0f0096b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855353641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.2855353641
Directory	/workspace/15.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/15.sram_ctrl_ram_cfg.27186488
Short name	T815
Test name
Test status
Simulation time	44807381 ps
CPU time	0.73 seconds
Started	Jul 16 07:41:51 PM PDT 24
Finished	Jul 16 07:42:04 PM PDT 24
Peak memory	202848 kb
Host	smart-75779a95-d2b9-4304-b577-36eb6f66bb45
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27186488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.27186488
Directory	/workspace/15.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/15.sram_ctrl_regwen.4109130152
Short name	T228
Test name
Test status
Simulation time	10005192553 ps
CPU time	556.49 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 07:51:26 PM PDT 24
Peak memory	373864 kb
Host	smart-4d884cc8-dd3e-4ab2-9f5c-df9e8d3e54a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109130152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.4109130152
Directory	/workspace/15.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/15.sram_ctrl_smoke.385792452
Short name	T687
Test name
Test status
Simulation time	2040965796 ps
CPU time	9.8 seconds
Started	Jul 16 07:41:58 PM PDT 24
Finished	Jul 16 07:42:19 PM PDT 24
Peak memory	202784 kb
Host	smart-7ea4ea58-8a59-4fb6-b7cd-fcab082dafa2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385792452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.385792452
Directory	/workspace/15.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all.4242322566
Short name	T459
Test name
Test status
Simulation time	122900146071 ps
CPU time	2017.83 seconds
Started	Jul 16 07:41:52 PM PDT 24
Finished	Jul 16 08:15:41 PM PDT 24
Peak memory	374688 kb
Host	smart-74c17eca-41cf-4bd2-9fcd-dc507e6e750f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242322566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.4242322566
Directory	/workspace/15.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2836249314
Short name	T302
Test name
Test status
Simulation time	9408654048 ps
CPU time	49.93 seconds
Started	Jul 16 07:41:50 PM PDT 24
Finished	Jul 16 07:42:53 PM PDT 24
Peak memory	273584 kb
Host	smart-223b6c69-9c97-40c0-aa2b-12c22c6f2e1e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2836249314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2836249314
Directory	/workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2389587382
Short name	T266
Test name
Test status
Simulation time	27841693329 ps
CPU time	369.86 seconds
Started	Jul 16 07:41:56 PM PDT 24
Finished	Jul 16 07:48:17 PM PDT 24
Peak memory	202932 kb
Host	smart-1ce02139-c42e-42ca-86c2-ed2385315f68
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389587382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.2389587382
Directory	/workspace/15.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2481790018
Short name	T38
Test name
Test status
Simulation time	108260865 ps
CPU time	36.57 seconds
Started	Jul 16 07:41:57 PM PDT 24
Finished	Jul 16 07:42:44 PM PDT 24
Peak memory	293508 kb
Host	smart-1a7f9c49-5086-4305-b155-8592c48f6b1d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481790018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2481790018
Directory	/workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1184124302
Short name	T683
Test name
Test status
Simulation time	4890630093 ps
CPU time	2186.61 seconds
Started	Jul 16 07:42:05 PM PDT 24
Finished	Jul 16 08:18:40 PM PDT 24
Peak memory	373344 kb
Host	smart-289d823d-3e08-499c-ba36-ff294e100917
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184124302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.1184124302
Directory	/workspace/16.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/16.sram_ctrl_alert_test.1455636282
Short name	T752
Test name
Test status
Simulation time	14682394 ps
CPU time	0.67 seconds
Started	Jul 16 07:42:09 PM PDT 24
Finished	Jul 16 07:42:17 PM PDT 24
Peak memory	202580 kb
Host	smart-a035a8b0-5ba3-4307-a338-d5278325ab27
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455636282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.1455636282
Directory	/workspace/16.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.sram_ctrl_bijection.2280555390
Short name	T630
Test name
Test status
Simulation time	2596819392 ps
CPU time	57.09 seconds
Started	Jul 16 07:42:12 PM PDT 24
Finished	Jul 16 07:43:17 PM PDT 24
Peak memory	202960 kb
Host	smart-de9bca60-1c6d-4f4f-ad47-189148200275
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280555390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .2280555390
Directory	/workspace/16.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/16.sram_ctrl_executable.2696024883
Short name	T304
Test name
Test status
Simulation time	58146959105 ps
CPU time	1303.57 seconds
Started	Jul 16 07:42:04 PM PDT 24
Finished	Jul 16 08:03:56 PM PDT 24
Peak memory	374732 kb
Host	smart-c1f7ba04-5c44-4f0f-ac20-8ab27f73a7a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696024883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.2696024883
Directory	/workspace/16.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/16.sram_ctrl_lc_escalation.2330357370
Short name	T774
Test name
Test status
Simulation time	520184361 ps
CPU time	5.39 seconds
Started	Jul 16 07:42:05 PM PDT 24
Finished	Jul 16 07:42:19 PM PDT 24
Peak memory	202788 kb
Host	smart-f2d71a31-af89-48a3-ab18-f30718e9a743
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330357370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2330357370
Directory	/workspace/16.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/16.sram_ctrl_max_throughput.1142609865
Short name	T334
Test name
Test status
Simulation time	52146665 ps
CPU time	3.71 seconds
Started	Jul 16 07:42:06 PM PDT 24
Finished	Jul 16 07:42:17 PM PDT 24
Peak memory	220524 kb
Host	smart-c535b6aa-cfc4-4229-b9db-41f0c39b1e0e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142609865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.1142609865
Directory	/workspace/16.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3713061501
Short name	T939
Test name
Test status
Simulation time	62903115 ps
CPU time	4.36 seconds
Started	Jul 16 07:42:07 PM PDT 24
Finished	Jul 16 07:42:19 PM PDT 24
Peak memory	210992 kb
Host	smart-bb3d2303-d708-4565-a62e-5adb0d94de6f
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713061501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.3713061501
Directory	/workspace/16.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_walk.937558333
Short name	T332
Test name
Test status
Simulation time	290607467 ps
CPU time	5.62 seconds
Started	Jul 16 07:42:04 PM PDT 24
Finished	Jul 16 07:42:19 PM PDT 24
Peak memory	202792 kb
Host	smart-c9e6aabe-4632-4efb-8817-8ac758f8ea87
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937558333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _mem_walk.937558333
Directory	/workspace/16.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access.3164328349
Short name	T157
Test name
Test status
Simulation time	218609079 ps
CPU time	80.61 seconds
Started	Jul 16 07:42:04 PM PDT 24
Finished	Jul 16 07:43:33 PM PDT 24
Peak memory	347940 kb
Host	smart-5b571c5a-31b7-428d-ac27-68677f457a4b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164328349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.3164328349
Directory	/workspace/16.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3613624307
Short name	T848
Test name
Test status
Simulation time	20129287246 ps
CPU time	388.97 seconds
Started	Jul 16 07:42:06 PM PDT 24
Finished	Jul 16 07:48:43 PM PDT 24
Peak memory	202964 kb
Host	smart-a733117d-b4b9-4d55-a736-fc5594b1446d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613624307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.3613624307
Directory	/workspace/16.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/16.sram_ctrl_ram_cfg.658693074
Short name	T28
Test name
Test status
Simulation time	44160648 ps
CPU time	0.76 seconds
Started	Jul 16 07:42:07 PM PDT 24
Finished	Jul 16 07:42:15 PM PDT 24
Peak memory	202668 kb
Host	smart-f54acc96-d30d-409c-a03d-ea12be0047d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658693074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.658693074
Directory	/workspace/16.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/16.sram_ctrl_regwen.548161269
Short name	T190
Test name
Test status
Simulation time	19232594069 ps
CPU time	1960.75 seconds
Started	Jul 16 07:42:06 PM PDT 24
Finished	Jul 16 08:14:55 PM PDT 24
Peak memory	375840 kb
Host	smart-3d10c7db-6107-4328-bcfc-7ea7fcf3a826
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548161269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.548161269
Directory	/workspace/16.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/16.sram_ctrl_smoke.1530188695
Short name	T31
Test name
Test status
Simulation time	109496648 ps
CPU time	2.26 seconds
Started	Jul 16 07:42:05 PM PDT 24
Finished	Jul 16 07:42:16 PM PDT 24
Peak memory	208624 kb
Host	smart-1c82a0af-b837-46e4-b5eb-3eae7daaae83
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530188695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1530188695
Directory	/workspace/16.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all.2977030271
Short name	T778
Test name
Test status
Simulation time	22796059010 ps
CPU time	2848.19 seconds
Started	Jul 16 07:42:05 PM PDT 24
Finished	Jul 16 08:29:41 PM PDT 24
Peak memory	375704 kb
Host	smart-1b80dc53-f588-4062-b200-662b01b75c4d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977030271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.2977030271
Directory	/workspace/16.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3885489990
Short name	T56
Test name
Test status
Simulation time	3061502640 ps
CPU time	24.07 seconds
Started	Jul 16 07:42:08 PM PDT 24
Finished	Jul 16 07:42:40 PM PDT 24
Peak memory	212264 kb
Host	smart-f131a6a6-6cf0-4ade-9355-c33778da427c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3885489990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3885489990
Directory	/workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.832237661
Short name	T465
Test name
Test status
Simulation time	2331164400 ps
CPU time	214.32 seconds
Started	Jul 16 07:42:06 PM PDT 24
Finished	Jul 16 07:45:48 PM PDT 24
Peak memory	202944 kb
Host	smart-d07b6faa-b85a-4b72-8dbb-eebf94340f89
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832237661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_stress_pipeline.832237661
Directory	/workspace/16.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1533163204
Short name	T64
Test name
Test status
Simulation time	311943096 ps
CPU time	118.87 seconds
Started	Jul 16 07:42:02 PM PDT 24
Finished	Jul 16 07:44:11 PM PDT 24
Peak memory	369376 kb
Host	smart-35683075-d411-46d8-9dcf-16806bf2ed8d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533163204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.1533163204
Directory	/workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3717990128
Short name	T490
Test name
Test status
Simulation time	7216143988 ps
CPU time	715.11 seconds
Started	Jul 16 07:42:05 PM PDT 24
Finished	Jul 16 07:54:09 PM PDT 24
Peak memory	373780 kb
Host	smart-e90c2940-afca-4c0c-8ce1-8461903ce027
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717990128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.3717990128
Directory	/workspace/17.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/17.sram_ctrl_alert_test.3714242068
Short name	T657
Test name
Test status
Simulation time	19422434 ps
CPU time	0.7 seconds
Started	Jul 16 07:42:12 PM PDT 24
Finished	Jul 16 07:42:21 PM PDT 24
Peak memory	202296 kb
Host	smart-d241a0cc-42c9-440e-8c63-537a98d1faed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714242068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.3714242068
Directory	/workspace/17.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.sram_ctrl_bijection.2570416612
Short name	T197
Test name
Test status
Simulation time	2531903304 ps
CPU time	54.95 seconds
Started	Jul 16 07:42:08 PM PDT 24
Finished	Jul 16 07:43:10 PM PDT 24
Peak memory	202940 kb
Host	smart-78952611-1b3c-4b4d-83c8-45ebfb2a9417
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570416612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .2570416612
Directory	/workspace/17.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/17.sram_ctrl_executable.473778853
Short name	T586
Test name
Test status
Simulation time	43253766700 ps
CPU time	728.41 seconds
Started	Jul 16 07:42:07 PM PDT 24
Finished	Jul 16 07:54:23 PM PDT 24
Peak memory	374316 kb
Host	smart-ab73e643-ab4e-4818-848a-6db4e1af85d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473778853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl e.473778853
Directory	/workspace/17.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/17.sram_ctrl_lc_escalation.2443841262
Short name	T864
Test name
Test status
Simulation time	8211616702 ps
CPU time	7.99 seconds
Started	Jul 16 07:42:08 PM PDT 24
Finished	Jul 16 07:42:24 PM PDT 24
Peak memory	211076 kb
Host	smart-da9277a8-1e6a-47b6-b47e-ab3f7661fe20
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443841262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.2443841262
Directory	/workspace/17.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/17.sram_ctrl_max_throughput.2589500275
Short name	T922
Test name
Test status
Simulation time	69520149 ps
CPU time	16.23 seconds
Started	Jul 16 07:42:08 PM PDT 24
Finished	Jul 16 07:42:32 PM PDT 24
Peak memory	258948 kb
Host	smart-758ab331-d729-449a-b24a-a07a71a8fa33
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589500275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.2589500275
Directory	/workspace/17.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2153512958
Short name	T626
Test name
Test status
Simulation time	99587782 ps
CPU time	3.34 seconds
Started	Jul 16 07:42:12 PM PDT 24
Finished	Jul 16 07:42:24 PM PDT 24
Peak memory	211100 kb
Host	smart-aeb26135-28a4-45ad-be32-2523d737b9aa
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153512958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.2153512958
Directory	/workspace/17.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_walk.627990146
Short name	T631
Test name
Test status
Simulation time	414748083 ps
CPU time	5.52 seconds
Started	Jul 16 07:42:09 PM PDT 24
Finished	Jul 16 07:42:21 PM PDT 24
Peak memory	202880 kb
Host	smart-6add9f56-9ad9-4501-9f82-ea75cad3eb10
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627990146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _mem_walk.627990146
Directory	/workspace/17.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/17.sram_ctrl_multiple_keys.1917915526
Short name	T436
Test name
Test status
Simulation time	451666608 ps
CPU time	209.76 seconds
Started	Jul 16 07:42:07 PM PDT 24
Finished	Jul 16 07:45:45 PM PDT 24
Peak memory	355032 kb
Host	smart-45cad4e5-062f-4a92-ade2-e40d8f230c32
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917915526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1917915526
Directory	/workspace/17.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access.3029102241
Short name	T219
Test name
Test status
Simulation time	39053338 ps
CPU time	1.29 seconds
Started	Jul 16 07:42:07 PM PDT 24
Finished	Jul 16 07:42:16 PM PDT 24
Peak memory	202632 kb
Host	smart-2e723fee-f51d-4f3b-a49c-83bbdf015a95
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029102241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.3029102241
Directory	/workspace/17.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.814771986
Short name	T526
Test name
Test status
Simulation time	6576705096 ps
CPU time	244.3 seconds
Started	Jul 16 07:42:06 PM PDT 24
Finished	Jul 16 07:46:18 PM PDT 24
Peak memory	202972 kb
Host	smart-0ebff53f-1ad0-423f-9f56-9c40caa1d9e3
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814771986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.sram_ctrl_partial_access_b2b.814771986
Directory	/workspace/17.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/17.sram_ctrl_ram_cfg.2152586632
Short name	T727
Test name
Test status
Simulation time	28701144 ps
CPU time	0.76 seconds
Started	Jul 16 07:42:09 PM PDT 24
Finished	Jul 16 07:42:17 PM PDT 24
Peak memory	202856 kb
Host	smart-728e8450-8b8b-4451-a10c-527123e327ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152586632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2152586632
Directory	/workspace/17.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/17.sram_ctrl_regwen.1624196384
Short name	T605
Test name
Test status
Simulation time	22853418590 ps
CPU time	603.07 seconds
Started	Jul 16 07:42:12 PM PDT 24
Finished	Jul 16 07:52:22 PM PDT 24
Peak memory	370832 kb
Host	smart-c8f3c519-1cb0-4b37-b14f-06821c963577
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624196384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1624196384
Directory	/workspace/17.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/17.sram_ctrl_smoke.817954652
Short name	T435
Test name
Test status
Simulation time	85791201 ps
CPU time	4.74 seconds
Started	Jul 16 07:42:07 PM PDT 24
Finished	Jul 16 07:42:19 PM PDT 24
Peak memory	225412 kb
Host	smart-890d3c11-6511-42e4-b3cb-2e6da8a22428
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817954652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.817954652
Directory	/workspace/17.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all.2011229509
Short name	T886
Test name
Test status
Simulation time	54730076641 ps
CPU time	4587.74 seconds
Started	Jul 16 07:42:07 PM PDT 24
Finished	Jul 16 08:58:43 PM PDT 24
Peak memory	379880 kb
Host	smart-de9ca2d9-72cc-4625-bfff-c150996df151
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011229509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.2011229509
Directory	/workspace/17.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.582420215
Short name	T122
Test name
Test status
Simulation time	1363557299 ps
CPU time	7.27 seconds
Started	Jul 16 07:42:08 PM PDT 24
Finished	Jul 16 07:42:22 PM PDT 24
Peak memory	211112 kb
Host	smart-0818a2b5-d497-46b3-a5c4-59f30b1a7a8b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=582420215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.582420215
Directory	/workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1315379470
Short name	T414
Test name
Test status
Simulation time	33162814618 ps
CPU time	317.59 seconds
Started	Jul 16 07:42:07 PM PDT 24
Finished	Jul 16 07:47:32 PM PDT 24
Peak memory	202784 kb
Host	smart-ec9b1a46-6ca9-413c-8b26-b812d2cc6edf
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315379470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.1315379470
Directory	/workspace/17.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2593661062
Short name	T929
Test name
Test status
Simulation time	421028053 ps
CPU time	63.83 seconds
Started	Jul 16 07:42:11 PM PDT 24
Finished	Jul 16 07:43:22 PM PDT 24
Peak memory	316116 kb
Host	smart-83095c8e-a46e-4d52-a6ee-69eff695e83a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593661062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.2593661062
Directory	/workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.3708695387
Short name	T760
Test name
Test status
Simulation time	4979326447 ps
CPU time	1073.36 seconds
Started	Jul 16 07:42:21 PM PDT 24
Finished	Jul 16 08:00:22 PM PDT 24
Peak memory	375608 kb
Host	smart-f9dde5b9-afb8-416c-b079-e3079fdf2a7e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708695387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.3708695387
Directory	/workspace/18.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/18.sram_ctrl_alert_test.1508495742
Short name	T509
Test name
Test status
Simulation time	14982351 ps
CPU time	0.68 seconds
Started	Jul 16 07:42:19 PM PDT 24
Finished	Jul 16 07:42:27 PM PDT 24
Peak memory	202580 kb
Host	smart-4f7aee77-c61a-4e8a-9810-052de8b0752c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508495742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.1508495742
Directory	/workspace/18.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.sram_ctrl_bijection.2198639835
Short name	T268
Test name
Test status
Simulation time	874296466 ps
CPU time	40.8 seconds
Started	Jul 16 07:42:08 PM PDT 24
Finished	Jul 16 07:42:56 PM PDT 24
Peak memory	202856 kb
Host	smart-30118983-7b67-42b3-ac35-3450fca894d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198639835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .2198639835
Directory	/workspace/18.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/18.sram_ctrl_executable.2000133124
Short name	T353
Test name
Test status
Simulation time	6116269090 ps
CPU time	367.74 seconds
Started	Jul 16 07:42:18 PM PDT 24
Finished	Jul 16 07:48:33 PM PDT 24
Peak memory	338940 kb
Host	smart-3b3637ac-aa4a-444c-85de-bfa8e48ac2ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000133124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.2000133124
Directory	/workspace/18.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/18.sram_ctrl_lc_escalation.934435280
Short name	T249
Test name
Test status
Simulation time	489159812 ps
CPU time	7.27 seconds
Started	Jul 16 07:42:20 PM PDT 24
Finished	Jul 16 07:42:34 PM PDT 24
Peak memory	202868 kb
Host	smart-4fd07489-1a84-4999-b972-ae091c466421
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934435280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc alation.934435280
Directory	/workspace/18.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/18.sram_ctrl_max_throughput.835754664
Short name	T143
Test name
Test status
Simulation time	265443152 ps
CPU time	98.78 seconds
Started	Jul 16 07:42:22 PM PDT 24
Finished	Jul 16 07:44:08 PM PDT 24
Peak memory	369420 kb
Host	smart-0a830c4d-0f69-408e-a7a4-a2acb025dac9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835754664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.sram_ctrl_max_throughput.835754664
Directory	/workspace/18.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2376528482
Short name	T899
Test name
Test status
Simulation time	1188531353 ps
CPU time	6.09 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:36 PM PDT 24
Peak memory	211080 kb
Host	smart-a0f2a7d5-6fa1-487c-b574-62feae2389ee
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376528482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.2376528482
Directory	/workspace/18.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_walk.3515054134
Short name	T548
Test name
Test status
Simulation time	521482632 ps
CPU time	8.71 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:39 PM PDT 24
Peak memory	211104 kb
Host	smart-581031fd-8a3c-42b8-8db9-006ad9a44558
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515054134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3515054134
Directory	/workspace/18.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/18.sram_ctrl_multiple_keys.220685800
Short name	T884
Test name
Test status
Simulation time	5020845484 ps
CPU time	1304.12 seconds
Started	Jul 16 07:42:09 PM PDT 24
Finished	Jul 16 08:04:00 PM PDT 24
Peak memory	371592 kb
Host	smart-87494bf1-af32-4627-87cd-31e294637f97
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220685800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip le_keys.220685800
Directory	/workspace/18.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access.1973156534
Short name	T783
Test name
Test status
Simulation time	4912076133 ps
CPU time	15.27 seconds
Started	Jul 16 07:42:20 PM PDT 24
Finished	Jul 16 07:42:43 PM PDT 24
Peak memory	247840 kb
Host	smart-9a661743-249e-4273-8bc4-017bdcf86d3a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973156534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.1973156534
Directory	/workspace/18.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2158944812
Short name	T609
Test name
Test status
Simulation time	2654978576 ps
CPU time	192.68 seconds
Started	Jul 16 07:42:18 PM PDT 24
Finished	Jul 16 07:45:37 PM PDT 24
Peak memory	202904 kb
Host	smart-8d48e4a0-b257-409b-b4d1-1fa3ed053e12
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158944812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.2158944812
Directory	/workspace/18.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/18.sram_ctrl_ram_cfg.4222230095
Short name	T323
Test name
Test status
Simulation time	49936494 ps
CPU time	0.78 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:31 PM PDT 24
Peak memory	202876 kb
Host	smart-3cf459f4-8eee-4065-818b-2270742f68ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222230095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.4222230095
Directory	/workspace/18.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/18.sram_ctrl_regwen.2709502206
Short name	T746
Test name
Test status
Simulation time	3450424436 ps
CPU time	291.87 seconds
Started	Jul 16 07:42:21 PM PDT 24
Finished	Jul 16 07:47:21 PM PDT 24
Peak memory	359368 kb
Host	smart-bf357d36-d3af-47a4-8fc9-6c9bad794db6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709502206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2709502206
Directory	/workspace/18.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/18.sram_ctrl_smoke.2021223453
Short name	T387
Test name
Test status
Simulation time	192383338 ps
CPU time	39.48 seconds
Started	Jul 16 07:42:09 PM PDT 24
Finished	Jul 16 07:42:55 PM PDT 24
Peak memory	297580 kb
Host	smart-3855d493-f0b9-4e20-93b0-a3879fe180c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021223453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2021223453
Directory	/workspace/18.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1355195158
Short name	T364
Test name
Test status
Simulation time	688580003 ps
CPU time	291.77 seconds
Started	Jul 16 07:42:19 PM PDT 24
Finished	Jul 16 07:47:18 PM PDT 24
Peak memory	376104 kb
Host	smart-d38bdedb-e127-43ce-8303-61e8b2f88412
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1355195158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1355195158
Directory	/workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3831006849
Short name	T198
Test name
Test status
Simulation time	2779253146 ps
CPU time	273.8 seconds
Started	Jul 16 07:42:07 PM PDT 24
Finished	Jul 16 07:46:48 PM PDT 24
Peak memory	202852 kb
Host	smart-00339568-f627-49f4-9153-f069791327b5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831006849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.3831006849
Directory	/workspace/18.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3718211895
Short name	T936
Test name
Test status
Simulation time	427082342 ps
CPU time	37.42 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:43:08 PM PDT 24
Peak memory	300768 kb
Host	smart-f778672b-a504-4f06-95a5-a3320875f11f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718211895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3718211895
Directory	/workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.312203790
Short name	T416
Test name
Test status
Simulation time	3668699263 ps
CPU time	233.98 seconds
Started	Jul 16 07:42:20 PM PDT 24
Finished	Jul 16 07:46:21 PM PDT 24
Peak memory	333932 kb
Host	smart-fec542fa-578f-4a3b-8500-035fbf99df6f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312203790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_access_during_key_req.312203790
Directory	/workspace/19.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/19.sram_ctrl_alert_test.1310212683
Short name	T703
Test name
Test status
Simulation time	22050928 ps
CPU time	0.65 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:32 PM PDT 24
Peak memory	202624 kb
Host	smart-734dc757-fadd-451a-9f70-2dd67fe12a1a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310212683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1310212683
Directory	/workspace/19.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.sram_ctrl_bijection.4081674680
Short name	T762
Test name
Test status
Simulation time	3207633654 ps
CPU time	52.75 seconds
Started	Jul 16 07:42:21 PM PDT 24
Finished	Jul 16 07:43:21 PM PDT 24
Peak memory	202900 kb
Host	smart-478697ed-0251-423d-9b6f-ecd009a33672
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081674680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .4081674680
Directory	/workspace/19.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/19.sram_ctrl_executable.22152864
Short name	T357
Test name
Test status
Simulation time	4575335007 ps
CPU time	459.47 seconds
Started	Jul 16 07:42:25 PM PDT 24
Finished	Jul 16 07:50:13 PM PDT 24
Peak memory	365100 kb
Host	smart-290c0436-2e18-4e45-a0f7-f3c445f5676f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22152864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable .22152864
Directory	/workspace/19.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/19.sram_ctrl_lc_escalation.561178735
Short name	T903
Test name
Test status
Simulation time	203420346 ps
CPU time	2.77 seconds
Started	Jul 16 07:42:24 PM PDT 24
Finished	Jul 16 07:42:35 PM PDT 24
Peak memory	202820 kb
Host	smart-3ada0a00-a390-4cad-b49f-2ed1b56c014f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561178735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esc alation.561178735
Directory	/workspace/19.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/19.sram_ctrl_max_throughput.2645332336
Short name	T869
Test name
Test status
Simulation time	455117393 ps
CPU time	130.6 seconds
Started	Jul 16 07:42:25 PM PDT 24
Finished	Jul 16 07:44:44 PM PDT 24
Peak memory	369040 kb
Host	smart-1f1a51c2-c0cb-41f2-96ca-294abf1bcb74
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645332336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.2645332336
Directory	/workspace/19.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.166172324
Short name	T260
Test name
Test status
Simulation time	2041518978 ps
CPU time	3.86 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:34 PM PDT 24
Peak memory	211084 kb
Host	smart-84ac062c-8c10-401c-8b11-939fd6e0e3ee
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166172324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sram_ctrl_mem_partial_access.166172324
Directory	/workspace/19.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_walk.3242890519
Short name	T771
Test name
Test status
Simulation time	824551911 ps
CPU time	6.36 seconds
Started	Jul 16 07:42:22 PM PDT 24
Finished	Jul 16 07:42:36 PM PDT 24
Peak memory	202836 kb
Host	smart-53d38149-61db-4036-9129-6340edbbe818
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242890519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.3242890519
Directory	/workspace/19.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/19.sram_ctrl_multiple_keys.2975088965
Short name	T913
Test name
Test status
Simulation time	21710408490 ps
CPU time	410.14 seconds
Started	Jul 16 07:42:22 PM PDT 24
Finished	Jul 16 07:49:20 PM PDT 24
Peak memory	373072 kb
Host	smart-4c59e037-1d53-4d5a-999c-bb0bf93eb178
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975088965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.2975088965
Directory	/workspace/19.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access.1968051868
Short name	T296
Test name
Test status
Simulation time	450888307 ps
CPU time	64.19 seconds
Started	Jul 16 07:42:18 PM PDT 24
Finished	Jul 16 07:43:29 PM PDT 24
Peak memory	308204 kb
Host	smart-84bd18ec-380a-48ea-b66b-0c28752418b9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968051868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.1968051868
Directory	/workspace/19.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_ram_cfg.1540019318
Short name	T766
Test name
Test status
Simulation time	58123074 ps
CPU time	0.76 seconds
Started	Jul 16 07:42:25 PM PDT 24
Finished	Jul 16 07:42:34 PM PDT 24
Peak memory	202736 kb
Host	smart-3f2581b8-b9ea-48af-a2ed-805f922e75a0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540019318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1540019318
Directory	/workspace/19.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/19.sram_ctrl_regwen.1292268183
Short name	T716
Test name
Test status
Simulation time	4298939847 ps
CPU time	402.57 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:49:14 PM PDT 24
Peak memory	373904 kb
Host	smart-3cf64983-99ab-40b2-889d-8dae1cfd6612
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292268183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1292268183
Directory	/workspace/19.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/19.sram_ctrl_smoke.3405744242
Short name	T775
Test name
Test status
Simulation time	31114254 ps
CPU time	0.83 seconds
Started	Jul 16 07:42:21 PM PDT 24
Finished	Jul 16 07:42:29 PM PDT 24
Peak memory	202592 kb
Host	smart-9d100489-6b06-4208-b43a-d4c5bb5f5eaf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405744242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3405744242
Directory	/workspace/19.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all.601897429
Short name	T444
Test name
Test status
Simulation time	55795422230 ps
CPU time	4951.47 seconds
Started	Jul 16 07:42:20 PM PDT 24
Finished	Jul 16 09:04:59 PM PDT 24
Peak memory	382452 kb
Host	smart-e217a07a-6e66-4e54-ad4b-703a7ec25571
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601897429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_stress_all.601897429
Directory	/workspace/19.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.413926085
Short name	T59
Test name
Test status
Simulation time	2317519307 ps
CPU time	526.41 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:51:17 PM PDT 24
Peak memory	386040 kb
Host	smart-b494bb85-5618-4d3e-9471-1fb4aa35a133
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=413926085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.413926085
Directory	/workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2755086560
Short name	T741
Test name
Test status
Simulation time	15815565461 ps
CPU time	219.01 seconds
Started	Jul 16 07:42:20 PM PDT 24
Finished	Jul 16 07:46:05 PM PDT 24
Peak memory	202912 kb
Host	smart-5ee0e82f-bb3c-4139-8eee-1b3c7139b333
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755086560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.2755086560
Directory	/workspace/19.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1875579494
Short name	T273
Test name
Test status
Simulation time	195324692 ps
CPU time	26.73 seconds
Started	Jul 16 07:42:20 PM PDT 24
Finished	Jul 16 07:42:54 PM PDT 24
Peak memory	287640 kb
Host	smart-ad5a1363-7dc9-4289-8cb6-e525cfa12eb5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875579494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1875579494
Directory	/workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2791427603
Short name	T517
Test name
Test status
Simulation time	7870419423 ps
CPU time	869.07 seconds
Started	Jul 16 07:41:14 PM PDT 24
Finished	Jul 16 07:56:02 PM PDT 24
Peak memory	374632 kb
Host	smart-c23cb618-f8e8-455f-8a2f-6a90670c49e3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791427603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.2791427603
Directory	/workspace/2.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/2.sram_ctrl_alert_test.3628874494
Short name	T708
Test name
Test status
Simulation time	17289950 ps
CPU time	0.69 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:41:20 PM PDT 24
Peak memory	202612 kb
Host	smart-eb614ef4-ff56-4134-8056-90e357d848a3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628874494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3628874494
Directory	/workspace/2.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.sram_ctrl_bijection.181836186
Short name	T665
Test name
Test status
Simulation time	2804968439 ps
CPU time	62.81 seconds
Started	Jul 16 07:41:13 PM PDT 24
Finished	Jul 16 07:42:35 PM PDT 24
Peak memory	202900 kb
Host	smart-42a6bca4-c415-40e2-8c6a-a9927082a053
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181836186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.181836186
Directory	/workspace/2.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/2.sram_ctrl_executable.4197104
Short name	T145
Test name
Test status
Simulation time	11384215450 ps
CPU time	735.38 seconds
Started	Jul 16 07:41:06 PM PDT 24
Finished	Jul 16 07:53:29 PM PDT 24
Peak memory	364476 kb
Host	smart-fb39c2fb-eaea-4406-adb4-7033b092b062
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.4197104
Directory	/workspace/2.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/2.sram_ctrl_lc_escalation.4216982306
Short name	T749
Test name
Test status
Simulation time	330957148 ps
CPU time	4.28 seconds
Started	Jul 16 07:41:15 PM PDT 24
Finished	Jul 16 07:41:40 PM PDT 24
Peak memory	202804 kb
Host	smart-62e91a87-6508-4085-ba8f-3516ff856ec6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216982306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.4216982306
Directory	/workspace/2.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/2.sram_ctrl_max_throughput.1509640626
Short name	T747
Test name
Test status
Simulation time	229317861 ps
CPU time	42.62 seconds
Started	Jul 16 07:41:14 PM PDT 24
Finished	Jul 16 07:42:16 PM PDT 24
Peak memory	321316 kb
Host	smart-dae65154-ce9c-4877-8a39-fec77c75d3b3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509640626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.1509640626
Directory	/workspace/2.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1981784395
Short name	T552
Test name
Test status
Simulation time	360150462 ps
CPU time	3.16 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:41:23 PM PDT 24
Peak memory	211000 kb
Host	smart-d56554c3-5fb4-4b36-ac86-eaf705f3391d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981784395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.1981784395
Directory	/workspace/2.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_walk.1119010056
Short name	T428
Test name
Test status
Simulation time	341037951 ps
CPU time	5.48 seconds
Started	Jul 16 07:41:07 PM PDT 24
Finished	Jul 16 07:41:22 PM PDT 24
Peak memory	211084 kb
Host	smart-8f0af590-b8d1-4bf5-b935-0df59a4401a1
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119010056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.1119010056
Directory	/workspace/2.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/2.sram_ctrl_multiple_keys.2939626761
Short name	T150
Test name
Test status
Simulation time	3297002651 ps
CPU time	1359.73 seconds
Started	Jul 16 07:41:11 PM PDT 24
Finished	Jul 16 08:04:06 PM PDT 24
Peak memory	373656 kb
Host	smart-1c09c21e-467c-492c-8266-18c4a54dc893
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939626761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.2939626761
Directory	/workspace/2.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access.3491499777
Short name	T852
Test name
Test status
Simulation time	163200151 ps
CPU time	67.26 seconds
Started	Jul 16 07:41:14 PM PDT 24
Finished	Jul 16 07:42:40 PM PDT 24
Peak memory	317140 kb
Host	smart-58acd9db-eeba-494f-8e15-ddee44e9f703
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491499777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.3491499777
Directory	/workspace/2.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2195019027
Short name	T239
Test name
Test status
Simulation time	57077007852 ps
CPU time	340.33 seconds
Started	Jul 16 07:41:08 PM PDT 24
Finished	Jul 16 07:47:00 PM PDT 24
Peak memory	202912 kb
Host	smart-25267e48-64d2-4f2e-bd25-31be47c82f5a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195019027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.2195019027
Directory	/workspace/2.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/2.sram_ctrl_ram_cfg.2548914419
Short name	T885
Test name
Test status
Simulation time	124098029 ps
CPU time	0.73 seconds
Started	Jul 16 07:41:09 PM PDT 24
Finished	Jul 16 07:41:22 PM PDT 24
Peak memory	202876 kb
Host	smart-9d5344c2-31ca-44c7-8d05-518aecaffa39
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548914419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2548914419
Directory	/workspace/2.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/2.sram_ctrl_regwen.2840222237
Short name	T166
Test name
Test status
Simulation time	26497313254 ps
CPU time	206.41 seconds
Started	Jul 16 07:41:09 PM PDT 24
Finished	Jul 16 07:44:48 PM PDT 24
Peak memory	374556 kb
Host	smart-1d324e65-d97b-43b3-a07e-e4daf14431c0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840222237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2840222237
Directory	/workspace/2.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/2.sram_ctrl_sec_cm.1521833469
Short name	T17
Test name
Test status
Simulation time	749492075 ps
CPU time	3.41 seconds
Started	Jul 16 07:41:07 PM PDT 24
Finished	Jul 16 07:41:20 PM PDT 24
Peak memory	222580 kb
Host	smart-616ad31b-f84e-4965-b372-d79050d52519
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521833469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1521833469
Directory	/workspace/2.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.sram_ctrl_smoke.106286913
Short name	T809
Test name
Test status
Simulation time	309932862 ps
CPU time	1.99 seconds
Started	Jul 16 07:41:13 PM PDT 24
Finished	Jul 16 07:41:32 PM PDT 24
Peak memory	202712 kb
Host	smart-7b06af2a-906c-48ef-a9b1-4cddf8ec560b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106286913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.106286913
Directory	/workspace/2.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all.2789873452
Short name	T532
Test name
Test status
Simulation time	45805022822 ps
CPU time	1316.68 seconds
Started	Jul 16 07:41:07 PM PDT 24
Finished	Jul 16 08:03:15 PM PDT 24
Peak memory	372436 kb
Host	smart-6656c89f-6cde-4356-bc67-6543ae1153d6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789873452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.2789873452
Directory	/workspace/2.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1794011255
Short name	T210
Test name
Test status
Simulation time	3052477541 ps
CPU time	284.4 seconds
Started	Jul 16 07:41:14 PM PDT 24
Finished	Jul 16 07:46:17 PM PDT 24
Peak memory	202888 kb
Host	smart-72800085-5492-4f12-8411-7ea6d96ed0bf
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794011255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.1794011255
Directory	/workspace/2.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1371393099
Short name	T477
Test name
Test status
Simulation time	78185278 ps
CPU time	1.35 seconds
Started	Jul 16 07:41:15 PM PDT 24
Finished	Jul 16 07:41:35 PM PDT 24
Peak memory	210984 kb
Host	smart-1d2aaba0-22df-4253-823d-d1d97d5bdf5c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371393099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1371393099
Directory	/workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.3932723312
Short name	T926
Test name
Test status
Simulation time	3007809860 ps
CPU time	595.77 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:52:27 PM PDT 24
Peak memory	342920 kb
Host	smart-e4f6400f-99ee-47d2-9e49-540983ce08e8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932723312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.3932723312
Directory	/workspace/20.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/20.sram_ctrl_alert_test.3471408695
Short name	T446
Test name
Test status
Simulation time	104724559 ps
CPU time	0.68 seconds
Started	Jul 16 07:42:27 PM PDT 24
Finished	Jul 16 07:42:37 PM PDT 24
Peak memory	202472 kb
Host	smart-3436a994-d016-48c8-bf3d-13916d097176
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471408695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.3471408695
Directory	/workspace/20.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.sram_ctrl_bijection.3547606555
Short name	T547
Test name
Test status
Simulation time	1391131889 ps
CPU time	22.91 seconds
Started	Jul 16 07:42:22 PM PDT 24
Finished	Jul 16 07:42:53 PM PDT 24
Peak memory	202800 kb
Host	smart-cc5319ee-d71f-489e-b899-50effed78094
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547606555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .3547606555
Directory	/workspace/20.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/20.sram_ctrl_executable.1400825428
Short name	T642
Test name
Test status
Simulation time	10097391228 ps
CPU time	164.53 seconds
Started	Jul 16 07:42:21 PM PDT 24
Finished	Jul 16 07:45:14 PM PDT 24
Peak memory	334716 kb
Host	smart-c8ed65c7-d5af-40be-9b46-43a0ec0d568a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400825428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.1400825428
Directory	/workspace/20.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/20.sram_ctrl_lc_escalation.2032535631
Short name	T660
Test name
Test status
Simulation time	799621744 ps
CPU time	3.12 seconds
Started	Jul 16 07:42:25 PM PDT 24
Finished	Jul 16 07:42:35 PM PDT 24
Peak memory	210968 kb
Host	smart-08fbef18-a24a-4708-bbbe-0891b8b282c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032535631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.2032535631
Directory	/workspace/20.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/20.sram_ctrl_max_throughput.2263651369
Short name	T595
Test name
Test status
Simulation time	734745891 ps
CPU time	30.35 seconds
Started	Jul 16 07:42:26 PM PDT 24
Finished	Jul 16 07:43:04 PM PDT 24
Peak memory	284348 kb
Host	smart-003c373e-66f0-4bba-98db-2e0d088df905
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263651369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.2263651369
Directory	/workspace/20.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2098755263
Short name	T181
Test name
Test status
Simulation time	63492798 ps
CPU time	4.57 seconds
Started	Jul 16 07:42:21 PM PDT 24
Finished	Jul 16 07:42:34 PM PDT 24
Peak memory	211124 kb
Host	smart-1c5e4e88-b857-45c7-af67-f2533d153e54
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098755263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2098755263
Directory	/workspace/20.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_walk.2511930814
Short name	T870
Test name
Test status
Simulation time	2381135803 ps
CPU time	7.01 seconds
Started	Jul 16 07:42:26 PM PDT 24
Finished	Jul 16 07:42:41 PM PDT 24
Peak memory	211176 kb
Host	smart-bbaac6d8-cbd9-47f1-91f7-3f656a209a93
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511930814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.2511930814
Directory	/workspace/20.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/20.sram_ctrl_multiple_keys.2716071191
Short name	T674
Test name
Test status
Simulation time	1001081659 ps
CPU time	509.47 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:51:00 PM PDT 24
Peak memory	364824 kb
Host	smart-9a671470-bc3b-461c-94e0-b948e23c4944
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716071191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.2716071191
Directory	/workspace/20.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access.1007143284
Short name	T537
Test name
Test status
Simulation time	303899994 ps
CPU time	20.2 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:51 PM PDT 24
Peak memory	269244 kb
Host	smart-8eecbe8f-963f-4b17-a405-9d22b5828e6d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007143284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.1007143284
Directory	/workspace/20.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2516761339
Short name	T493
Test name
Test status
Simulation time	16801156882 ps
CPU time	293.14 seconds
Started	Jul 16 07:42:25 PM PDT 24
Finished	Jul 16 07:47:27 PM PDT 24
Peak memory	202892 kb
Host	smart-249a57c6-40b3-40c5-9bfd-47904bc69664
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516761339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.2516761339
Directory	/workspace/20.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/20.sram_ctrl_ram_cfg.1559424640
Short name	T644
Test name
Test status
Simulation time	63253183 ps
CPU time	0.77 seconds
Started	Jul 16 07:42:25 PM PDT 24
Finished	Jul 16 07:42:34 PM PDT 24
Peak memory	202828 kb
Host	smart-ae8b36b9-7d12-4732-bb51-e36154c511f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559424640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1559424640
Directory	/workspace/20.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/20.sram_ctrl_regwen.2782199339
Short name	T21
Test name
Test status
Simulation time	45492397920 ps
CPU time	438.78 seconds
Started	Jul 16 07:42:27 PM PDT 24
Finished	Jul 16 07:49:54 PM PDT 24
Peak memory	366012 kb
Host	smart-ec01fdb2-913b-46ba-a5f1-b106acac2615
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782199339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2782199339
Directory	/workspace/20.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/20.sram_ctrl_smoke.2793352864
Short name	T863
Test name
Test status
Simulation time	598106910 ps
CPU time	11.78 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:43 PM PDT 24
Peak memory	202832 kb
Host	smart-0c872c65-2d39-49a6-a79d-985b3627fa3a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793352864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2793352864
Directory	/workspace/20.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all.3155459133
Short name	T602
Test name
Test status
Simulation time	327111470229 ps
CPU time	4185.28 seconds
Started	Jul 16 07:42:26 PM PDT 24
Finished	Jul 16 08:52:19 PM PDT 24
Peak memory	383900 kb
Host	smart-c25784b4-5ff5-4f52-a3ef-545de87f9850
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155459133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.3155459133
Directory	/workspace/20.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.305632210
Short name	T792
Test name
Test status
Simulation time	3736719441 ps
CPU time	483.65 seconds
Started	Jul 16 07:42:26 PM PDT 24
Finished	Jul 16 07:50:38 PM PDT 24
Peak memory	387100 kb
Host	smart-17f67cf3-8d8e-4459-9008-5a3e1b162f97
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=305632210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.305632210
Directory	/workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2138953226
Short name	T594
Test name
Test status
Simulation time	1621046020 ps
CPU time	155.55 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:45:07 PM PDT 24
Peak memory	202860 kb
Host	smart-38845689-d39c-4537-9e89-217b3194dda7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138953226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.2138953226
Directory	/workspace/20.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.4028087055
Short name	T726
Test name
Test status
Simulation time	189300913 ps
CPU time	48.32 seconds
Started	Jul 16 07:42:25 PM PDT 24
Finished	Jul 16 07:43:20 PM PDT 24
Peak memory	300688 kb
Host	smart-4ba7d4a7-5490-4abc-a9af-137998a2565f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028087055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.4028087055
Directory	/workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.3339270825
Short name	T481
Test name
Test status
Simulation time	7640815069 ps
CPU time	1468.12 seconds
Started	Jul 16 07:42:27 PM PDT 24
Finished	Jul 16 08:07:03 PM PDT 24
Peak memory	374728 kb
Host	smart-2cda306b-5962-4884-9fc7-f539f91b628c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339270825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.3339270825
Directory	/workspace/21.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/21.sram_ctrl_alert_test.1330963230
Short name	T559
Test name
Test status
Simulation time	62072066 ps
CPU time	0.69 seconds
Started	Jul 16 07:42:27 PM PDT 24
Finished	Jul 16 07:42:36 PM PDT 24
Peak memory	202640 kb
Host	smart-de323c87-5175-457d-a954-951a9c5000c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330963230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1330963230
Directory	/workspace/21.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.sram_ctrl_bijection.3094651531
Short name	T351
Test name
Test status
Simulation time	3259070219 ps
CPU time	37.96 seconds
Started	Jul 16 07:42:27 PM PDT 24
Finished	Jul 16 07:43:14 PM PDT 24
Peak memory	202780 kb
Host	smart-79e7cbdd-5efa-4b96-af68-35944b6dda99
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094651531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .3094651531
Directory	/workspace/21.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/21.sram_ctrl_executable.3820092640
Short name	T711
Test name
Test status
Simulation time	12333969621 ps
CPU time	558.49 seconds
Started	Jul 16 07:42:27 PM PDT 24
Finished	Jul 16 07:51:54 PM PDT 24
Peak memory	374548 kb
Host	smart-185ae78e-895c-4a32-9328-b01133a33dfb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820092640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.3820092640
Directory	/workspace/21.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/21.sram_ctrl_lc_escalation.3322333518
Short name	T285
Test name
Test status
Simulation time	511955404 ps
CPU time	5.54 seconds
Started	Jul 16 07:42:28 PM PDT 24
Finished	Jul 16 07:42:42 PM PDT 24
Peak memory	202644 kb
Host	smart-495cf52b-3ce2-4c62-814a-e84c720536ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322333518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.3322333518
Directory	/workspace/21.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/21.sram_ctrl_max_throughput.1085047647
Short name	T437
Test name
Test status
Simulation time	737225733 ps
CPU time	74.19 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:43:45 PM PDT 24
Peak memory	326844 kb
Host	smart-e821598f-12a5-4931-a1db-40fe05082743
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085047647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.1085047647
Directory	/workspace/21.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1532733241
Short name	T551
Test name
Test status
Simulation time	65889876 ps
CPU time	3.05 seconds
Started	Jul 16 07:42:28 PM PDT 24
Finished	Jul 16 07:42:40 PM PDT 24
Peak memory	210936 kb
Host	smart-5ebcecb4-e599-478e-86d5-dcb5163f5fe7
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532733241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.1532733241
Directory	/workspace/21.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_walk.783739207
Short name	T549
Test name
Test status
Simulation time	140377760 ps
CPU time	8.27 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:40 PM PDT 24
Peak memory	211088 kb
Host	smart-d2635388-bc3f-4eaf-8573-fdfdcb0bedd9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783739207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _mem_walk.783739207
Directory	/workspace/21.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/21.sram_ctrl_multiple_keys.3819220924
Short name	T252
Test name
Test status
Simulation time	5569136291 ps
CPU time	179.92 seconds
Started	Jul 16 07:42:26 PM PDT 24
Finished	Jul 16 07:45:34 PM PDT 24
Peak memory	364764 kb
Host	smart-863da495-4d69-4d90-9453-eaacaf1e0bc8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819220924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.3819220924
Directory	/workspace/21.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access.2825380855
Short name	T3
Test name
Test status
Simulation time	131365563 ps
CPU time	4.03 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:35 PM PDT 24
Peak memory	216684 kb
Host	smart-7472b88f-8149-46a8-b512-d42bc56bfa82
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825380855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.2825380855
Directory	/workspace/21.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1980591881
Short name	T40
Test name
Test status
Simulation time	2599023806 ps
CPU time	184.67 seconds
Started	Jul 16 07:42:28 PM PDT 24
Finished	Jul 16 07:45:42 PM PDT 24
Peak memory	202904 kb
Host	smart-9984e09c-0408-4dae-b1f4-faf506b729e6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980591881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.1980591881
Directory	/workspace/21.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/21.sram_ctrl_ram_cfg.2858250445
Short name	T699
Test name
Test status
Simulation time	66508573 ps
CPU time	0.74 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:32 PM PDT 24
Peak memory	202884 kb
Host	smart-9450d115-90a1-4c3d-a8ea-060b8ea2dac7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858250445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2858250445
Directory	/workspace/21.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/21.sram_ctrl_regwen.375321036
Short name	T879
Test name
Test status
Simulation time	13089190889 ps
CPU time	525.41 seconds
Started	Jul 16 07:42:27 PM PDT 24
Finished	Jul 16 07:51:21 PM PDT 24
Peak memory	364084 kb
Host	smart-d82d0889-acce-413c-911a-b94f1d63b4f5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375321036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.375321036
Directory	/workspace/21.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/21.sram_ctrl_smoke.3751904434
Short name	T474
Test name
Test status
Simulation time	349974053 ps
CPU time	20.9 seconds
Started	Jul 16 07:42:27 PM PDT 24
Finished	Jul 16 07:42:56 PM PDT 24
Peak memory	273680 kb
Host	smart-326beda3-454b-4ec7-ad0a-6cec1e5dbd76
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751904434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3751904434
Directory	/workspace/21.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all.3706868772
Short name	T340
Test name
Test status
Simulation time	5723990219 ps
CPU time	549.91 seconds
Started	Jul 16 07:42:31 PM PDT 24
Finished	Jul 16 07:51:49 PM PDT 24
Peak memory	367596 kb
Host	smart-7093d093-d563-458c-a01a-f4a5b08dcf6d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706868772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.3706868772
Directory	/workspace/21.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3497798045
Short name	T270
Test name
Test status
Simulation time	1741312860 ps
CPU time	263.12 seconds
Started	Jul 16 07:42:28 PM PDT 24
Finished	Jul 16 07:47:01 PM PDT 24
Peak memory	379536 kb
Host	smart-5a764fd0-95c0-4a86-9362-d36ccbd05000
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3497798045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3497798045
Directory	/workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1072551431
Short name	T578
Test name
Test status
Simulation time	11301305100 ps
CPU time	284.15 seconds
Started	Jul 16 07:42:26 PM PDT 24
Finished	Jul 16 07:47:18 PM PDT 24
Peak memory	202796 kb
Host	smart-772ef6de-0b9c-45c2-ba93-444d3c243a1e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072551431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.1072551431
Directory	/workspace/21.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.4194292067
Short name	T908
Test name
Test status
Simulation time	288638770 ps
CPU time	26.76 seconds
Started	Jul 16 07:42:27 PM PDT 24
Finished	Jul 16 07:43:02 PM PDT 24
Peak memory	278000 kb
Host	smart-c5fca889-4374-42cf-b44a-c233b3a19513
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194292067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.4194292067
Directory	/workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/22.sram_ctrl_alert_test.3229136679
Short name	T768
Test name
Test status
Simulation time	25037379 ps
CPU time	0.64 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:42:43 PM PDT 24
Peak memory	202628 kb
Host	smart-9c47d9c5-8813-4c61-b906-49f186669582
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229136679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.3229136679
Directory	/workspace/22.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.sram_ctrl_bijection.1590414634
Short name	T261
Test name
Test status
Simulation time	10914898094 ps
CPU time	84.68 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:43:55 PM PDT 24
Peak memory	202964 kb
Host	smart-d618005f-b56d-4324-b0b3-50831ba98794
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590414634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .1590414634
Directory	/workspace/22.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/22.sram_ctrl_executable.885674435
Short name	T317
Test name
Test status
Simulation time	20216942719 ps
CPU time	783.36 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:55:46 PM PDT 24
Peak memory	375588 kb
Host	smart-189da82c-9809-404c-ba2d-8e239bb7752a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885674435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl e.885674435
Directory	/workspace/22.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/22.sram_ctrl_lc_escalation.2567114369
Short name	T24
Test name
Test status
Simulation time	3684718302 ps
CPU time	9.6 seconds
Started	Jul 16 07:42:20 PM PDT 24
Finished	Jul 16 07:42:37 PM PDT 24
Peak memory	202928 kb
Host	smart-c90f4259-f57b-431f-95b0-c93b041d8d04
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567114369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.2567114369
Directory	/workspace/22.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/22.sram_ctrl_max_throughput.2592778509
Short name	T718
Test name
Test status
Simulation time	123997532 ps
CPU time	120.14 seconds
Started	Jul 16 07:42:22 PM PDT 24
Finished	Jul 16 07:44:30 PM PDT 24
Peak memory	351968 kb
Host	smart-d87d5a69-9b60-4976-b4e1-16274d4c8bb5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592778509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.2592778509
Directory	/workspace/22.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1278920532
Short name	T406
Test name
Test status
Simulation time	145138135 ps
CPU time	2.61 seconds
Started	Jul 16 07:42:38 PM PDT 24
Finished	Jul 16 07:42:47 PM PDT 24
Peak memory	211016 kb
Host	smart-8b968e9b-4dc2-4656-a307-6d1487fc8348
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278920532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.1278920532
Directory	/workspace/22.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_walk.2627431442
Short name	T780
Test name
Test status
Simulation time	1984332900 ps
CPU time	5.88 seconds
Started	Jul 16 07:42:42 PM PDT 24
Finished	Jul 16 07:42:52 PM PDT 24
Peak memory	211084 kb
Host	smart-724e6d95-2a8b-44db-8f93-d2cd0eab70f1
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627431442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.2627431442
Directory	/workspace/22.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/22.sram_ctrl_multiple_keys.3915086984
Short name	T298
Test name
Test status
Simulation time	4099894840 ps
CPU time	16.01 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:42:47 PM PDT 24
Peak memory	202956 kb
Host	smart-46e042e1-76f7-4985-96a9-28d9150d0ab9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915086984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.3915086984
Directory	/workspace/22.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access.491359816
Short name	T515
Test name
Test status
Simulation time	337424187 ps
CPU time	2.29 seconds
Started	Jul 16 07:42:22 PM PDT 24
Finished	Jul 16 07:42:32 PM PDT 24
Peak memory	202852 kb
Host	smart-899ef600-fee8-4e00-b1d7-e856195473a4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491359816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.s ram_ctrl_partial_access.491359816
Directory	/workspace/22.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3594939687
Short name	T740
Test name
Test status
Simulation time	11703225940 ps
CPU time	309.18 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:47:40 PM PDT 24
Peak memory	202920 kb
Host	smart-9ed3da0b-a6ea-4108-9f42-270883f86962
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594939687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.3594939687
Directory	/workspace/22.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/22.sram_ctrl_ram_cfg.2918537409
Short name	T335
Test name
Test status
Simulation time	89674743 ps
CPU time	0.76 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:42:44 PM PDT 24
Peak memory	202904 kb
Host	smart-f66cbaf4-46d7-4c2c-8035-e761750b8658
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918537409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2918537409
Directory	/workspace/22.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/22.sram_ctrl_regwen.3602357443
Short name	T572
Test name
Test status
Simulation time	94153789015 ps
CPU time	1958.92 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 08:15:37 PM PDT 24
Peak memory	371632 kb
Host	smart-0099e19b-eb4c-461e-bfab-32549b74ae33
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602357443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3602357443
Directory	/workspace/22.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/22.sram_ctrl_smoke.2030220701
Short name	T568
Test name
Test status
Simulation time	8498885092 ps
CPU time	64.15 seconds
Started	Jul 16 07:42:22 PM PDT 24
Finished	Jul 16 07:43:35 PM PDT 24
Peak memory	319340 kb
Host	smart-59afb2d1-1b6b-4c72-aec2-2d839c4ad1a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030220701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2030220701
Directory	/workspace/22.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3251987404
Short name	T632
Test name
Test status
Simulation time	1663823022 ps
CPU time	152.8 seconds
Started	Jul 16 07:42:23 PM PDT 24
Finished	Jul 16 07:45:03 PM PDT 24
Peak memory	202796 kb
Host	smart-31e8cb79-1812-4901-9f32-664d7bfa9e70
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251987404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.3251987404
Directory	/workspace/22.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.731590735
Short name	T318
Test name
Test status
Simulation time	151123711 ps
CPU time	144.54 seconds
Started	Jul 16 07:42:22 PM PDT 24
Finished	Jul 16 07:44:54 PM PDT 24
Peak memory	369436 kb
Host	smart-2c75cde0-3a3a-497e-a5c9-4597903b4d75
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731590735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.731590735
Directory	/workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.2676337741
Short name	T287
Test name
Test status
Simulation time	1131559376 ps
CPU time	78.4 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:44:16 PM PDT 24
Peak memory	322116 kb
Host	smart-fa180cfb-d5d2-41c8-8c8f-ff172361dba1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676337741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.2676337741
Directory	/workspace/23.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/23.sram_ctrl_alert_test.1776207125
Short name	T393
Test name
Test status
Simulation time	67673911 ps
CPU time	0.68 seconds
Started	Jul 16 07:42:35 PM PDT 24
Finished	Jul 16 07:42:42 PM PDT 24
Peak memory	202684 kb
Host	smart-db4d83ff-48cf-4c75-9ff3-938ba6fc8caa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776207125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.1776207125
Directory	/workspace/23.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.sram_ctrl_bijection.2335751783
Short name	T906
Test name
Test status
Simulation time	4476764344 ps
CPU time	65.09 seconds
Started	Jul 16 07:42:35 PM PDT 24
Finished	Jul 16 07:43:47 PM PDT 24
Peak memory	202936 kb
Host	smart-51b35674-21e1-4175-ad61-449fe95ba20e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335751783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .2335751783
Directory	/workspace/23.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/23.sram_ctrl_executable.2282118782
Short name	T825
Test name
Test status
Simulation time	15864747144 ps
CPU time	1076.62 seconds
Started	Jul 16 07:42:42 PM PDT 24
Finished	Jul 16 08:00:43 PM PDT 24
Peak memory	374768 kb
Host	smart-7df0dd91-1e2a-42c4-9bed-ba3643fab5af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282118782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.2282118782
Directory	/workspace/23.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/23.sram_ctrl_lc_escalation.2153630605
Short name	T882
Test name
Test status
Simulation time	1376020289 ps
CPU time	3.05 seconds
Started	Jul 16 07:42:28 PM PDT 24
Finished	Jul 16 07:42:40 PM PDT 24
Peak memory	202880 kb
Host	smart-6dd36865-75e2-4927-ab8e-c6fb30b32076
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153630605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.2153630605
Directory	/workspace/23.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/23.sram_ctrl_max_throughput.247477540
Short name	T531
Test name
Test status
Simulation time	41797772 ps
CPU time	2.38 seconds
Started	Jul 16 07:42:37 PM PDT 24
Finished	Jul 16 07:42:46 PM PDT 24
Peak memory	217172 kb
Host	smart-da361f3d-b5f4-493c-8c5f-ff3c29457c24
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247477540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.sram_ctrl_max_throughput.247477540
Directory	/workspace/23.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2970812387
Short name	T355
Test name
Test status
Simulation time	649596372 ps
CPU time	5.78 seconds
Started	Jul 16 07:42:38 PM PDT 24
Finished	Jul 16 07:42:50 PM PDT 24
Peak memory	210956 kb
Host	smart-9338f82e-726d-435d-a442-66f98cabec7b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970812387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.2970812387
Directory	/workspace/23.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_walk.2134266146
Short name	T601
Test name
Test status
Simulation time	1152521347 ps
CPU time	6.1 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:42:49 PM PDT 24
Peak memory	210984 kb
Host	smart-57817faa-bf3a-4ff9-9158-3e0b0b6634fe
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134266146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.2134266146
Directory	/workspace/23.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/23.sram_ctrl_multiple_keys.2426571801
Short name	T418
Test name
Test status
Simulation time	5971911208 ps
CPU time	1092.85 seconds
Started	Jul 16 07:42:37 PM PDT 24
Finished	Jul 16 08:00:57 PM PDT 24
Peak memory	362448 kb
Host	smart-90ab7e7d-22a6-48fc-a06c-a0fe9f210af8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426571801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.2426571801
Directory	/workspace/23.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access.1017629493
Short name	T269
Test name
Test status
Simulation time	621949561 ps
CPU time	145.36 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:45:09 PM PDT 24
Peak memory	356928 kb
Host	smart-a0df3425-0c23-49c1-9524-e25f3d69b058
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017629493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.1017629493
Directory	/workspace/23.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.118260356
Short name	T700
Test name
Test status
Simulation time	154981757086 ps
CPU time	514.29 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:51:18 PM PDT 24
Peak memory	202808 kb
Host	smart-9c82af45-0696-41ca-b921-1866b682626e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118260356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.sram_ctrl_partial_access_b2b.118260356
Directory	/workspace/23.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/23.sram_ctrl_ram_cfg.3349194962
Short name	T556
Test name
Test status
Simulation time	132306434 ps
CPU time	0.77 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:42:58 PM PDT 24
Peak memory	202828 kb
Host	smart-7e0c59c5-eed9-4404-9c56-4d9c89f176e0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349194962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3349194962
Directory	/workspace/23.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/23.sram_ctrl_regwen.2268909258
Short name	T668
Test name
Test status
Simulation time	15399242598 ps
CPU time	751.68 seconds
Started	Jul 16 07:42:37 PM PDT 24
Finished	Jul 16 07:55:15 PM PDT 24
Peak memory	375072 kb
Host	smart-1f72c3de-cada-45c7-b04e-fca1d0cd779e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268909258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2268909258
Directory	/workspace/23.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/23.sram_ctrl_smoke.1204963154
Short name	T203
Test name
Test status
Simulation time	593657495 ps
CPU time	22.15 seconds
Started	Jul 16 07:42:42 PM PDT 24
Finished	Jul 16 07:43:08 PM PDT 24
Peak memory	273988 kb
Host	smart-c3074b47-23c1-4cde-a378-5330579aceff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204963154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1204963154
Directory	/workspace/23.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all.2230041157
Short name	T736
Test name
Test status
Simulation time	14275273237 ps
CPU time	392.62 seconds
Started	Jul 16 07:42:38 PM PDT 24
Finished	Jul 16 07:49:17 PM PDT 24
Peak memory	332832 kb
Host	smart-d81b00b0-4d62-4927-a5b2-8e1720a3c514
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230041157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.2230041157
Directory	/workspace/23.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3883319973
Short name	T76
Test name
Test status
Simulation time	3469533868 ps
CPU time	29.32 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 07:43:24 PM PDT 24
Peak memory	211216 kb
Host	smart-d7084223-f1a2-443f-8323-754b528b48ae
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3883319973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3883319973
Directory	/workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3077998314
Short name	T206
Test name
Test status
Simulation time	2903221343 ps
CPU time	286.17 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:47:29 PM PDT 24
Peak memory	202864 kb
Host	smart-2fac3bf1-36f4-4573-8be9-bde56b0428e3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077998314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3077998314
Directory	/workspace/23.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3706941836
Short name	T795
Test name
Test status
Simulation time	79447334 ps
CPU time	4.59 seconds
Started	Jul 16 07:42:35 PM PDT 24
Finished	Jul 16 07:42:47 PM PDT 24
Peak memory	225320 kb
Host	smart-afa2dcb8-facf-424f-aefb-13283cb922c2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706941836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3706941836
Directory	/workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3017075447
Short name	T544
Test name
Test status
Simulation time	4058367013 ps
CPU time	795.7 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:55:59 PM PDT 24
Peak memory	373620 kb
Host	smart-16752c4b-a83d-4971-b9e9-458f9d78fe60
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017075447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.3017075447
Directory	/workspace/24.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/24.sram_ctrl_alert_test.3306369923
Short name	T415
Test name
Test status
Simulation time	12565689 ps
CPU time	0.65 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:42:43 PM PDT 24
Peak memory	202292 kb
Host	smart-eac6e0b5-6f7e-42da-bd6d-15027e75c705
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306369923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3306369923
Directory	/workspace/24.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.sram_ctrl_bijection.1302663941
Short name	T284
Test name
Test status
Simulation time	22478605236 ps
CPU time	47.95 seconds
Started	Jul 16 07:42:38 PM PDT 24
Finished	Jul 16 07:43:32 PM PDT 24
Peak memory	202944 kb
Host	smart-df0f6402-ebeb-4d90-93fa-16ad62d29b20
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302663941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .1302663941
Directory	/workspace/24.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/24.sram_ctrl_lc_escalation.2395354634
Short name	T80
Test name
Test status
Simulation time	791563928 ps
CPU time	7.31 seconds
Started	Jul 16 07:42:38 PM PDT 24
Finished	Jul 16 07:42:52 PM PDT 24
Peak memory	214328 kb
Host	smart-f9b473b0-ac1b-4334-b6dd-e179daf73ef7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395354634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.2395354634
Directory	/workspace/24.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/24.sram_ctrl_max_throughput.3131054429
Short name	T835
Test name
Test status
Simulation time	214322632 ps
CPU time	73.1 seconds
Started	Jul 16 07:42:37 PM PDT 24
Finished	Jul 16 07:43:57 PM PDT 24
Peak memory	318308 kb
Host	smart-4c27c1e8-5cd9-47f4-9533-3cd6335ccb86
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131054429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.3131054429
Directory	/workspace/24.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1859270232
Short name	T342
Test name
Test status
Simulation time	191132289 ps
CPU time	2.96 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:42:46 PM PDT 24
Peak memory	211076 kb
Host	smart-4c651d3d-3d96-42ec-9013-cc55007c35cb
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859270232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1859270232
Directory	/workspace/24.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_walk.2647504706
Short name	T534
Test name
Test status
Simulation time	142619911 ps
CPU time	4.54 seconds
Started	Jul 16 07:42:41 PM PDT 24
Finished	Jul 16 07:42:50 PM PDT 24
Peak memory	210984 kb
Host	smart-43d8dfe6-994d-488b-bbd4-3955f6e973eb
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647504706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2647504706
Directory	/workspace/24.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/24.sram_ctrl_multiple_keys.541484631
Short name	T417
Test name
Test status
Simulation time	4812105388 ps
CPU time	503.44 seconds
Started	Jul 16 07:42:35 PM PDT 24
Finished	Jul 16 07:51:06 PM PDT 24
Peak memory	374564 kb
Host	smart-876d3c73-ec54-42b7-9e9c-3e50323e1474
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541484631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multip le_keys.541484631
Directory	/workspace/24.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access.2779331824
Short name	T264
Test name
Test status
Simulation time	704892824 ps
CPU time	13.73 seconds
Started	Jul 16 07:42:52 PM PDT 24
Finished	Jul 16 07:43:11 PM PDT 24
Peak memory	202728 kb
Host	smart-9dc8fbc9-023e-4c2a-b768-db192b1c94cc
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779331824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.2779331824
Directory	/workspace/24.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3415915846
Short name	T236
Test name
Test status
Simulation time	15379504880 ps
CPU time	223.85 seconds
Started	Jul 16 07:42:41 PM PDT 24
Finished	Jul 16 07:46:30 PM PDT 24
Peak memory	202848 kb
Host	smart-50cd0f97-e930-43f6-97bf-756268a07c3b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415915846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.3415915846
Directory	/workspace/24.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/24.sram_ctrl_ram_cfg.3518367180
Short name	T217
Test name
Test status
Simulation time	72182200 ps
CPU time	0.76 seconds
Started	Jul 16 07:42:39 PM PDT 24
Finished	Jul 16 07:42:45 PM PDT 24
Peak memory	202868 kb
Host	smart-52efc08e-07b3-4304-a685-de7f847874c1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518367180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3518367180
Directory	/workspace/24.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/24.sram_ctrl_regwen.3639235193
Short name	T533
Test name
Test status
Simulation time	45973148548 ps
CPU time	830.16 seconds
Started	Jul 16 07:42:37 PM PDT 24
Finished	Jul 16 07:56:34 PM PDT 24
Peak memory	365540 kb
Host	smart-1ca0a584-af9e-4425-8767-2127b2157e0e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639235193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3639235193
Directory	/workspace/24.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/24.sram_ctrl_smoke.2357194454
Short name	T429
Test name
Test status
Simulation time	106894301 ps
CPU time	6.08 seconds
Started	Jul 16 07:42:41 PM PDT 24
Finished	Jul 16 07:42:52 PM PDT 24
Peak memory	202664 kb
Host	smart-ccd3dfc3-e337-49f6-bff7-d284735edd60
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357194454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2357194454
Directory	/workspace/24.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all.703262055
Short name	T805
Test name
Test status
Simulation time	18316306978 ps
CPU time	1109.53 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 08:01:27 PM PDT 24
Peak memory	374492 kb
Host	smart-dc1559c8-e9e9-462d-846a-0cd946c8f29f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703262055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_stress_all.703262055
Directory	/workspace/24.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2330735008
Short name	T921
Test name
Test status
Simulation time	601380083 ps
CPU time	16.12 seconds
Started	Jul 16 07:42:36 PM PDT 24
Finished	Jul 16 07:42:59 PM PDT 24
Peak memory	214816 kb
Host	smart-eaaa1e18-4cb5-426e-923e-d0fe310c0f7d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2330735008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2330735008
Directory	/workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.3036797915
Short name	T636
Test name
Test status
Simulation time	3724234472 ps
CPU time	178.56 seconds
Started	Jul 16 07:42:38 PM PDT 24
Finished	Jul 16 07:45:43 PM PDT 24
Peak memory	202820 kb
Host	smart-ef8ae18f-af25-4ee6-ba6e-b27458bd1e1a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036797915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.3036797915
Directory	/workspace/24.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2481957410
Short name	T232
Test name
Test status
Simulation time	47941887 ps
CPU time	2.86 seconds
Started	Jul 16 07:42:38 PM PDT 24
Finished	Jul 16 07:42:47 PM PDT 24
Peak memory	219108 kb
Host	smart-8086085d-c521-430a-b02d-2c82ef7ac0e3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481957410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.2481957410
Directory	/workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1435458243
Short name	T759
Test name
Test status
Simulation time	19340511781 ps
CPU time	1041.81 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 08:00:15 PM PDT 24
Peak memory	374740 kb
Host	smart-3c3f643f-c56a-40a5-840f-86a8a44170c6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435458243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.1435458243
Directory	/workspace/25.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/25.sram_ctrl_alert_test.1550023660
Short name	T196
Test name
Test status
Simulation time	87869052 ps
CPU time	0.65 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:42:58 PM PDT 24
Peak memory	202572 kb
Host	smart-235e2380-b4ee-4f07-87d2-96dc4daddc65
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550023660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1550023660
Directory	/workspace/25.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.sram_ctrl_bijection.1024999626
Short name	T702
Test name
Test status
Simulation time	1805573992 ps
CPU time	19.63 seconds
Started	Jul 16 07:42:41 PM PDT 24
Finished	Jul 16 07:43:05 PM PDT 24
Peak memory	202844 kb
Host	smart-9cce6438-5392-43af-8cfb-1d25c265a920
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024999626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .1024999626
Directory	/workspace/25.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/25.sram_ctrl_executable.4214230110
Short name	T603
Test name
Test status
Simulation time	5715841949 ps
CPU time	568.25 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 07:52:20 PM PDT 24
Peak memory	339848 kb
Host	smart-73f7321f-05c5-439a-91c5-06318da9ae8f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214230110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.4214230110
Directory	/workspace/25.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/25.sram_ctrl_lc_escalation.868091031
Short name	T717
Test name
Test status
Simulation time	2803401017 ps
CPU time	5.27 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 07:42:58 PM PDT 24
Peak memory	202888 kb
Host	smart-d3caa0e7-edea-4d0e-8995-90e3528985fb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868091031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esc alation.868091031
Directory	/workspace/25.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/25.sram_ctrl_max_throughput.804912282
Short name	T563
Test name
Test status
Simulation time	96244359 ps
CPU time	30.12 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:43:28 PM PDT 24
Peak memory	293128 kb
Host	smart-21f874ac-19ad-4f72-957c-a306bc921671
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804912282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.sram_ctrl_max_throughput.804912282
Directory	/workspace/25.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3740874113
Short name	T46
Test name
Test status
Simulation time	342277559 ps
CPU time	3.47 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 07:42:56 PM PDT 24
Peak memory	211084 kb
Host	smart-c0ca3299-8252-4273-acab-9bec2c9515cd
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740874113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.3740874113
Directory	/workspace/25.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_walk.508600794
Short name	T679
Test name
Test status
Simulation time	179033455 ps
CPU time	9.79 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 07:43:05 PM PDT 24
Peak memory	211056 kb
Host	smart-97247432-b28a-496c-9ba4-cf46f5944b93
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508600794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl _mem_walk.508600794
Directory	/workspace/25.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/25.sram_ctrl_multiple_keys.3740518969
Short name	T160
Test name
Test status
Simulation time	31105976542 ps
CPU time	652.05 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:53:50 PM PDT 24
Peak memory	357132 kb
Host	smart-14729a9a-2c33-428e-8be1-7f0805d5cc07
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740518969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.3740518969
Directory	/workspace/25.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access.3185568889
Short name	T61
Test name
Test status
Simulation time	2540018317 ps
CPU time	18.18 seconds
Started	Jul 16 07:42:54 PM PDT 24
Finished	Jul 16 07:43:17 PM PDT 24
Peak memory	202728 kb
Host	smart-e73dce8e-0440-4b00-be04-5e57ebdfdda8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185568889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3185568889
Directory	/workspace/25.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.681038762
Short name	T627
Test name
Test status
Simulation time	4175607054 ps
CPU time	295.62 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 07:47:49 PM PDT 24
Peak memory	202948 kb
Host	smart-1272487a-1878-4973-aa20-ecb65526e9ae
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681038762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.sram_ctrl_partial_access_b2b.681038762
Directory	/workspace/25.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/25.sram_ctrl_ram_cfg.4044139170
Short name	T440
Test name
Test status
Simulation time	76850114 ps
CPU time	0.76 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 07:42:53 PM PDT 24
Peak memory	202864 kb
Host	smart-c4fdecc0-694a-4097-8ef7-c6fa15bcd5a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044139170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.4044139170
Directory	/workspace/25.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/25.sram_ctrl_regwen.1564317289
Short name	T394
Test name
Test status
Simulation time	10897778159 ps
CPU time	979.31 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 07:59:13 PM PDT 24
Peak memory	368592 kb
Host	smart-e2571cd5-f98f-4571-af3c-3cbedb5ce195
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564317289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1564317289
Directory	/workspace/25.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/25.sram_ctrl_smoke.1843620927
Short name	T930
Test name
Test status
Simulation time	708424096 ps
CPU time	15.29 seconds
Started	Jul 16 07:42:43 PM PDT 24
Finished	Jul 16 07:43:01 PM PDT 24
Peak memory	202844 kb
Host	smart-81f863e4-9c68-4b4f-9ae5-b8ac9cdf4795
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843620927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1843620927
Directory	/workspace/25.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all.2433975813
Short name	T373
Test name
Test status
Simulation time	23810850923 ps
CPU time	1302.31 seconds
Started	Jul 16 07:42:48 PM PDT 24
Finished	Jul 16 08:04:33 PM PDT 24
Peak memory	373676 kb
Host	smart-53d9744d-c0ef-4dca-abe6-f57cb1d82d8f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433975813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.2433975813
Directory	/workspace/25.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2329636443
Short name	T124
Test name
Test status
Simulation time	743876688 ps
CPU time	20.43 seconds
Started	Jul 16 07:42:52 PM PDT 24
Finished	Jul 16 07:43:17 PM PDT 24
Peak memory	212308 kb
Host	smart-09112c88-54b3-4d3d-bb8e-69960f59ec14
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2329636443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2329636443
Directory	/workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.54028188
Short name	T226
Test name
Test status
Simulation time	9686162856 ps
CPU time	215.6 seconds
Started	Jul 16 07:42:54 PM PDT 24
Finished	Jul 16 07:46:34 PM PDT 24
Peak memory	202920 kb
Host	smart-91120f4a-d104-4b3c-9a87-ca23a4d8a31a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54028188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_stress_pipeline.54028188
Directory	/workspace/25.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3315701806
Short name	T305
Test name
Test status
Simulation time	213405312 ps
CPU time	56.92 seconds
Started	Jul 16 07:42:52 PM PDT 24
Finished	Jul 16 07:43:54 PM PDT 24
Peak memory	305048 kb
Host	smart-94431cd1-b46b-461b-894c-b757853b5997
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315701806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.3315701806
Directory	/workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.4039739266
Short name	T282
Test name
Test status
Simulation time	15987849611 ps
CPU time	1091.19 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 08:01:04 PM PDT 24
Peak memory	373988 kb
Host	smart-01791ccc-018a-4dac-8c97-fd95245692ee
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039739266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.4039739266
Directory	/workspace/26.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/26.sram_ctrl_alert_test.963420548
Short name	T398
Test name
Test status
Simulation time	26539115 ps
CPU time	0.63 seconds
Started	Jul 16 07:42:52 PM PDT 24
Finished	Jul 16 07:42:57 PM PDT 24
Peak memory	202628 kb
Host	smart-9102b72a-0bde-4413-b82b-e9df50756714
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963420548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.963420548
Directory	/workspace/26.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.sram_ctrl_bijection.673703776
Short name	T623
Test name
Test status
Simulation time	917159811 ps
CPU time	42.43 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:43:40 PM PDT 24
Peak memory	202836 kb
Host	smart-cf82225f-77d3-4a15-b8c5-12f528af5a15
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673703776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 673703776
Directory	/workspace/26.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/26.sram_ctrl_executable.822421286
Short name	T199
Test name
Test status
Simulation time	4089870331 ps
CPU time	1162.36 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 08:02:20 PM PDT 24
Peak memory	375464 kb
Host	smart-b534d114-9919-4932-b99d-0a46fc48e1a5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822421286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl e.822421286
Directory	/workspace/26.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/26.sram_ctrl_lc_escalation.1084778310
Short name	T611
Test name
Test status
Simulation time	310519193 ps
CPU time	2.26 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:43:00 PM PDT 24
Peak memory	202800 kb
Host	smart-a6a143b0-379e-448f-b47c-f121bbe942a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084778310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.1084778310
Directory	/workspace/26.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/26.sram_ctrl_max_throughput.1684103721
Short name	T888
Test name
Test status
Simulation time	516966590 ps
CPU time	121.71 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:44:59 PM PDT 24
Peak memory	370124 kb
Host	smart-8d6b3e93-a346-4fc7-9373-829b89bb5b1c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684103721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.1684103721
Directory	/workspace/26.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3290719948
Short name	T44
Test name
Test status
Simulation time	274136666 ps
CPU time	3.08 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 07:42:58 PM PDT 24
Peak memory	211056 kb
Host	smart-6829eb9c-190a-42f4-bac0-10beefd9ec18
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290719948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.3290719948
Directory	/workspace/26.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_walk.2118170198
Short name	T745
Test name
Test status
Simulation time	2605094355 ps
CPU time	11.2 seconds
Started	Jul 16 07:42:48 PM PDT 24
Finished	Jul 16 07:43:01 PM PDT 24
Peak memory	211136 kb
Host	smart-14f8740b-424a-4019-953f-febb69fed272
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118170198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.2118170198
Directory	/workspace/26.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/26.sram_ctrl_multiple_keys.259529510
Short name	T666
Test name
Test status
Simulation time	11654208080 ps
CPU time	1565.27 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 08:08:59 PM PDT 24
Peak memory	370780 kb
Host	smart-651b85db-6387-4a2d-9942-450efbefcacf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259529510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip le_keys.259529510
Directory	/workspace/26.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access.3779843087
Short name	T893
Test name
Test status
Simulation time	300243079 ps
CPU time	16.01 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 07:43:12 PM PDT 24
Peak memory	202792 kb
Host	smart-edb0fe77-ac25-4b0f-8abb-7239f3821a7e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779843087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.3779843087
Directory	/workspace/26.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.125217875
Short name	T593
Test name
Test status
Simulation time	93234199300 ps
CPU time	224.31 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:46:42 PM PDT 24
Peak memory	202320 kb
Host	smart-2c13cc4d-35ca-435b-bded-33c6a4bf98b8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125217875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.sram_ctrl_partial_access_b2b.125217875
Directory	/workspace/26.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/26.sram_ctrl_ram_cfg.3848180307
Short name	T331
Test name
Test status
Simulation time	86549952 ps
CPU time	0.72 seconds
Started	Jul 16 07:42:52 PM PDT 24
Finished	Jul 16 07:42:57 PM PDT 24
Peak memory	202868 kb
Host	smart-9d9681ca-084c-4828-ad23-75d647a3db19
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848180307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3848180307
Directory	/workspace/26.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/26.sram_ctrl_regwen.931351088
Short name	T443
Test name
Test status
Simulation time	59866189781 ps
CPU time	1023.89 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 07:59:59 PM PDT 24
Peak memory	359368 kb
Host	smart-58a4d271-5913-43da-826d-30f939704697
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931351088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.931351088
Directory	/workspace/26.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/26.sram_ctrl_smoke.1043226515
Short name	T814
Test name
Test status
Simulation time	1144308310 ps
CPU time	22.93 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 07:43:18 PM PDT 24
Peak memory	272516 kb
Host	smart-596727dc-33b1-43bf-9201-45e38bdd637e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043226515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1043226515
Directory	/workspace/26.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all.3168260323
Short name	T369
Test name
Test status
Simulation time	61185448676 ps
CPU time	1380.8 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 08:05:56 PM PDT 24
Peak memory	375784 kb
Host	smart-2c73f34e-e884-4a4b-9501-be092f64dfe3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168260323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.3168260323
Directory	/workspace/26.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.3748817969
Short name	T487
Test name
Test status
Simulation time	8592101400 ps
CPU time	206.29 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 07:46:19 PM PDT 24
Peak memory	202992 kb
Host	smart-1e1112bb-e6de-4b46-aced-16dcaeb2afa4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748817969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.3748817969
Directory	/workspace/26.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3170130746
Short name	T445
Test name
Test status
Simulation time	747137956 ps
CPU time	106.12 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 07:44:41 PM PDT 24
Peak memory	361216 kb
Host	smart-8c671038-d5a0-415b-a9e4-b7110b1de645
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170130746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3170130746
Directory	/workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3379593185
Short name	T482
Test name
Test status
Simulation time	574928452 ps
CPU time	65.81 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 07:44:02 PM PDT 24
Peak memory	281572 kb
Host	smart-788cfbb1-efaf-413b-9b2a-2ce8aa9f4fa5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379593185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.3379593185
Directory	/workspace/27.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/27.sram_ctrl_alert_test.1172816339
Short name	T693
Test name
Test status
Simulation time	12744956 ps
CPU time	0.66 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:43:07 PM PDT 24
Peak memory	202284 kb
Host	smart-e5c9c375-0908-4c99-bde9-7ecc578d4f17
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172816339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1172816339
Directory	/workspace/27.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.sram_ctrl_bijection.2281149787
Short name	T562
Test name
Test status
Simulation time	1169744901 ps
CPU time	21.78 seconds
Started	Jul 16 07:42:49 PM PDT 24
Finished	Jul 16 07:43:13 PM PDT 24
Peak memory	202772 kb
Host	smart-be4c0379-5a21-4d63-80bd-21132ef97f30
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281149787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .2281149787
Directory	/workspace/27.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/27.sram_ctrl_executable.4217840729
Short name	T833
Test name
Test status
Simulation time	9214201107 ps
CPU time	1050.72 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 08:00:28 PM PDT 24
Peak memory	374740 kb
Host	smart-b02dee4d-2234-42e2-a081-739ff5f14b73
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217840729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.4217840729
Directory	/workspace/27.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/27.sram_ctrl_lc_escalation.314187373
Short name	T890
Test name
Test status
Simulation time	368257350 ps
CPU time	4.78 seconds
Started	Jul 16 07:42:52 PM PDT 24
Finished	Jul 16 07:43:01 PM PDT 24
Peak memory	202820 kb
Host	smart-6ca18ba5-6213-47fb-bd5d-a7280431fbd4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314187373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_esc alation.314187373
Directory	/workspace/27.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/27.sram_ctrl_max_throughput.885826382
Short name	T806
Test name
Test status
Simulation time	134361978 ps
CPU time	80.44 seconds
Started	Jul 16 07:42:53 PM PDT 24
Finished	Jul 16 07:44:18 PM PDT 24
Peak memory	364324 kb
Host	smart-06060ba6-c7c4-48e1-9e41-7017ebfa31d4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885826382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.sram_ctrl_max_throughput.885826382
Directory	/workspace/27.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3738565115
Short name	T662
Test name
Test status
Simulation time	511258886 ps
CPU time	2.86 seconds
Started	Jul 16 07:43:02 PM PDT 24
Finished	Jul 16 07:43:06 PM PDT 24
Peak memory	211140 kb
Host	smart-ed4f53b4-204c-4ec5-bdf4-458d882ebca9
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738565115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.3738565115
Directory	/workspace/27.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_walk.2227664915
Short name	T927
Test name
Test status
Simulation time	787116859 ps
CPU time	6.4 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:43:13 PM PDT 24
Peak memory	202820 kb
Host	smart-ad656405-b6a9-4923-909e-7c82077ea672
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227664915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.2227664915
Directory	/workspace/27.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/27.sram_ctrl_multiple_keys.2412709703
Short name	T744
Test name
Test status
Simulation time	13291747001 ps
CPU time	981.61 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 07:59:14 PM PDT 24
Peak memory	374692 kb
Host	smart-93a6ade6-64bd-457e-9ab8-a7e28f42ef97
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412709703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.2412709703
Directory	/workspace/27.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access.2231341580
Short name	T608
Test name
Test status
Simulation time	421673010 ps
CPU time	4.69 seconds
Started	Jul 16 07:42:52 PM PDT 24
Finished	Jul 16 07:43:02 PM PDT 24
Peak memory	202868 kb
Host	smart-abc5afd4-da52-437d-9d33-63b39e749786
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231341580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.2231341580
Directory	/workspace/27.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.4132502387
Short name	T271
Test name
Test status
Simulation time	12442601821 ps
CPU time	314.32 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 07:48:08 PM PDT 24
Peak memory	202904 kb
Host	smart-a4870530-a75e-40ea-ac7c-c66c39fe661f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132502387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.4132502387
Directory	/workspace/27.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/27.sram_ctrl_ram_cfg.2545989218
Short name	T254
Test name
Test status
Simulation time	71085191 ps
CPU time	0.77 seconds
Started	Jul 16 07:42:54 PM PDT 24
Finished	Jul 16 07:43:00 PM PDT 24
Peak memory	202696 kb
Host	smart-bd290666-95d8-4615-9571-bd424c26728b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545989218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2545989218
Directory	/workspace/27.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/27.sram_ctrl_regwen.3321179563
Short name	T512
Test name
Test status
Simulation time	3537597868 ps
CPU time	1429.67 seconds
Started	Jul 16 07:42:50 PM PDT 24
Finished	Jul 16 08:06:43 PM PDT 24
Peak memory	370472 kb
Host	smart-1218554b-d348-4fa0-a53d-d8a93ffc88d1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321179563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3321179563
Directory	/workspace/27.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/27.sram_ctrl_smoke.1349631189
Short name	T648
Test name
Test status
Simulation time	393640249 ps
CPU time	75.59 seconds
Started	Jul 16 07:42:52 PM PDT 24
Finished	Jul 16 07:44:12 PM PDT 24
Peak memory	321428 kb
Host	smart-18b9829c-7bbf-4e04-9c62-d9b768e3b2a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349631189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1349631189
Directory	/workspace/27.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_all.2263464477
Short name	T330
Test name
Test status
Simulation time	119709540640 ps
CPU time	6169 seconds
Started	Jul 16 07:43:07 PM PDT 24
Finished	Jul 16 09:26:00 PM PDT 24
Peak memory	383916 kb
Host	smart-34849936-857f-4462-b919-982cba066d62
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263464477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.2263464477
Directory	/workspace/27.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.461958461
Short name	T542
Test name
Test status
Simulation time	2371748925 ps
CPU time	63.39 seconds
Started	Jul 16 07:43:07 PM PDT 24
Finished	Jul 16 07:44:14 PM PDT 24
Peak memory	312148 kb
Host	smart-66e1cb3b-ccf4-400b-b069-b6456df9e5ae
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=461958461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.461958461
Directory	/workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1245409106
Short name	T691
Test name
Test status
Simulation time	1784804760 ps
CPU time	167.41 seconds
Started	Jul 16 07:42:51 PM PDT 24
Finished	Jul 16 07:45:42 PM PDT 24
Peak memory	202796 kb
Host	smart-9503b264-af7f-4d5f-bc1c-57e22388efb4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245409106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.1245409106
Directory	/workspace/27.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1609429082
Short name	T919
Test name
Test status
Simulation time	456416234 ps
CPU time	65 seconds
Started	Jul 16 07:42:52 PM PDT 24
Finished	Jul 16 07:44:01 PM PDT 24
Peak memory	311384 kb
Host	smart-bf85f90f-6f3d-4b67-bb41-14f7343ea57f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609429082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1609429082
Directory	/workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.56281512
Short name	T34
Test name
Test status
Simulation time	2955988349 ps
CPU time	1002.86 seconds
Started	Jul 16 07:43:03 PM PDT 24
Finished	Jul 16 07:59:47 PM PDT 24
Peak memory	370532 kb
Host	smart-b6499f0b-4e61-48d7-b5b6-ff59f3c61244
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56281512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.sram_ctrl_access_during_key_req.56281512
Directory	/workspace/28.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/28.sram_ctrl_alert_test.561081194
Short name	T492
Test name
Test status
Simulation time	14625503 ps
CPU time	0.66 seconds
Started	Jul 16 07:43:08 PM PDT 24
Finished	Jul 16 07:43:12 PM PDT 24
Peak memory	202548 kb
Host	smart-5d2f91de-e1ee-4130-af04-a506d2a953aa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561081194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.561081194
Directory	/workspace/28.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.sram_ctrl_bijection.3140493783
Short name	T889
Test name
Test status
Simulation time	20298377048 ps
CPU time	71.6 seconds
Started	Jul 16 07:43:11 PM PDT 24
Finished	Jul 16 07:44:26 PM PDT 24
Peak memory	202884 kb
Host	smart-e1b87293-c54c-41e0-a95d-110bbc02cbb2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140493783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .3140493783
Directory	/workspace/28.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/28.sram_ctrl_executable.2472344610
Short name	T137
Test name
Test status
Simulation time	24035048198 ps
CPU time	402.07 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:49:48 PM PDT 24
Peak memory	374688 kb
Host	smart-aaad2307-68a9-4302-88ef-a28f002b5f1d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472344610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.2472344610
Directory	/workspace/28.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/28.sram_ctrl_lc_escalation.3785984439
Short name	T344
Test name
Test status
Simulation time	361362671 ps
CPU time	3.09 seconds
Started	Jul 16 07:43:09 PM PDT 24
Finished	Jul 16 07:43:16 PM PDT 24
Peak memory	202876 kb
Host	smart-9edb1525-6050-444c-93d8-8ce6f769ee83
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785984439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.3785984439
Directory	/workspace/28.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/28.sram_ctrl_max_throughput.2820690585
Short name	T382
Test name
Test status
Simulation time	109390317 ps
CPU time	59.77 seconds
Started	Jul 16 07:43:06 PM PDT 24
Finished	Jul 16 07:44:09 PM PDT 24
Peak memory	308724 kb
Host	smart-be1fa81c-488c-49d7-b704-a35b81109a8e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820690585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.2820690585
Directory	/workspace/28.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.4171284523
Short name	T255
Test name
Test status
Simulation time	429777742 ps
CPU time	3.07 seconds
Started	Jul 16 07:43:08 PM PDT 24
Finished	Jul 16 07:43:15 PM PDT 24
Peak memory	210992 kb
Host	smart-d5590014-3dd0-49db-8316-5dc82a2abfe0
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171284523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.4171284523
Directory	/workspace/28.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_walk.1374597417
Short name	T938
Test name
Test status
Simulation time	599845269 ps
CPU time	10.33 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:43:17 PM PDT 24
Peak memory	202844 kb
Host	smart-4acaa4b7-c375-420f-9592-9d21da4f577f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374597417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.1374597417
Directory	/workspace/28.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/28.sram_ctrl_multiple_keys.729409294
Short name	T516
Test name
Test status
Simulation time	5254753493 ps
CPU time	348.11 seconds
Started	Jul 16 07:43:06 PM PDT 24
Finished	Jul 16 07:48:57 PM PDT 24
Peak memory	315356 kb
Host	smart-3227d568-ea14-497c-b1f6-994ec1380f99
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729409294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip le_keys.729409294
Directory	/workspace/28.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access.651339270
Short name	T639
Test name
Test status
Simulation time	518944895 ps
CPU time	2.58 seconds
Started	Jul 16 07:43:05 PM PDT 24
Finished	Jul 16 07:43:10 PM PDT 24
Peak memory	202848 kb
Host	smart-621c6f7c-542a-470d-85f3-1aec765d8aa9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651339270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s ram_ctrl_partial_access.651339270
Directory	/workspace/28.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.4277417221
Short name	T763
Test name
Test status
Simulation time	21851404198 ps
CPU time	430.28 seconds
Started	Jul 16 07:43:07 PM PDT 24
Finished	Jul 16 07:50:21 PM PDT 24
Peak memory	202908 kb
Host	smart-c2631577-bbd4-47d6-800d-a03c3c046ab7
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277417221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.4277417221
Directory	/workspace/28.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/28.sram_ctrl_ram_cfg.2897703332
Short name	T581
Test name
Test status
Simulation time	31082487 ps
CPU time	0.79 seconds
Started	Jul 16 07:43:03 PM PDT 24
Finished	Jul 16 07:43:05 PM PDT 24
Peak memory	202912 kb
Host	smart-d760d6df-faa7-4377-a79b-21bb731203cb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897703332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2897703332
Directory	/workspace/28.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/28.sram_ctrl_regwen.2042641597
Short name	T378
Test name
Test status
Simulation time	25498976259 ps
CPU time	706.55 seconds
Started	Jul 16 07:43:07 PM PDT 24
Finished	Jul 16 07:54:57 PM PDT 24
Peak memory	371764 kb
Host	smart-71b2e246-ff0c-4e51-aaca-8250ab126e56
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042641597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2042641597
Directory	/workspace/28.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/28.sram_ctrl_smoke.2819730130
Short name	T832
Test name
Test status
Simulation time	3934543531 ps
CPU time	17.87 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:43:24 PM PDT 24
Peak memory	202888 kb
Host	smart-ea6d315e-d37d-4d30-a8e5-cba1a2fe4905
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819730130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2819730130
Directory	/workspace/28.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2650098030
Short name	T753
Test name
Test status
Simulation time	9502572819 ps
CPU time	250.2 seconds
Started	Jul 16 07:43:06 PM PDT 24
Finished	Jul 16 07:47:20 PM PDT 24
Peak memory	359580 kb
Host	smart-bf25c83e-8fd3-4f56-895b-251668fa5076
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2650098030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2650098030
Directory	/workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2636331661
Short name	T625
Test name
Test status
Simulation time	15888000712 ps
CPU time	372.31 seconds
Started	Jul 16 07:43:08 PM PDT 24
Finished	Jul 16 07:49:24 PM PDT 24
Peak memory	202884 kb
Host	smart-6ae3551e-612a-43f2-898a-bbbd90717229
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636331661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.2636331661
Directory	/workspace/28.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1707839495
Short name	T788
Test name
Test status
Simulation time	335113140 ps
CPU time	21.42 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:43:26 PM PDT 24
Peak memory	269244 kb
Host	smart-6275fe22-318e-4d15-bbf6-d3e01c83d23c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707839495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1707839495
Directory	/workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.3896870025
Short name	T690
Test name
Test status
Simulation time	6155651894 ps
CPU time	373.22 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:49:20 PM PDT 24
Peak memory	366524 kb
Host	smart-7afed433-5e9f-4785-b0da-cf1baf50bd71
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896870025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.3896870025
Directory	/workspace/29.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/29.sram_ctrl_alert_test.2033656345
Short name	T263
Test name
Test status
Simulation time	12449924 ps
CPU time	0.64 seconds
Started	Jul 16 07:43:06 PM PDT 24
Finished	Jul 16 07:43:10 PM PDT 24
Peak memory	202700 kb
Host	smart-5057c995-39c3-4f71-98c6-4259e4e0edc3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033656345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.2033656345
Directory	/workspace/29.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.sram_ctrl_bijection.2572017304
Short name	T230
Test name
Test status
Simulation time	1959889670 ps
CPU time	31.36 seconds
Started	Jul 16 07:43:06 PM PDT 24
Finished	Jul 16 07:43:40 PM PDT 24
Peak memory	202788 kb
Host	smart-78f99232-5ddb-4160-8613-5cba878878a2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572017304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .2572017304
Directory	/workspace/29.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/29.sram_ctrl_executable.4253610464
Short name	T427
Test name
Test status
Simulation time	20762356267 ps
CPU time	1723.99 seconds
Started	Jul 16 07:43:08 PM PDT 24
Finished	Jul 16 08:11:55 PM PDT 24
Peak memory	374832 kb
Host	smart-042af4d5-6c89-4d03-83ce-01ed37a6949e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253610464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.4253610464
Directory	/workspace/29.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/29.sram_ctrl_lc_escalation.229522790
Short name	T152
Test name
Test status
Simulation time	2025380637 ps
CPU time	6.04 seconds
Started	Jul 16 07:43:05 PM PDT 24
Finished	Jul 16 07:43:14 PM PDT 24
Peak memory	202728 kb
Host	smart-266fa9cd-7521-4f3d-801e-13d92895c1b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229522790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esc alation.229522790
Directory	/workspace/29.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/29.sram_ctrl_max_throughput.1365509024
Short name	T267
Test name
Test status
Simulation time	127337278 ps
CPU time	1.75 seconds
Started	Jul 16 07:43:05 PM PDT 24
Finished	Jul 16 07:43:10 PM PDT 24
Peak memory	211032 kb
Host	smart-71c17f9a-491c-4d65-9a0e-0a99ed5446d2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365509024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.1365509024
Directory	/workspace/29.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_partial_access.3219111810
Short name	T758
Test name
Test status
Simulation time	184579156 ps
CPU time	3.31 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:43:10 PM PDT 24
Peak memory	211072 kb
Host	smart-a2e621cb-7ba0-43a3-b5b8-57365c139213
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219111810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.3219111810
Directory	/workspace/29.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_walk.1039720702
Short name	T865
Test name
Test status
Simulation time	2265181140 ps
CPU time	11.89 seconds
Started	Jul 16 07:43:06 PM PDT 24
Finished	Jul 16 07:43:22 PM PDT 24
Peak memory	210972 kb
Host	smart-5b6019a4-bc9f-4e9a-874a-951e751ce912
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039720702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.1039720702
Directory	/workspace/29.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/29.sram_ctrl_multiple_keys.516344372
Short name	T321
Test name
Test status
Simulation time	22742277035 ps
CPU time	696.07 seconds
Started	Jul 16 07:43:05 PM PDT 24
Finished	Jul 16 07:54:44 PM PDT 24
Peak memory	357236 kb
Host	smart-f6b86902-58e2-4d05-b15f-02459f5cd298
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516344372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip le_keys.516344372
Directory	/workspace/29.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access.3479690896
Short name	T933
Test name
Test status
Simulation time	293039894 ps
CPU time	22.65 seconds
Started	Jul 16 07:43:06 PM PDT 24
Finished	Jul 16 07:43:32 PM PDT 24
Peak memory	267700 kb
Host	smart-ca73ebe6-9da7-44f1-8491-fb1ee1f7d708
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479690896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.3479690896
Directory	/workspace/29.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.976726539
Short name	T189
Test name
Test status
Simulation time	68393240853 ps
CPU time	295.52 seconds
Started	Jul 16 07:43:08 PM PDT 24
Finished	Jul 16 07:48:08 PM PDT 24
Peak memory	202900 kb
Host	smart-04738867-1f6d-48c3-a6bf-fc816962d77d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976726539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.sram_ctrl_partial_access_b2b.976726539
Directory	/workspace/29.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/29.sram_ctrl_ram_cfg.2266117859
Short name	T732
Test name
Test status
Simulation time	118503727 ps
CPU time	0.76 seconds
Started	Jul 16 07:43:07 PM PDT 24
Finished	Jul 16 07:43:12 PM PDT 24
Peak memory	202888 kb
Host	smart-865bdf81-7332-4fea-9af0-b4385aedb36d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266117859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2266117859
Directory	/workspace/29.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/29.sram_ctrl_regwen.2338400188
Short name	T599
Test name
Test status
Simulation time	3849813499 ps
CPU time	211.05 seconds
Started	Jul 16 07:43:05 PM PDT 24
Finished	Jul 16 07:46:39 PM PDT 24
Peak memory	333900 kb
Host	smart-8df6f5e0-625f-4c6c-a3ea-f4df19e19205
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338400188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2338400188
Directory	/workspace/29.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/29.sram_ctrl_smoke.646603341
Short name	T472
Test name
Test status
Simulation time	134985842 ps
CPU time	93.53 seconds
Started	Jul 16 07:43:09 PM PDT 24
Finished	Jul 16 07:44:46 PM PDT 24
Peak memory	344872 kb
Host	smart-cc1ef95d-b2bd-4956-9eab-599b7a7f3088
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646603341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.646603341
Directory	/workspace/29.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all.1393798924
Short name	T377
Test name
Test status
Simulation time	61884781779 ps
CPU time	1049.87 seconds
Started	Jul 16 07:43:08 PM PDT 24
Finished	Jul 16 08:00:42 PM PDT 24
Peak memory	370920 kb
Host	smart-d018bb78-3cad-4019-b3da-f1bd8703834a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393798924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.1393798924
Directory	/workspace/29.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1094374621
Short name	T914
Test name
Test status
Simulation time	15620331811 ps
CPU time	747.58 seconds
Started	Jul 16 07:43:05 PM PDT 24
Finished	Jul 16 07:55:35 PM PDT 24
Peak memory	379924 kb
Host	smart-47e219f6-b7ea-4be8-a822-ba7336b1777d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1094374621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1094374621
Directory	/workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3989327455
Short name	T647
Test name
Test status
Simulation time	7475000782 ps
CPU time	174.76 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:46:00 PM PDT 24
Peak memory	202868 kb
Host	smart-e1629c63-78b1-4a9e-b569-9db97184bdbd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989327455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3989327455
Directory	/workspace/29.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2290415978
Short name	T767
Test name
Test status
Simulation time	135406111 ps
CPU time	102.71 seconds
Started	Jul 16 07:43:08 PM PDT 24
Finished	Jul 16 07:44:54 PM PDT 24
Peak memory	347168 kb
Host	smart-3ab3ea23-eb5e-4f21-80ca-8c1a2ab7ff50
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290415978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.2290415978
Directory	/workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.2965945588
Short name	T341
Test name
Test status
Simulation time	3078858095 ps
CPU time	365.42 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:47:55 PM PDT 24
Peak memory	355488 kb
Host	smart-3d220978-a005-41be-9073-0e4e449bdc45
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965945588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.2965945588
Directory	/workspace/3.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/3.sram_ctrl_alert_test.3413457942
Short name	T265
Test name
Test status
Simulation time	13907685 ps
CPU time	0.64 seconds
Started	Jul 16 07:41:20 PM PDT 24
Finished	Jul 16 07:41:42 PM PDT 24
Peak memory	202600 kb
Host	smart-cc45aa9b-c5a1-4972-92b3-67aa73fd2959
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413457942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.3413457942
Directory	/workspace/3.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.sram_ctrl_bijection.727721314
Short name	T242
Test name
Test status
Simulation time	3524979050 ps
CPU time	58.48 seconds
Started	Jul 16 07:41:06 PM PDT 24
Finished	Jul 16 07:42:12 PM PDT 24
Peak memory	203000 kb
Host	smart-f4c04f33-8462-4b68-9d6a-28a6cbd76004
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727721314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.727721314
Directory	/workspace/3.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/3.sram_ctrl_executable.2552167628
Short name	T361
Test name
Test status
Simulation time	14466420865 ps
CPU time	1184.04 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 08:01:26 PM PDT 24
Peak memory	374488 kb
Host	smart-8ca7bb2b-7fe1-4f5a-bf37-c0d633b8c8b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552167628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.2552167628
Directory	/workspace/3.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/3.sram_ctrl_lc_escalation.231435940
Short name	T484
Test name
Test status
Simulation time	271034194 ps
CPU time	3.33 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:41:49 PM PDT 24
Peak memory	202824 kb
Host	smart-9b3c877a-7c91-40ba-a167-1dea18fdc575
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231435940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esca lation.231435940
Directory	/workspace/3.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/3.sram_ctrl_max_throughput.2185261034
Short name	T874
Test name
Test status
Simulation time	180913931 ps
CPU time	33.36 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:42:18 PM PDT 24
Peak memory	292756 kb
Host	smart-e65b4cc6-de4f-4d4f-ad90-ae9aedec1fcb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185261034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.2185261034
Directory	/workspace/3.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.4021932311
Short name	T98
Test name
Test status
Simulation time	86308298 ps
CPU time	3.05 seconds
Started	Jul 16 07:41:19 PM PDT 24
Finished	Jul 16 07:41:43 PM PDT 24
Peak memory	211056 kb
Host	smart-af5f715c-1b83-414e-82df-344d7263d376
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021932311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.4021932311
Directory	/workspace/3.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_walk.3075565427
Short name	T673
Test name
Test status
Simulation time	95701679 ps
CPU time	5.17 seconds
Started	Jul 16 07:41:18 PM PDT 24
Finished	Jul 16 07:41:44 PM PDT 24
Peak memory	211104 kb
Host	smart-c1a53cf7-94e6-4c3a-b712-500e10b7e94e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075565427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.3075565427
Directory	/workspace/3.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/3.sram_ctrl_multiple_keys.3562261220
Short name	T689
Test name
Test status
Simulation time	10638955895 ps
CPU time	878.39 seconds
Started	Jul 16 07:41:09 PM PDT 24
Finished	Jul 16 07:56:01 PM PDT 24
Peak memory	368608 kb
Host	smart-57778d1d-809c-4b77-8bea-a9d86b351c13
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562261220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.3562261220
Directory	/workspace/3.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access.169508671
Short name	T370
Test name
Test status
Simulation time	616398011 ps
CPU time	10.55 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:55 PM PDT 24
Peak memory	202760 kb
Host	smart-b4002555-b2d6-4f72-8fed-f93b94145836
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169508671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr am_ctrl_partial_access.169508671
Directory	/workspace/3.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2544054003
Short name	T536
Test name
Test status
Simulation time	27209313977 ps
CPU time	216.49 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:45:21 PM PDT 24
Peak memory	202916 kb
Host	smart-b81d5ff9-f698-4df6-9c3a-16ccd02cc92d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544054003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.2544054003
Directory	/workspace/3.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/3.sram_ctrl_ram_cfg.2672556143
Short name	T288
Test name
Test status
Simulation time	29394740 ps
CPU time	0.74 seconds
Started	Jul 16 07:41:20 PM PDT 24
Finished	Jul 16 07:41:40 PM PDT 24
Peak memory	202892 kb
Host	smart-1eb2ef9d-01b7-4feb-8b44-aad004303246
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672556143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2672556143
Directory	/workspace/3.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/3.sram_ctrl_regwen.3305669889
Short name	T756
Test name
Test status
Simulation time	7643446109 ps
CPU time	891.91 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:56:37 PM PDT 24
Peak memory	369800 kb
Host	smart-833cfdab-ccf4-417c-9c06-b07534c69a5a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305669889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.3305669889
Directory	/workspace/3.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/3.sram_ctrl_sec_cm.379426988
Short name	T29
Test name
Test status
Simulation time	414254162 ps
CPU time	1.91 seconds
Started	Jul 16 07:41:27 PM PDT 24
Finished	Jul 16 07:41:50 PM PDT 24
Peak memory	221868 kb
Host	smart-a1bf7b3e-8723-4693-b37c-ca3dcdce09c4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379426988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_sec_cm.379426988
Directory	/workspace/3.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.sram_ctrl_smoke.4264848168
Short name	T456
Test name
Test status
Simulation time	246569946 ps
CPU time	1.67 seconds
Started	Jul 16 07:41:10 PM PDT 24
Finished	Jul 16 07:41:24 PM PDT 24
Peak memory	202872 kb
Host	smart-f33469e2-6e25-4406-b9a0-9157b621227f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264848168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.4264848168
Directory	/workspace/3.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all.3303105476
Short name	T248
Test name
Test status
Simulation time	160419959186 ps
CPU time	1809.81 seconds
Started	Jul 16 07:41:21 PM PDT 24
Finished	Jul 16 08:11:51 PM PDT 24
Peak memory	375660 kb
Host	smart-9e022179-3046-40af-97ce-80b50c02eb19
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303105476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.3303105476
Directory	/workspace/3.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.982239300
Short name	T576
Test name
Test status
Simulation time	1551106586 ps
CPU time	9.22 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:41:59 PM PDT 24
Peak memory	218560 kb
Host	smart-482138cd-4910-4606-adcd-41894c11d2f3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=982239300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.982239300
Directory	/workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1459219389
Short name	T464
Test name
Test status
Simulation time	1230220246 ps
CPU time	116.35 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:43:42 PM PDT 24
Peak memory	202432 kb
Host	smart-76c832fe-4514-4540-bc07-f9fecd86db6e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459219389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.1459219389
Directory	/workspace/3.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2829221266
Short name	T881
Test name
Test status
Simulation time	605640254 ps
CPU time	102.73 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:43:29 PM PDT 24
Peak memory	353256 kb
Host	smart-d28717f6-0226-4879-ad8e-2472150c154f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829221266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2829221266
Directory	/workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2096805258
Short name	T571
Test name
Test status
Simulation time	29945270670 ps
CPU time	976.2 seconds
Started	Jul 16 07:43:10 PM PDT 24
Finished	Jul 16 07:59:30 PM PDT 24
Peak memory	375708 kb
Host	smart-f9fce00d-8214-4d22-bbdd-83b3710a4f69
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096805258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.2096805258
Directory	/workspace/30.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/30.sram_ctrl_bijection.3703539047
Short name	T294
Test name
Test status
Simulation time	3279334958 ps
CPU time	72.98 seconds
Started	Jul 16 07:43:08 PM PDT 24
Finished	Jul 16 07:44:25 PM PDT 24
Peak memory	202944 kb
Host	smart-264c5836-6f88-496c-8557-a44769775233
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703539047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .3703539047
Directory	/workspace/30.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/30.sram_ctrl_executable.4189704114
Short name	T713
Test name
Test status
Simulation time	8224746921 ps
CPU time	1236.32 seconds
Started	Jul 16 07:43:17 PM PDT 24
Finished	Jul 16 08:03:55 PM PDT 24
Peak memory	373144 kb
Host	smart-55dea291-93f9-4dbd-9ebb-85228bc5bceb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189704114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.4189704114
Directory	/workspace/30.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/30.sram_ctrl_lc_escalation.2836494152
Short name	T871
Test name
Test status
Simulation time	566339293 ps
CPU time	7.31 seconds
Started	Jul 16 07:43:08 PM PDT 24
Finished	Jul 16 07:43:19 PM PDT 24
Peak memory	202780 kb
Host	smart-fbc1270d-c421-44d8-9d85-a85dfa38849f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836494152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.2836494152
Directory	/workspace/30.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/30.sram_ctrl_max_throughput.3907850419
Short name	T505
Test name
Test status
Simulation time	239355468 ps
CPU time	79.38 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:44:26 PM PDT 24
Peak memory	350948 kb
Host	smart-a5e6dc95-4c97-4393-8a36-9b0573da0c80
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907850419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.3907850419
Directory	/workspace/30.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2279486740
Short name	T596
Test name
Test status
Simulation time	302927184 ps
CPU time	4.54 seconds
Started	Jul 16 07:43:18 PM PDT 24
Finished	Jul 16 07:43:25 PM PDT 24
Peak memory	211104 kb
Host	smart-23f7348a-6694-4237-a9f2-326d8507129a
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279486740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.2279486740
Directory	/workspace/30.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_walk.1493177984
Short name	T463
Test name
Test status
Simulation time	1704547761 ps
CPU time	10.71 seconds
Started	Jul 16 07:43:20 PM PDT 24
Finished	Jul 16 07:43:33 PM PDT 24
Peak memory	211052 kb
Host	smart-19494d2b-23da-41bc-bb02-a686ef880c42
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493177984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.1493177984
Directory	/workspace/30.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/30.sram_ctrl_multiple_keys.1308613107
Short name	T622
Test name
Test status
Simulation time	3754326881 ps
CPU time	980.58 seconds
Started	Jul 16 07:43:05 PM PDT 24
Finished	Jul 16 07:59:28 PM PDT 24
Peak memory	374408 kb
Host	smart-29f3a105-e4df-4ce4-85c7-276fecbc0a8e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308613107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1308613107
Directory	/workspace/30.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access.4152814898
Short name	T169
Test name
Test status
Simulation time	647815290 ps
CPU time	137.6 seconds
Started	Jul 16 07:43:07 PM PDT 24
Finished	Jul 16 07:45:29 PM PDT 24
Peak memory	356112 kb
Host	smart-9fa29863-1e51-4a4c-b987-0b16b74d29b9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152814898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.4152814898
Directory	/workspace/30.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1425393765
Short name	T931
Test name
Test status
Simulation time	15212855895 ps
CPU time	354.35 seconds
Started	Jul 16 07:43:05 PM PDT 24
Finished	Jul 16 07:49:02 PM PDT 24
Peak memory	202904 kb
Host	smart-48b9f4a5-406a-47a8-88ca-b10dea41d190
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425393765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.1425393765
Directory	/workspace/30.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/30.sram_ctrl_ram_cfg.1205840144
Short name	T520
Test name
Test status
Simulation time	50050800 ps
CPU time	0.75 seconds
Started	Jul 16 07:43:19 PM PDT 24
Finished	Jul 16 07:43:22 PM PDT 24
Peak memory	202884 kb
Host	smart-9c7c49ff-7467-4706-8e41-58b60920b9db
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205840144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1205840144
Directory	/workspace/30.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/30.sram_ctrl_regwen.2561199092
Short name	T451
Test name
Test status
Simulation time	1621879712 ps
CPU time	341.06 seconds
Started	Jul 16 07:43:20 PM PDT 24
Finished	Jul 16 07:49:04 PM PDT 24
Peak memory	366612 kb
Host	smart-f3d2d876-7907-45f0-bac0-4ba268612005
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561199092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2561199092
Directory	/workspace/30.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/30.sram_ctrl_smoke.657737810
Short name	T162
Test name
Test status
Simulation time	127940550 ps
CPU time	91.01 seconds
Started	Jul 16 07:43:04 PM PDT 24
Finished	Jul 16 07:44:38 PM PDT 24
Peak memory	337284 kb
Host	smart-6128b511-5fd0-4f19-8f7c-dbcb2f0d9ac3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657737810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.657737810
Directory	/workspace/30.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all.4024087273
Short name	T670
Test name
Test status
Simulation time	10648969604 ps
CPU time	1853.76 seconds
Started	Jul 16 07:43:19 PM PDT 24
Finished	Jul 16 08:14:15 PM PDT 24
Peak memory	376080 kb
Host	smart-446a79ef-ad09-4a50-85df-6e8d42be9242
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024087273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.4024087273
Directory	/workspace/30.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1150171530
Short name	T734
Test name
Test status
Simulation time	5543132168 ps
CPU time	38.55 seconds
Started	Jul 16 07:43:20 PM PDT 24
Finished	Jul 16 07:44:02 PM PDT 24
Peak memory	219432 kb
Host	smart-a752ae42-f67c-45cd-b75e-6f8796cf80c8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1150171530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1150171530
Directory	/workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1898176444
Short name	T2
Test name
Test status
Simulation time	25612855062 ps
CPU time	183.25 seconds
Started	Jul 16 07:43:07 PM PDT 24
Finished	Jul 16 07:46:14 PM PDT 24
Peak memory	203012 kb
Host	smart-42d5a896-bf42-4875-870a-b135e176c028
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898176444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.1898176444
Directory	/workspace/30.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.335134698
Short name	T737
Test name
Test status
Simulation time	464433457 ps
CPU time	33.97 seconds
Started	Jul 16 07:43:06 PM PDT 24
Finished	Jul 16 07:43:44 PM PDT 24
Peak memory	302984 kb
Host	smart-c6164eab-562b-4452-8175-7c45f9a009db
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335134698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_throughput_w_partial_write.335134698
Directory	/workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.869795526
Short name	T277
Test name
Test status
Simulation time	3707886950 ps
CPU time	1189.06 seconds
Started	Jul 16 07:43:19 PM PDT 24
Finished	Jul 16 08:03:10 PM PDT 24
Peak memory	373464 kb
Host	smart-d16ea2ba-2bb6-4ee8-ba75-cbec453f1284
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869795526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 31.sram_ctrl_access_during_key_req.869795526
Directory	/workspace/31.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/31.sram_ctrl_alert_test.2166198985
Short name	T297
Test name
Test status
Simulation time	89738782 ps
CPU time	0.63 seconds
Started	Jul 16 07:43:21 PM PDT 24
Finished	Jul 16 07:43:25 PM PDT 24
Peak memory	202608 kb
Host	smart-a47fa9d9-7e47-4bc1-9e6c-51ee0165a228
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166198985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2166198985
Directory	/workspace/31.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.sram_ctrl_bijection.1724761625
Short name	T295
Test name
Test status
Simulation time	937304669 ps
CPU time	62.63 seconds
Started	Jul 16 07:43:20 PM PDT 24
Finished	Jul 16 07:44:25 PM PDT 24
Peak memory	202776 kb
Host	smart-1d4ff83f-4eb3-4671-844d-b44c38579ee8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724761625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .1724761625
Directory	/workspace/31.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/31.sram_ctrl_executable.3008717527
Short name	T218
Test name
Test status
Simulation time	754509983 ps
CPU time	101.53 seconds
Started	Jul 16 07:43:19 PM PDT 24
Finished	Jul 16 07:45:03 PM PDT 24
Peak memory	354760 kb
Host	smart-609bc268-1e9e-4787-abea-832b48066ffb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008717527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.3008717527
Directory	/workspace/31.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/31.sram_ctrl_lc_escalation.3654108939
Short name	T245
Test name
Test status
Simulation time	3428993368 ps
CPU time	10.68 seconds
Started	Jul 16 07:43:20 PM PDT 24
Finished	Jul 16 07:43:35 PM PDT 24
Peak memory	211144 kb
Host	smart-b7bb8213-6d85-408a-8087-422c83c7e0f7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654108939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.3654108939
Directory	/workspace/31.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/31.sram_ctrl_max_throughput.614021128
Short name	T606
Test name
Test status
Simulation time	84969009 ps
CPU time	31.69 seconds
Started	Jul 16 07:43:19 PM PDT 24
Finished	Jul 16 07:43:54 PM PDT 24
Peak memory	284564 kb
Host	smart-693f08eb-564d-41a1-bf10-004103158800
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614021128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.sram_ctrl_max_throughput.614021128
Directory	/workspace/31.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.323396066
Short name	T58
Test name
Test status
Simulation time	388624272 ps
CPU time	3.5 seconds
Started	Jul 16 07:43:22 PM PDT 24
Finished	Jul 16 07:43:29 PM PDT 24
Peak memory	211016 kb
Host	smart-92a8a71a-9025-49c2-8c17-a8dbe1b3f34b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323396066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .sram_ctrl_mem_partial_access.323396066
Directory	/workspace/31.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_walk.822451169
Short name	T194
Test name
Test status
Simulation time	463504048 ps
CPU time	10.97 seconds
Started	Jul 16 07:43:22 PM PDT 24
Finished	Jul 16 07:43:36 PM PDT 24
Peak memory	211044 kb
Host	smart-d091149a-72f8-4715-b0d5-98553e8ab1db
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822451169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl _mem_walk.822451169
Directory	/workspace/31.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/31.sram_ctrl_multiple_keys.70855385
Short name	T400
Test name
Test status
Simulation time	6450758762 ps
CPU time	420.16 seconds
Started	Jul 16 07:43:21 PM PDT 24
Finished	Jul 16 07:50:25 PM PDT 24
Peak memory	342772 kb
Host	smart-ebfff715-07cb-4a89-bf47-8e637faa596c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70855385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multipl e_keys.70855385
Directory	/workspace/31.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access.3505675232
Short name	T588
Test name
Test status
Simulation time	879825812 ps
CPU time	14.22 seconds
Started	Jul 16 07:43:21 PM PDT 24
Finished	Jul 16 07:43:38 PM PDT 24
Peak memory	202784 kb
Host	smart-634e835d-185e-4b38-8a75-b78ecb8ebbea
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505675232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.3505675232
Directory	/workspace/31.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3266240909
Short name	T843
Test name
Test status
Simulation time	3767839413 ps
CPU time	258.68 seconds
Started	Jul 16 07:43:21 PM PDT 24
Finished	Jul 16 07:47:43 PM PDT 24
Peak memory	202932 kb
Host	smart-600b247a-f7b5-4a1d-b539-b69848a8f23d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266240909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.3266240909
Directory	/workspace/31.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/31.sram_ctrl_ram_cfg.711054693
Short name	T431
Test name
Test status
Simulation time	284948945 ps
CPU time	0.76 seconds
Started	Jul 16 07:43:20 PM PDT 24
Finished	Jul 16 07:43:24 PM PDT 24
Peak memory	202848 kb
Host	smart-70380620-34d7-4cbe-8d41-4162363bfdf4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711054693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.711054693
Directory	/workspace/31.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/31.sram_ctrl_regwen.2137017219
Short name	T935
Test name
Test status
Simulation time	12194906769 ps
CPU time	470.26 seconds
Started	Jul 16 07:43:22 PM PDT 24
Finished	Jul 16 07:51:15 PM PDT 24
Peak memory	353316 kb
Host	smart-e518bd7e-765a-47f3-9368-ffecd9e1feec
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137017219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2137017219
Directory	/workspace/31.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/31.sram_ctrl_smoke.321440936
Short name	T457
Test name
Test status
Simulation time	507903485 ps
CPU time	38.14 seconds
Started	Jul 16 07:43:19 PM PDT 24
Finished	Jul 16 07:44:00 PM PDT 24
Peak memory	299984 kb
Host	smart-3d524010-629e-4a34-8a1c-3af139caaea5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321440936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.321440936
Directory	/workspace/31.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all.2973160299
Short name	T811
Test name
Test status
Simulation time	15058595320 ps
CPU time	4016.22 seconds
Started	Jul 16 07:43:20 PM PDT 24
Finished	Jul 16 08:50:20 PM PDT 24
Peak memory	384872 kb
Host	smart-6062dc3c-4bb8-4f9f-93f8-fdc1fcce3451
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973160299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.2973160299
Directory	/workspace/31.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3161599391
Short name	T664
Test name
Test status
Simulation time	228013270 ps
CPU time	21.51 seconds
Started	Jul 16 07:43:19 PM PDT 24
Finished	Jul 16 07:43:43 PM PDT 24
Peak memory	239612 kb
Host	smart-5d76770b-c6c6-44fe-9586-c786c6545905
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3161599391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3161599391
Directory	/workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1645510980
Short name	T289
Test name
Test status
Simulation time	7954612979 ps
CPU time	190.6 seconds
Started	Jul 16 07:43:19 PM PDT 24
Finished	Jul 16 07:46:32 PM PDT 24
Peak memory	202908 kb
Host	smart-d975a7b5-68b3-46b0-b3e6-c64277c80381
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645510980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.1645510980
Directory	/workspace/31.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1916974241
Short name	T924
Test name
Test status
Simulation time	335907785 ps
CPU time	64.86 seconds
Started	Jul 16 07:43:21 PM PDT 24
Finished	Jul 16 07:44:29 PM PDT 24
Peak memory	318020 kb
Host	smart-6b31bde5-0629-4214-b321-7a2a227dae89
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916974241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1916974241
Directory	/workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.918476698
Short name	T528
Test name
Test status
Simulation time	3728213015 ps
CPU time	1147.91 seconds
Started	Jul 16 07:43:34 PM PDT 24
Finished	Jul 16 08:02:43 PM PDT 24
Peak memory	363460 kb
Host	smart-c6d80544-e94a-4520-a933-795c5abd3ef8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918476698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 32.sram_ctrl_access_during_key_req.918476698
Directory	/workspace/32.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/32.sram_ctrl_alert_test.921443827
Short name	T844
Test name
Test status
Simulation time	30153175 ps
CPU time	0.63 seconds
Started	Jul 16 07:43:34 PM PDT 24
Finished	Jul 16 07:43:36 PM PDT 24
Peak memory	202668 kb
Host	smart-0c513b3d-0ac9-4765-889c-04e1cef9e547
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921443827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.921443827
Directory	/workspace/32.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.sram_ctrl_bijection.3802442585
Short name	T480
Test name
Test status
Simulation time	2072750471 ps
CPU time	36.9 seconds
Started	Jul 16 07:43:22 PM PDT 24
Finished	Jul 16 07:44:02 PM PDT 24
Peak memory	202812 kb
Host	smart-4b1b93a6-f395-4d68-bb4b-3844ea8758c1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802442585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .3802442585
Directory	/workspace/32.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/32.sram_ctrl_executable.1598341795
Short name	T589
Test name
Test status
Simulation time	12700841717 ps
CPU time	959.93 seconds
Started	Jul 16 07:43:36 PM PDT 24
Finished	Jul 16 07:59:40 PM PDT 24
Peak memory	362068 kb
Host	smart-c0e9dfc3-b834-4b91-a957-3fd24340cbe9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598341795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.1598341795
Directory	/workspace/32.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/32.sram_ctrl_lc_escalation.1734637458
Short name	T633
Test name
Test status
Simulation time	5548050623 ps
CPU time	6.65 seconds
Started	Jul 16 07:43:33 PM PDT 24
Finished	Jul 16 07:43:40 PM PDT 24
Peak memory	211140 kb
Host	smart-439641f3-1ae3-4882-9b6f-241e502ee45c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734637458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.1734637458
Directory	/workspace/32.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/32.sram_ctrl_max_throughput.846697121
Short name	T423
Test name
Test status
Simulation time	300295489 ps
CPU time	20.49 seconds
Started	Jul 16 07:43:24 PM PDT 24
Finished	Jul 16 07:43:47 PM PDT 24
Peak memory	268248 kb
Host	smart-343f9241-a2a4-42b2-8335-9feebe34ac95
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846697121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.sram_ctrl_max_throughput.846697121
Directory	/workspace/32.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3117393113
Short name	T641
Test name
Test status
Simulation time	123575403 ps
CPU time	2.99 seconds
Started	Jul 16 07:43:42 PM PDT 24
Finished	Jul 16 07:43:48 PM PDT 24
Peak memory	211124 kb
Host	smart-795e0a98-a2e4-4925-9111-904ac668ba89
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117393113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.3117393113
Directory	/workspace/32.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_walk.3440445150
Short name	T430
Test name
Test status
Simulation time	134257889 ps
CPU time	5.25 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:43:43 PM PDT 24
Peak memory	211052 kb
Host	smart-5021be54-0e30-44ee-b044-0a691e19c2a7
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440445150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3440445150
Directory	/workspace/32.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/32.sram_ctrl_multiple_keys.3335157738
Short name	T379
Test name
Test status
Simulation time	18631251319 ps
CPU time	1208.89 seconds
Started	Jul 16 07:43:21 PM PDT 24
Finished	Jul 16 08:03:34 PM PDT 24
Peak memory	374956 kb
Host	smart-5eadfd90-279a-4a50-b279-8eebc2bb3d37
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335157738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.3335157738
Directory	/workspace/32.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access.871354080
Short name	T374
Test name
Test status
Simulation time	210677972 ps
CPU time	1.81 seconds
Started	Jul 16 07:43:22 PM PDT 24
Finished	Jul 16 07:43:27 PM PDT 24
Peak memory	202852 kb
Host	smart-b58eca07-008e-43c4-a04a-69a013812b1c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871354080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.s ram_ctrl_partial_access.871354080
Directory	/workspace/32.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2536957480
Short name	T211
Test name
Test status
Simulation time	30450014002 ps
CPU time	239.5 seconds
Started	Jul 16 07:43:23 PM PDT 24
Finished	Jul 16 07:47:25 PM PDT 24
Peak memory	202624 kb
Host	smart-a36e54da-5bd0-4fd2-9c38-530d7161b1e5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536957480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.2536957480
Directory	/workspace/32.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/32.sram_ctrl_ram_cfg.1757458106
Short name	T911
Test name
Test status
Simulation time	41427844 ps
CPU time	0.75 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:43:38 PM PDT 24
Peak memory	202876 kb
Host	smart-52942393-24fc-4369-a7ba-755c50ce202e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757458106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1757458106
Directory	/workspace/32.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/32.sram_ctrl_regwen.235239450
Short name	T772
Test name
Test status
Simulation time	3983603466 ps
CPU time	756.39 seconds
Started	Jul 16 07:43:34 PM PDT 24
Finished	Jul 16 07:56:11 PM PDT 24
Peak memory	366432 kb
Host	smart-a8942747-7e26-4f51-abc8-cd57ef1a6b03
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235239450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.235239450
Directory	/workspace/32.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/32.sram_ctrl_smoke.1105750252
Short name	T180
Test name
Test status
Simulation time	1740237756 ps
CPU time	10.01 seconds
Started	Jul 16 07:43:22 PM PDT 24
Finished	Jul 16 07:43:35 PM PDT 24
Peak memory	202816 kb
Host	smart-038f2e74-a813-4078-b6e2-8221c9fad680
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105750252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1105750252
Directory	/workspace/32.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all.3401157999
Short name	T174
Test name
Test status
Simulation time	37952465870 ps
CPU time	2167.74 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 08:19:48 PM PDT 24
Peak memory	374968 kb
Host	smart-74d9aedd-fac9-4e34-a888-b5555f968a10
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401157999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.3401157999
Directory	/workspace/32.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1793406642
Short name	T620
Test name
Test status
Simulation time	2686336398 ps
CPU time	251 seconds
Started	Jul 16 07:43:23 PM PDT 24
Finished	Jul 16 07:47:37 PM PDT 24
Peak memory	202576 kb
Host	smart-a37d85e4-0556-4df9-b8b0-e109f41278fd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793406642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.1793406642
Directory	/workspace/32.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.500876529
Short name	T168
Test name
Test status
Simulation time	353087982 ps
CPU time	23.41 seconds
Started	Jul 16 07:43:43 PM PDT 24
Finished	Jul 16 07:44:08 PM PDT 24
Peak memory	279292 kb
Host	smart-1cb70de7-2718-4a89-9563-1d94a55ecd92
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500876529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_throughput_w_partial_write.500876529
Directory	/workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3415045128
Short name	T561
Test name
Test status
Simulation time	2150070758 ps
CPU time	552.75 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:52:49 PM PDT 24
Peak memory	371608 kb
Host	smart-765fa229-3992-4dd2-92ab-524329ec2da5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415045128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.3415045128
Directory	/workspace/33.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/33.sram_ctrl_alert_test.3335330003
Short name	T738
Test name
Test status
Simulation time	17201302 ps
CPU time	0.65 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:43:38 PM PDT 24
Peak memory	202632 kb
Host	smart-21958eb3-b6aa-4f66-9225-246bb02ec6a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335330003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3335330003
Directory	/workspace/33.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.sram_ctrl_bijection.4163209834
Short name	T410
Test name
Test status
Simulation time	2888156832 ps
CPU time	65.54 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:44:46 PM PDT 24
Peak memory	202980 kb
Host	smart-64bd2483-cdd5-4ea4-90d7-c995563fd3b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163209834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .4163209834
Directory	/workspace/33.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/33.sram_ctrl_executable.3449889529
Short name	T707
Test name
Test status
Simulation time	37354117786 ps
CPU time	1207.69 seconds
Started	Jul 16 07:43:38 PM PDT 24
Finished	Jul 16 08:03:49 PM PDT 24
Peak memory	375420 kb
Host	smart-90d0e184-08fe-4475-8053-aae00eaea0bd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449889529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.3449889529
Directory	/workspace/33.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/33.sram_ctrl_lc_escalation.647643230
Short name	T434
Test name
Test status
Simulation time	2685335867 ps
CPU time	9.22 seconds
Started	Jul 16 07:43:43 PM PDT 24
Finished	Jul 16 07:43:54 PM PDT 24
Peak memory	211148 kb
Host	smart-a64c6820-438f-4688-a3a9-975ff8450280
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647643230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esc alation.647643230
Directory	/workspace/33.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/33.sram_ctrl_max_throughput.2826371049
Short name	T256
Test name
Test status
Simulation time	185493734 ps
CPU time	120.75 seconds
Started	Jul 16 07:43:43 PM PDT 24
Finished	Jul 16 07:45:46 PM PDT 24
Peak memory	366284 kb
Host	smart-a9e37926-ca15-4524-b3cc-f76a15e7e790
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826371049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.2826371049
Directory	/workspace/33.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3159312990
Short name	T845
Test name
Test status
Simulation time	173141488 ps
CPU time	5.75 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:43:42 PM PDT 24
Peak memory	211036 kb
Host	smart-66b96950-b44e-40f3-8423-5acfb0f7e19a
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159312990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.3159312990
Directory	/workspace/33.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_walk.1933661819
Short name	T413
Test name
Test status
Simulation time	4501983668 ps
CPU time	5.83 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:43:46 PM PDT 24
Peak memory	211236 kb
Host	smart-eaa073df-3a23-44b6-b4f7-9c400953351b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933661819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.1933661819
Directory	/workspace/33.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/33.sram_ctrl_multiple_keys.775653496
Short name	T175
Test name
Test status
Simulation time	3844425681 ps
CPU time	655.1 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:54:32 PM PDT 24
Peak memory	375592 kb
Host	smart-2439e3ae-3f58-4dff-b738-ed9889a9be15
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775653496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip le_keys.775653496
Directory	/workspace/33.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access.3778560335
Short name	T144
Test name
Test status
Simulation time	1089379219 ps
CPU time	97.32 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:45:18 PM PDT 24
Peak memory	336636 kb
Host	smart-8f0eabd6-404c-451d-98ea-e9154f81e501
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778560335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.3778560335
Directory	/workspace/33.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2434239004
Short name	T360
Test name
Test status
Simulation time	81141556067 ps
CPU time	493.51 seconds
Started	Jul 16 07:43:36 PM PDT 24
Finished	Jul 16 07:51:54 PM PDT 24
Peak memory	202920 kb
Host	smart-7cb1218a-ef44-4ce0-89fc-803a8bd9e724
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434239004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2434239004
Directory	/workspace/33.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/33.sram_ctrl_ram_cfg.530636967
Short name	T272
Test name
Test status
Simulation time	33238732 ps
CPU time	0.78 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:43:37 PM PDT 24
Peak memory	202812 kb
Host	smart-461f2563-ba09-40d1-80d8-ed12b248a132
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530636967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.530636967
Directory	/workspace/33.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/33.sram_ctrl_regwen.4155888203
Short name	T452
Test name
Test status
Simulation time	32751940478 ps
CPU time	1081.15 seconds
Started	Jul 16 07:43:33 PM PDT 24
Finished	Jul 16 08:01:35 PM PDT 24
Peak memory	372340 kb
Host	smart-3d3f6c00-8eaa-4bfb-91fc-2be17a01b6fe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155888203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.4155888203
Directory	/workspace/33.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/33.sram_ctrl_smoke.2422928063
Short name	T146
Test name
Test status
Simulation time	138456068 ps
CPU time	102.37 seconds
Started	Jul 16 07:43:43 PM PDT 24
Finished	Jul 16 07:45:27 PM PDT 24
Peak memory	355060 kb
Host	smart-a15b8486-7665-4c3b-ac9e-a2226a2e8416
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422928063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2422928063
Directory	/workspace/33.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all.112860347
Short name	T900
Test name
Test status
Simulation time	26702153571 ps
CPU time	1822.83 seconds
Started	Jul 16 07:43:36 PM PDT 24
Finished	Jul 16 08:14:03 PM PDT 24
Peak memory	382944 kb
Host	smart-3f786ba0-59bb-4b75-8045-d67d9dbe477d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112860347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_stress_all.112860347
Directory	/workspace/33.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.241215762
Short name	T514
Test name
Test status
Simulation time	485697200 ps
CPU time	32.59 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:44:10 PM PDT 24
Peak memory	263264 kb
Host	smart-d6097453-912e-412b-8be1-46661a1403aa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=241215762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.241215762
Directory	/workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3747575729
Short name	T510
Test name
Test status
Simulation time	2321022323 ps
CPU time	221.15 seconds
Started	Jul 16 07:43:36 PM PDT 24
Finished	Jul 16 07:47:20 PM PDT 24
Peak memory	202892 kb
Host	smart-71b17313-6c01-4c79-80ec-5e0f137a80ee
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747575729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.3747575729
Directory	/workspace/33.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1530265137
Short name	T158
Test name
Test status
Simulation time	213729785 ps
CPU time	42.41 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:44:20 PM PDT 24
Peak memory	301972 kb
Host	smart-dfc6ba3d-2a34-4874-9ce6-a43fc2898245
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530265137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1530265137
Directory	/workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3796001544
Short name	T7
Test name
Test status
Simulation time	3618293499 ps
CPU time	193.48 seconds
Started	Jul 16 07:43:36 PM PDT 24
Finished	Jul 16 07:46:53 PM PDT 24
Peak memory	346108 kb
Host	smart-e92f3a64-07a8-41cd-87ec-1d3e4680a7b5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796001544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.3796001544
Directory	/workspace/34.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/34.sram_ctrl_alert_test.1786600990
Short name	T821
Test name
Test status
Simulation time	12919253 ps
CPU time	0.64 seconds
Started	Jul 16 07:43:36 PM PDT 24
Finished	Jul 16 07:43:41 PM PDT 24
Peak memory	202648 kb
Host	smart-56d605e0-9826-4385-a30f-33bbc16377a4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786600990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1786600990
Directory	/workspace/34.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.sram_ctrl_bijection.2576528743
Short name	T574
Test name
Test status
Simulation time	1333129110 ps
CPU time	29.47 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:44:06 PM PDT 24
Peak memory	202888 kb
Host	smart-7fa15bea-2603-4106-8db2-1d43385ba7fb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576528743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .2576528743
Directory	/workspace/34.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/34.sram_ctrl_executable.428633733
Short name	T339
Test name
Test status
Simulation time	616663988 ps
CPU time	212.57 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:47:13 PM PDT 24
Peak memory	358868 kb
Host	smart-653165d0-728a-417c-b216-7b81ba6314a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428633733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executabl e.428633733
Directory	/workspace/34.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/34.sram_ctrl_lc_escalation.2225351813
Short name	T682
Test name
Test status
Simulation time	1539833423 ps
CPU time	6.84 seconds
Started	Jul 16 07:43:44 PM PDT 24
Finished	Jul 16 07:43:53 PM PDT 24
Peak memory	202792 kb
Host	smart-37f995c1-9f4c-4a3a-9c3f-bc4b3d22325a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225351813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.2225351813
Directory	/workspace/34.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/34.sram_ctrl_max_throughput.2155657392
Short name	T841
Test name
Test status
Simulation time	138690683 ps
CPU time	108.36 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:45:29 PM PDT 24
Peak memory	358308 kb
Host	smart-b3e92ae9-880b-45e3-8fba-4c7bd0ec7476
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155657392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.2155657392
Directory	/workspace/34.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1731126509
Short name	T404
Test name
Test status
Simulation time	188039108 ps
CPU time	5.58 seconds
Started	Jul 16 07:43:36 PM PDT 24
Finished	Jul 16 07:43:45 PM PDT 24
Peak memory	210992 kb
Host	smart-de6ed631-b649-42d9-abdf-9d9c33968594
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731126509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.1731126509
Directory	/workspace/34.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_walk.2986968630
Short name	T866
Test name
Test status
Simulation time	478607195 ps
CPU time	6.54 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:43:42 PM PDT 24
Peak memory	211052 kb
Host	smart-6cf0afcf-1a03-4911-894d-9d53515c8b4f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986968630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.2986968630
Directory	/workspace/34.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/34.sram_ctrl_multiple_keys.4002276535
Short name	T220
Test name
Test status
Simulation time	7690896117 ps
CPU time	1328.9 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 08:05:47 PM PDT 24
Peak memory	375728 kb
Host	smart-4c5dab8c-4496-4cbb-9ab2-5d8c2e4b1287
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002276535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.4002276535
Directory	/workspace/34.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access.3334430249
Short name	T214
Test name
Test status
Simulation time	248742712 ps
CPU time	14.59 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:43:55 PM PDT 24
Peak memory	245312 kb
Host	smart-9d871b43-7081-45d0-8ec7-728c218f4f33
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334430249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.3334430249
Directory	/workspace/34.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2823073399
Short name	T389
Test name
Test status
Simulation time	5103006053 ps
CPU time	366.18 seconds
Started	Jul 16 07:43:36 PM PDT 24
Finished	Jul 16 07:49:46 PM PDT 24
Peak memory	202980 kb
Host	smart-a684cc71-61b1-4ceb-ad9e-eaa0af91478d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823073399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.2823073399
Directory	/workspace/34.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/34.sram_ctrl_ram_cfg.2684180565
Short name	T184
Test name
Test status
Simulation time	69671686 ps
CPU time	0.74 seconds
Started	Jul 16 07:43:42 PM PDT 24
Finished	Jul 16 07:43:46 PM PDT 24
Peak memory	202884 kb
Host	smart-4033ecb9-a4d7-46bb-9795-8dd6cb7be4bc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684180565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2684180565
Directory	/workspace/34.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/34.sram_ctrl_regwen.3379687918
Short name	T498
Test name
Test status
Simulation time	5177459497 ps
CPU time	519.62 seconds
Started	Jul 16 07:43:42 PM PDT 24
Finished	Jul 16 07:52:24 PM PDT 24
Peak memory	361428 kb
Host	smart-de3c862b-5ba6-44ae-ba4c-9c5cf782b89a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379687918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3379687918
Directory	/workspace/34.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/34.sram_ctrl_smoke.1074046757
Short name	T817
Test name
Test status
Simulation time	492368804 ps
CPU time	50.15 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:44:30 PM PDT 24
Peak memory	295708 kb
Host	smart-7092c1ec-276e-4eb5-a16c-8fe3f10199be
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074046757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1074046757
Directory	/workspace/34.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all.1214132151
Short name	T827
Test name
Test status
Simulation time	12254386065 ps
CPU time	2112.51 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 08:18:54 PM PDT 24
Peak memory	376740 kb
Host	smart-a97d2900-4fcb-4614-b8d7-4dbd936d3391
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214132151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.1214132151
Directory	/workspace/34.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.237364499
Short name	T564
Test name
Test status
Simulation time	1711163566 ps
CPU time	164.58 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:46:25 PM PDT 24
Peak memory	371236 kb
Host	smart-150ed5ec-dccb-4949-829b-a7c12f65def3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=237364499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.237364499
Directory	/workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3296043512
Short name	T545
Test name
Test status
Simulation time	2048426862 ps
CPU time	188.96 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:46:50 PM PDT 24
Peak memory	202828 kb
Host	smart-092cfcf7-cc6c-46d2-9148-1481a18633f8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296043512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.3296043512
Directory	/workspace/34.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3893570863
Short name	T604
Test name
Test status
Simulation time	78556943 ps
CPU time	6.01 seconds
Started	Jul 16 07:43:38 PM PDT 24
Finished	Jul 16 07:43:47 PM PDT 24
Peak memory	235536 kb
Host	smart-bdfdc474-a6a8-4042-9105-83dcd7a78d8a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893570863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3893570863
Directory	/workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.4157753980
Short name	T469
Test name
Test status
Simulation time	1495077593 ps
CPU time	306.72 seconds
Started	Jul 16 07:43:51 PM PDT 24
Finished	Jul 16 07:49:00 PM PDT 24
Peak memory	337468 kb
Host	smart-7782e16c-1410-4098-a6f5-bd80c576943d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157753980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.4157753980
Directory	/workspace/35.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/35.sram_ctrl_alert_test.1156559774
Short name	T698
Test name
Test status
Simulation time	15285906 ps
CPU time	0.66 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:43:56 PM PDT 24
Peak memory	202668 kb
Host	smart-f12875e4-af70-464e-a0ef-637335e41677
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156559774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1156559774
Directory	/workspace/35.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.sram_ctrl_bijection.1021183117
Short name	T253
Test name
Test status
Simulation time	9060208204 ps
CPU time	38.57 seconds
Started	Jul 16 07:43:42 PM PDT 24
Finished	Jul 16 07:44:24 PM PDT 24
Peak memory	202944 kb
Host	smart-d3835e82-422a-49a2-adb0-adc4bdbba186
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021183117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .1021183117
Directory	/workspace/35.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/35.sram_ctrl_executable.1212815262
Short name	T830
Test name
Test status
Simulation time	122713157800 ps
CPU time	1903.99 seconds
Started	Jul 16 07:43:52 PM PDT 24
Finished	Jul 16 08:15:37 PM PDT 24
Peak memory	375676 kb
Host	smart-9d5f14a9-6ca4-4040-86a5-e5dec6f115a3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212815262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.1212815262
Directory	/workspace/35.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/35.sram_ctrl_lc_escalation.631717702
Short name	T577
Test name
Test status
Simulation time	600303459 ps
CPU time	6.79 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:44:01 PM PDT 24
Peak memory	202844 kb
Host	smart-ef0d9480-4fe9-4ca8-8f3d-4bbfba398e9e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631717702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esc alation.631717702
Directory	/workspace/35.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/35.sram_ctrl_max_throughput.361696950
Short name	T638
Test name
Test status
Simulation time	89705021 ps
CPU time	4.49 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:43:59 PM PDT 24
Peak memory	223232 kb
Host	smart-db9226f4-b93d-43f2-9e41-2a9b383e0d1c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361696950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.sram_ctrl_max_throughput.361696950
Directory	/workspace/35.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.554133262
Short name	T99
Test name
Test status
Simulation time	1665140279 ps
CPU time	4.05 seconds
Started	Jul 16 07:43:51 PM PDT 24
Finished	Jul 16 07:43:56 PM PDT 24
Peak memory	211092 kb
Host	smart-f0ae636d-c0d7-4760-a9c7-fa983c54dee9
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554133262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .sram_ctrl_mem_partial_access.554133262
Directory	/workspace/35.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_walk.516341937
Short name	T376
Test name
Test status
Simulation time	1293956948 ps
CPU time	10.09 seconds
Started	Jul 16 07:43:51 PM PDT 24
Finished	Jul 16 07:44:02 PM PDT 24
Peak memory	210984 kb
Host	smart-70259f4f-9d37-4917-9d66-48dd6d0497cd
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516341937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _mem_walk.516341937
Directory	/workspace/35.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/35.sram_ctrl_multiple_keys.3153641246
Short name	T705
Test name
Test status
Simulation time	23626675901 ps
CPU time	310.93 seconds
Started	Jul 16 07:43:37 PM PDT 24
Finished	Jul 16 07:48:52 PM PDT 24
Peak memory	333760 kb
Host	smart-318955d1-544c-4de2-ac5b-095fa22638f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153641246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.3153641246
Directory	/workspace/35.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access.468456967
Short name	T521
Test name
Test status
Simulation time	144634089 ps
CPU time	30.5 seconds
Started	Jul 16 07:43:35 PM PDT 24
Finished	Jul 16 07:44:07 PM PDT 24
Peak memory	279528 kb
Host	smart-5f38bbfa-8a3e-420a-baac-385b53f303d1
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468456967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.s ram_ctrl_partial_access.468456967
Directory	/workspace/35.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2906840662
Short name	T801
Test name
Test status
Simulation time	4683149582 ps
CPU time	346.4 seconds
Started	Jul 16 07:43:42 PM PDT 24
Finished	Jul 16 07:49:31 PM PDT 24
Peak memory	202916 kb
Host	smart-eecf3815-8aee-43c9-bbc4-263ba7406a97
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906840662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.2906840662
Directory	/workspace/35.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/35.sram_ctrl_ram_cfg.3357122431
Short name	T148
Test name
Test status
Simulation time	49829233 ps
CPU time	0.79 seconds
Started	Jul 16 07:43:52 PM PDT 24
Finished	Jul 16 07:43:55 PM PDT 24
Peak memory	202900 kb
Host	smart-6e4e7ad0-f018-4d3c-b561-f7eac66f0517
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357122431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3357122431
Directory	/workspace/35.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/35.sram_ctrl_regwen.3177105062
Short name	T909
Test name
Test status
Simulation time	1882860582 ps
CPU time	26.93 seconds
Started	Jul 16 07:43:56 PM PDT 24
Finished	Jul 16 07:44:24 PM PDT 24
Peak memory	251280 kb
Host	smart-a1a0bb66-0023-47d9-9162-693cb5f919e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177105062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.3177105062
Directory	/workspace/35.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/35.sram_ctrl_smoke.1386883383
Short name	T661
Test name
Test status
Simulation time	309325830 ps
CPU time	2.24 seconds
Started	Jul 16 07:43:36 PM PDT 24
Finished	Jul 16 07:43:41 PM PDT 24
Peak memory	202800 kb
Host	smart-20149a11-13ce-4add-9ad3-01924d8d1a44
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386883383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1386883383
Directory	/workspace/35.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all.3583103914
Short name	T570
Test name
Test status
Simulation time	12212379900 ps
CPU time	1086.98 seconds
Started	Jul 16 07:43:55 PM PDT 24
Finished	Jul 16 08:02:04 PM PDT 24
Peak memory	370604 kb
Host	smart-791ea2b1-9436-4de0-aff7-681d4241c688
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583103914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.3583103914
Directory	/workspace/35.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3751891631
Short name	T49
Test name
Test status
Simulation time	1293712215 ps
CPU time	124.95 seconds
Started	Jul 16 07:43:51 PM PDT 24
Finished	Jul 16 07:45:58 PM PDT 24
Peak memory	361396 kb
Host	smart-0362ddec-c90e-4136-88a6-99b5cb3ca740
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3751891631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3751891631
Directory	/workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1663829199
Short name	T399
Test name
Test status
Simulation time	16144881909 ps
CPU time	378.9 seconds
Started	Jul 16 07:43:38 PM PDT 24
Finished	Jul 16 07:50:00 PM PDT 24
Peak memory	202928 kb
Host	smart-8b58d224-4a49-4380-9756-adf3663c0121
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663829199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1663829199
Directory	/workspace/35.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2711488760
Short name	T854
Test name
Test status
Simulation time	594014477 ps
CPU time	93.62 seconds
Started	Jul 16 07:43:52 PM PDT 24
Finished	Jul 16 07:45:28 PM PDT 24
Peak memory	370220 kb
Host	smart-e319352a-64b9-4e64-a157-907374138710
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711488760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.2711488760
Directory	/workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2293825005
Short name	T43
Test name
Test status
Simulation time	20632958150 ps
CPU time	1023.64 seconds
Started	Jul 16 07:43:58 PM PDT 24
Finished	Jul 16 08:01:04 PM PDT 24
Peak memory	375036 kb
Host	smart-e50587b0-a0f8-4b47-b55a-a97cdf0493b2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293825005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.2293825005
Directory	/workspace/36.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/36.sram_ctrl_alert_test.2989355050
Short name	T301
Test name
Test status
Simulation time	23419909 ps
CPU time	0.67 seconds
Started	Jul 16 07:43:56 PM PDT 24
Finished	Jul 16 07:43:58 PM PDT 24
Peak memory	202608 kb
Host	smart-884ad220-11b0-4091-8113-830b1327b0d0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989355050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.2989355050
Directory	/workspace/36.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.sram_ctrl_bijection.1932792257
Short name	T468
Test name
Test status
Simulation time	14472121190 ps
CPU time	81.01 seconds
Started	Jul 16 07:43:50 PM PDT 24
Finished	Jul 16 07:45:12 PM PDT 24
Peak memory	202924 kb
Host	smart-75b0d710-d1f7-4c9b-8b1c-b62b527bf9c4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932792257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .1932792257
Directory	/workspace/36.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/36.sram_ctrl_executable.3343443120
Short name	T311
Test name
Test status
Simulation time	16110264399 ps
CPU time	1164.06 seconds
Started	Jul 16 07:43:52 PM PDT 24
Finished	Jul 16 08:03:17 PM PDT 24
Peak memory	374704 kb
Host	smart-af5fe695-d0ad-4f33-9440-c5bdb533cd9e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343443120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.3343443120
Directory	/workspace/36.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/36.sram_ctrl_lc_escalation.2208095653
Short name	T153
Test name
Test status
Simulation time	1151626367 ps
CPU time	7.11 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:44:01 PM PDT 24
Peak memory	202812 kb
Host	smart-b341fc72-7482-414a-ab3b-1fd03d9b5d20
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208095653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.2208095653
Directory	/workspace/36.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/36.sram_ctrl_max_throughput.3137939726
Short name	T466
Test name
Test status
Simulation time	134414504 ps
CPU time	126.75 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:46:02 PM PDT 24
Peak memory	370212 kb
Host	smart-843cb132-8a2f-4827-946b-520ebe93bec8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137939726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.3137939726
Directory	/workspace/36.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2374877990
Short name	T438
Test name
Test status
Simulation time	60775184 ps
CPU time	3 seconds
Started	Jul 16 07:43:56 PM PDT 24
Finished	Jul 16 07:44:00 PM PDT 24
Peak memory	211096 kb
Host	smart-f8a3d729-85d2-489a-9c6b-92f1d734214c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374877990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.2374877990
Directory	/workspace/36.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_walk.174013871
Short name	T511
Test name
Test status
Simulation time	1384433875 ps
CPU time	6.38 seconds
Started	Jul 16 07:43:52 PM PDT 24
Finished	Jul 16 07:44:00 PM PDT 24
Peak memory	211120 kb
Host	smart-9b174e8b-d480-4c28-88bd-5a84acc01ac8
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174013871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl _mem_walk.174013871
Directory	/workspace/36.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/36.sram_ctrl_multiple_keys.3924640097
Short name	T807
Test name
Test status
Simulation time	12531347692 ps
CPU time	1538.06 seconds
Started	Jul 16 07:43:56 PM PDT 24
Finished	Jul 16 08:09:36 PM PDT 24
Peak memory	375752 kb
Host	smart-cadd89a3-f692-49e7-8287-b32f6f4f797e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924640097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.3924640097
Directory	/workspace/36.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access.128159513
Short name	T275
Test name
Test status
Simulation time	925298972 ps
CPU time	15.51 seconds
Started	Jul 16 07:43:51 PM PDT 24
Finished	Jul 16 07:44:08 PM PDT 24
Peak memory	202692 kb
Host	smart-2baadbc5-0741-4181-bb1b-729257f82156
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128159513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s ram_ctrl_partial_access.128159513
Directory	/workspace/36.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2999125401
Short name	T851
Test name
Test status
Simulation time	47493880338 ps
CPU time	297.91 seconds
Started	Jul 16 07:43:55 PM PDT 24
Finished	Jul 16 07:48:55 PM PDT 24
Peak memory	202880 kb
Host	smart-c22d5587-5192-48ad-ad3f-238d7ba39c85
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999125401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.2999125401
Directory	/workspace/36.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/36.sram_ctrl_ram_cfg.957289280
Short name	T27
Test name
Test status
Simulation time	50534461 ps
CPU time	0.76 seconds
Started	Jul 16 07:43:51 PM PDT 24
Finished	Jul 16 07:43:53 PM PDT 24
Peak memory	202848 kb
Host	smart-dd1538a1-433e-4826-98de-2445e0cf7ee8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957289280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.957289280
Directory	/workspace/36.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/36.sram_ctrl_regwen.2957265236
Short name	T743
Test name
Test status
Simulation time	31296601665 ps
CPU time	772.5 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:56:47 PM PDT 24
Peak memory	371172 kb
Host	smart-b69f0d49-5279-4ceb-b01a-2f1f0be1d925
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957265236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2957265236
Directory	/workspace/36.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/36.sram_ctrl_smoke.4163253301
Short name	T325
Test name
Test status
Simulation time	58396212 ps
CPU time	11.42 seconds
Started	Jul 16 07:43:57 PM PDT 24
Finished	Jul 16 07:44:10 PM PDT 24
Peak memory	250048 kb
Host	smart-da8fe8fe-45ff-4907-804b-7f587bad0f39
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163253301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.4163253301
Directory	/workspace/36.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all.1275149572
Short name	T787
Test name
Test status
Simulation time	158052084310 ps
CPU time	4515.25 seconds
Started	Jul 16 07:43:54 PM PDT 24
Finished	Jul 16 08:59:11 PM PDT 24
Peak memory	383916 kb
Host	smart-c75ad8a8-e431-49a3-ba7f-ab6120dad348
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275149572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.1275149572
Directory	/workspace/36.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3010342595
Short name	T123
Test name
Test status
Simulation time	2515234715 ps
CPU time	39.45 seconds
Started	Jul 16 07:43:52 PM PDT 24
Finished	Jul 16 07:44:33 PM PDT 24
Peak memory	310424 kb
Host	smart-d3dca733-bfee-48c2-85de-a6d2b589c5db
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3010342595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3010342595
Directory	/workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3893644578
Short name	T186
Test name
Test status
Simulation time	5738885624 ps
CPU time	265.99 seconds
Started	Jul 16 07:43:56 PM PDT 24
Finished	Jul 16 07:48:24 PM PDT 24
Peak memory	202908 kb
Host	smart-ae5c188b-b045-4b54-836d-9709094a76ed
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893644578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.3893644578
Directory	/workspace/36.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1263547155
Short name	T826
Test name
Test status
Simulation time	577212875 ps
CPU time	118.16 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:45:53 PM PDT 24
Peak memory	361156 kb
Host	smart-2cb33db2-84c9-4725-9ae2-3dc9183bade7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263547155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.1263547155
Directory	/workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/37.sram_ctrl_access_during_key_req.435024644
Short name	T504
Test name
Test status
Simulation time	10651232259 ps
CPU time	1491.04 seconds
Started	Jul 16 07:43:54 PM PDT 24
Finished	Jul 16 08:08:47 PM PDT 24
Peak memory	374812 kb
Host	smart-25326182-785b-4bc9-9add-d8833c37513c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435024644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 37.sram_ctrl_access_during_key_req.435024644
Directory	/workspace/37.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/37.sram_ctrl_alert_test.1829373464
Short name	T907
Test name
Test status
Simulation time	31611864 ps
CPU time	0.64 seconds
Started	Jul 16 07:44:13 PM PDT 24
Finished	Jul 16 07:44:16 PM PDT 24
Peak memory	202652 kb
Host	smart-1fb70533-97e2-43f3-ab12-8822677cd374
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829373464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1829373464
Directory	/workspace/37.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.sram_ctrl_bijection.1365821378
Short name	T188
Test name
Test status
Simulation time	2982876326 ps
CPU time	25.18 seconds
Started	Jul 16 07:43:52 PM PDT 24
Finished	Jul 16 07:44:18 PM PDT 24
Peak memory	202816 kb
Host	smart-5049b46f-669e-43eb-abad-89139c40235e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365821378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .1365821378
Directory	/workspace/37.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/37.sram_ctrl_executable.3545678062
Short name	T159
Test name
Test status
Simulation time	66659577053 ps
CPU time	1083.79 seconds
Started	Jul 16 07:43:54 PM PDT 24
Finished	Jul 16 08:01:59 PM PDT 24
Peak memory	369592 kb
Host	smart-83336a3f-f8d6-404e-af0c-47b59cc933bf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545678062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.3545678062
Directory	/workspace/37.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/37.sram_ctrl_lc_escalation.2996006369
Short name	T624
Test name
Test status
Simulation time	405871739 ps
CPU time	1.47 seconds
Started	Jul 16 07:43:52 PM PDT 24
Finished	Jul 16 07:43:55 PM PDT 24
Peak memory	210948 kb
Host	smart-e860286d-60f1-49df-891a-aa5c3132b19e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996006369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.2996006369
Directory	/workspace/37.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/37.sram_ctrl_max_throughput.1680682410
Short name	T868
Test name
Test status
Simulation time	330741618 ps
CPU time	95.27 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:45:30 PM PDT 24
Peak memory	370120 kb
Host	smart-1f488c95-91d7-4c73-9ec8-39ba37b4c370
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680682410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.1680682410
Directory	/workspace/37.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_partial_access.4032605454
Short name	T183
Test name
Test status
Simulation time	46547589 ps
CPU time	2.62 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 07:44:15 PM PDT 24
Peak memory	211060 kb
Host	smart-c92ca9f0-ba30-4a94-a399-5e84a6631721
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032605454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.4032605454
Directory	/workspace/37.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_walk.2519170431
Short name	T407
Test name
Test status
Simulation time	597292567 ps
CPU time	8.87 seconds
Started	Jul 16 07:44:16 PM PDT 24
Finished	Jul 16 07:44:26 PM PDT 24
Peak memory	210740 kb
Host	smart-fc8f0396-e15b-406c-9a79-95d4da9a61f8
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519170431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.2519170431
Directory	/workspace/37.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/37.sram_ctrl_multiple_keys.3058579550
Short name	T523
Test name
Test status
Simulation time	6194695367 ps
CPU time	464.06 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:51:39 PM PDT 24
Peak memory	373664 kb
Host	smart-b5d33b95-942e-4289-869b-c6fa1521951c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058579550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.3058579550
Directory	/workspace/37.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access.497345531
Short name	T724
Test name
Test status
Simulation time	151606578 ps
CPU time	7.51 seconds
Started	Jul 16 07:43:54 PM PDT 24
Finished	Jul 16 07:44:03 PM PDT 24
Peak memory	202824 kb
Host	smart-0446a54d-5633-4d4c-9b3b-0be5ee4a9bda
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497345531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s ram_ctrl_partial_access.497345531
Directory	/workspace/37.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1991611641
Short name	T506
Test name
Test status
Simulation time	41552651464 ps
CPU time	406.12 seconds
Started	Jul 16 07:43:56 PM PDT 24
Finished	Jul 16 07:50:43 PM PDT 24
Peak memory	202912 kb
Host	smart-cdee16e8-7957-45e3-810e-4b3af87485b4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991611641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.1991611641
Directory	/workspace/37.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/37.sram_ctrl_ram_cfg.1664075115
Short name	T310
Test name
Test status
Simulation time	32626294 ps
CPU time	0.75 seconds
Started	Jul 16 07:43:54 PM PDT 24
Finished	Jul 16 07:43:57 PM PDT 24
Peak memory	202884 kb
Host	smart-651e305a-c124-4351-a136-96533b78a9cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664075115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1664075115
Directory	/workspace/37.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/37.sram_ctrl_regwen.3591049728
Short name	T755
Test name
Test status
Simulation time	6686268909 ps
CPU time	577.45 seconds
Started	Jul 16 07:43:56 PM PDT 24
Finished	Jul 16 07:53:35 PM PDT 24
Peak memory	365500 kb
Host	smart-78e4e03d-1914-4a7a-960b-d0c4c15968c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591049728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3591049728
Directory	/workspace/37.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/37.sram_ctrl_smoke.2634512416
Short name	T750
Test name
Test status
Simulation time	544835075 ps
CPU time	5.42 seconds
Started	Jul 16 07:43:52 PM PDT 24
Finished	Jul 16 07:43:59 PM PDT 24
Peak memory	220084 kb
Host	smart-1e92e74d-e057-4171-b7a1-d2faf70ba357
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634512416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2634512416
Directory	/workspace/37.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all.545937013
Short name	T847
Test name
Test status
Simulation time	22974938202 ps
CPU time	362.8 seconds
Started	Jul 16 07:44:13 PM PDT 24
Finished	Jul 16 07:50:18 PM PDT 24
Peak memory	331740 kb
Host	smart-435c0961-0508-434c-8236-13e9207321fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545937013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_stress_all.545937013
Directory	/workspace/37.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2420029737
Short name	T494
Test name
Test status
Simulation time	5258987721 ps
CPU time	173.01 seconds
Started	Jul 16 07:44:14 PM PDT 24
Finished	Jul 16 07:47:09 PM PDT 24
Peak memory	351396 kb
Host	smart-a4e7c1af-2023-4b9b-91f0-69fffbee2626
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2420029737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2420029737
Directory	/workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.4100974612
Short name	T293
Test name
Test status
Simulation time	1401814264 ps
CPU time	133.05 seconds
Started	Jul 16 07:43:53 PM PDT 24
Finished	Jul 16 07:46:07 PM PDT 24
Peak memory	202844 kb
Host	smart-d736b47e-d696-48d2-8130-9263d75691ba
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100974612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.4100974612
Directory	/workspace/37.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4035332387
Short name	T155
Test name
Test status
Simulation time	134223830 ps
CPU time	67.45 seconds
Started	Jul 16 07:43:54 PM PDT 24
Finished	Jul 16 07:45:03 PM PDT 24
Peak memory	328468 kb
Host	smart-f3393d41-5c72-4d47-91a2-4fe7a651e250
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035332387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.4035332387
Directory	/workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/38.sram_ctrl_access_during_key_req.2516956501
Short name	T238
Test name
Test status
Simulation time	15701436887 ps
CPU time	1130.43 seconds
Started	Jul 16 07:44:16 PM PDT 24
Finished	Jul 16 08:03:08 PM PDT 24
Peak memory	374792 kb
Host	smart-eba9165b-b60f-4854-bcce-c4d7003f01fd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516956501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.2516956501
Directory	/workspace/38.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/38.sram_ctrl_alert_test.469167519
Short name	T165
Test name
Test status
Simulation time	16018020 ps
CPU time	0.66 seconds
Started	Jul 16 07:44:10 PM PDT 24
Finished	Jul 16 07:44:12 PM PDT 24
Peak memory	202620 kb
Host	smart-765616c9-bb51-4763-ab81-7b21c3c4a35b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469167519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.469167519
Directory	/workspace/38.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.sram_ctrl_bijection.1082484987
Short name	T336
Test name
Test status
Simulation time	10364474684 ps
CPU time	66.63 seconds
Started	Jul 16 07:44:12 PM PDT 24
Finished	Jul 16 07:45:21 PM PDT 24
Peak memory	202896 kb
Host	smart-dd341876-c677-4ae7-bbbd-4bdf39d22928
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082484987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .1082484987
Directory	/workspace/38.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/38.sram_ctrl_executable.225973712
Short name	T686
Test name
Test status
Simulation time	1606930289 ps
CPU time	794.68 seconds
Started	Jul 16 07:44:13 PM PDT 24
Finished	Jul 16 07:57:30 PM PDT 24
Peak memory	373256 kb
Host	smart-d1e994e5-aaa0-4594-96ba-0543d19a9da0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225973712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executabl e.225973712
Directory	/workspace/38.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/38.sram_ctrl_lc_escalation.3557476667
Short name	T932
Test name
Test status
Simulation time	127192560 ps
CPU time	1.16 seconds
Started	Jul 16 07:44:12 PM PDT 24
Finished	Jul 16 07:44:15 PM PDT 24
Peak memory	202548 kb
Host	smart-0a1eb568-148d-49a3-a0dd-6a80b72dcda1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557476667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.3557476667
Directory	/workspace/38.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/38.sram_ctrl_max_throughput.737833273
Short name	T426
Test name
Test status
Simulation time	96442190 ps
CPU time	37.08 seconds
Started	Jul 16 07:44:14 PM PDT 24
Finished	Jul 16 07:44:53 PM PDT 24
Peak memory	300788 kb
Host	smart-9494bec8-99b7-4437-b18d-23a68e672d9f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737833273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.sram_ctrl_max_throughput.737833273
Directory	/workspace/38.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.3474403495
Short name	T314
Test name
Test status
Simulation time	110391591 ps
CPU time	2.9 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 07:44:15 PM PDT 24
Peak memory	210996 kb
Host	smart-bbbd758b-0f73-41b8-9dc5-f304628f9b43
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474403495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.3474403495
Directory	/workspace/38.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_walk.2102900531
Short name	T358
Test name
Test status
Simulation time	618821812 ps
CPU time	9.23 seconds
Started	Jul 16 07:44:12 PM PDT 24
Finished	Jul 16 07:44:23 PM PDT 24
Peak memory	211088 kb
Host	smart-3062d300-8a30-43b6-a257-c789111e33eb
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102900531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.2102900531
Directory	/workspace/38.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/38.sram_ctrl_multiple_keys.2401228596
Short name	T320
Test name
Test status
Simulation time	17290471154 ps
CPU time	445.81 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 07:51:38 PM PDT 24
Peak memory	372556 kb
Host	smart-5340f76f-2b83-49d5-94e9-db5ade97ec90
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401228596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.2401228596
Directory	/workspace/38.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access.1788945218
Short name	T877
Test name
Test status
Simulation time	1947545731 ps
CPU time	18.63 seconds
Started	Jul 16 07:44:10 PM PDT 24
Finished	Jul 16 07:44:30 PM PDT 24
Peak memory	202784 kb
Host	smart-1e8e75df-547b-4e76-a7a9-8c3394a9fdbf
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788945218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.1788945218
Directory	/workspace/38.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4009501662
Short name	T503
Test name
Test status
Simulation time	14056041026 ps
CPU time	367 seconds
Started	Jul 16 07:44:10 PM PDT 24
Finished	Jul 16 07:50:18 PM PDT 24
Peak memory	202956 kb
Host	smart-1f13674e-bccb-47af-8937-8f64de58c715
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009501662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.4009501662
Directory	/workspace/38.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/38.sram_ctrl_ram_cfg.2748356585
Short name	T818
Test name
Test status
Simulation time	108458060 ps
CPU time	0.77 seconds
Started	Jul 16 07:44:13 PM PDT 24
Finished	Jul 16 07:44:16 PM PDT 24
Peak memory	202844 kb
Host	smart-cb4dd1ae-d1ad-4b43-8c80-8844d6ddebeb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748356585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2748356585
Directory	/workspace/38.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/38.sram_ctrl_regwen.3430554017
Short name	T204
Test name
Test status
Simulation time	23470520703 ps
CPU time	1199.09 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 08:04:12 PM PDT 24
Peak memory	374624 kb
Host	smart-89f3e493-3b54-40d9-8edd-f29e99653804
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430554017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3430554017
Directory	/workspace/38.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/38.sram_ctrl_smoke.287394345
Short name	T375
Test name
Test status
Simulation time	594618341 ps
CPU time	91.19 seconds
Started	Jul 16 07:44:12 PM PDT 24
Finished	Jul 16 07:45:45 PM PDT 24
Peak memory	333448 kb
Host	smart-2809e7ec-1758-4766-90b4-347eb5773427
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287394345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.287394345
Directory	/workspace/38.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all.559518782
Short name	T618
Test name
Test status
Simulation time	31249784096 ps
CPU time	3972.45 seconds
Started	Jul 16 07:44:12 PM PDT 24
Finished	Jul 16 08:50:27 PM PDT 24
Peak memory	376772 kb
Host	smart-8a94b099-ebde-4287-b237-bc385ca3ede7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559518782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_stress_all.559518782
Directory	/workspace/38.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.644226279
Short name	T120
Test name
Test status
Simulation time	318653838 ps
CPU time	10.31 seconds
Started	Jul 16 07:44:13 PM PDT 24
Finished	Jul 16 07:44:25 PM PDT 24
Peak memory	212484 kb
Host	smart-e91c46a5-9ebf-4395-ad55-7b01bb3759e8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=644226279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.644226279
Directory	/workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1905458923
Short name	T448
Test name
Test status
Simulation time	6263319536 ps
CPU time	313.19 seconds
Started	Jul 16 07:44:13 PM PDT 24
Finished	Jul 16 07:49:29 PM PDT 24
Peak memory	202888 kb
Host	smart-98574d57-719f-4da9-9741-ce2255e74d22
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905458923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.1905458923
Directory	/workspace/38.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.859247822
Short name	T803
Test name
Test status
Simulation time	346727811 ps
CPU time	19.47 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 07:44:33 PM PDT 24
Peak memory	278520 kb
Host	smart-2dea4e76-633d-4500-b055-d9f586fbda87
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859247822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.859247822
Directory	/workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1875604437
Short name	T535
Test name
Test status
Simulation time	7324681333 ps
CPU time	802.35 seconds
Started	Jul 16 07:44:12 PM PDT 24
Finished	Jul 16 07:57:37 PM PDT 24
Peak memory	374728 kb
Host	smart-3f2cd48e-2b5c-485f-9b4a-7a9785d677f5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875604437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.1875604437
Directory	/workspace/39.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/39.sram_ctrl_alert_test.756271159
Short name	T754
Test name
Test status
Simulation time	20972155 ps
CPU time	0.65 seconds
Started	Jul 16 07:44:25 PM PDT 24
Finished	Jul 16 07:44:29 PM PDT 24
Peak memory	202628 kb
Host	smart-d6128d94-2475-427f-abab-b1476ee3c626
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756271159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.756271159
Directory	/workspace/39.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.sram_ctrl_bijection.1659618046
Short name	T386
Test name
Test status
Simulation time	884201720 ps
CPU time	29.01 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 07:44:41 PM PDT 24
Peak memory	202784 kb
Host	smart-09e4172d-d3e0-4cd5-9602-8e09ec4a1c6d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659618046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .1659618046
Directory	/workspace/39.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/39.sram_ctrl_executable.2577095995
Short name	T867
Test name
Test status
Simulation time	3199848237 ps
CPU time	198.97 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 07:47:32 PM PDT 24
Peak memory	365580 kb
Host	smart-9a1ddccb-14aa-4d1e-b5e4-2b3b0872eca0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577095995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.2577095995
Directory	/workspace/39.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/39.sram_ctrl_lc_escalation.4020340123
Short name	T822
Test name
Test status
Simulation time	959440222 ps
CPU time	6.27 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 07:44:19 PM PDT 24
Peak memory	202812 kb
Host	smart-029c7cd3-349d-43b4-966f-df3dd1430888
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020340123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.4020340123
Directory	/workspace/39.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/39.sram_ctrl_max_throughput.1509665582
Short name	T147
Test name
Test status
Simulation time	366932675 ps
CPU time	38.71 seconds
Started	Jul 16 07:44:13 PM PDT 24
Finished	Jul 16 07:44:53 PM PDT 24
Peak memory	293812 kb
Host	smart-831c0a88-7e61-4b30-bcfc-37c2da7a367b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509665582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.1509665582
Directory	/workspace/39.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_walk.274320110
Short name	T800
Test name
Test status
Simulation time	273024059 ps
CPU time	4.58 seconds
Started	Jul 16 07:44:24 PM PDT 24
Finished	Jul 16 07:44:31 PM PDT 24
Peak memory	202912 kb
Host	smart-6803709c-ed01-4056-b704-4ebb5cbd6b83
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274320110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _mem_walk.274320110
Directory	/workspace/39.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/39.sram_ctrl_multiple_keys.1174087994
Short name	T234
Test name
Test status
Simulation time	4938871269 ps
CPU time	1021.59 seconds
Started	Jul 16 07:44:16 PM PDT 24
Finished	Jul 16 08:01:19 PM PDT 24
Peak memory	372776 kb
Host	smart-6accbd9b-6fd6-4f8c-8b21-ac257a848ee1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174087994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.1174087994
Directory	/workspace/39.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access.818071924
Short name	T770
Test name
Test status
Simulation time	433688198 ps
CPU time	108.74 seconds
Started	Jul 16 07:44:12 PM PDT 24
Finished	Jul 16 07:46:03 PM PDT 24
Peak memory	367996 kb
Host	smart-87b1f569-6feb-420a-b829-a9892da2c1c4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818071924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s ram_ctrl_partial_access.818071924
Directory	/workspace/39.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1859586139
Short name	T846
Test name
Test status
Simulation time	17826251664 ps
CPU time	256.51 seconds
Started	Jul 16 07:44:13 PM PDT 24
Finished	Jul 16 07:48:31 PM PDT 24
Peak memory	202924 kb
Host	smart-99a359c6-0c28-435c-ac7a-f5c141cb6443
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859586139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.1859586139
Directory	/workspace/39.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/39.sram_ctrl_ram_cfg.422338380
Short name	T573
Test name
Test status
Simulation time	145723536 ps
CPU time	0.82 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 07:44:13 PM PDT 24
Peak memory	202820 kb
Host	smart-3c6fa496-c028-4e2b-a8ee-975a4f2fbaa3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422338380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.422338380
Directory	/workspace/39.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/39.sram_ctrl_regwen.827280821
Short name	T345
Test name
Test status
Simulation time	11812657116 ps
CPU time	1580.07 seconds
Started	Jul 16 07:44:12 PM PDT 24
Finished	Jul 16 08:10:34 PM PDT 24
Peak memory	373852 kb
Host	smart-13b2e060-d225-4937-9e55-81f68f51912a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827280821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.827280821
Directory	/workspace/39.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/39.sram_ctrl_smoke.627938805
Short name	T566
Test name
Test status
Simulation time	174729091 ps
CPU time	11.15 seconds
Started	Jul 16 07:44:12 PM PDT 24
Finished	Jul 16 07:44:26 PM PDT 24
Peak memory	202828 kb
Host	smart-d973ab50-92d9-4fe2-8d12-9fe65f0c227c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627938805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.627938805
Directory	/workspace/39.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all.1251596060
Short name	T462
Test name
Test status
Simulation time	8544384870 ps
CPU time	1662.77 seconds
Started	Jul 16 07:44:26 PM PDT 24
Finished	Jul 16 08:12:11 PM PDT 24
Peak memory	383700 kb
Host	smart-4d5bac9a-d61e-4fb1-8614-75fb32241cb9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251596060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.1251596060
Directory	/workspace/39.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.334608083
Short name	T859
Test name
Test status
Simulation time	876988702 ps
CPU time	20.17 seconds
Started	Jul 16 07:44:24 PM PDT 24
Finished	Jul 16 07:44:47 PM PDT 24
Peak memory	262384 kb
Host	smart-60c41bc3-2ecb-49f8-a95f-c0d3cdc95527
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=334608083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.334608083
Directory	/workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1143471829
Short name	T541
Test name
Test status
Simulation time	17263593560 ps
CPU time	327.36 seconds
Started	Jul 16 07:44:06 PM PDT 24
Finished	Jul 16 07:49:34 PM PDT 24
Peak memory	202952 kb
Host	smart-cfb0a3a2-e9b6-4e78-8e62-e7665a617a92
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143471829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1143471829
Directory	/workspace/39.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2320130526
Short name	T461
Test name
Test status
Simulation time	76746394 ps
CPU time	12.45 seconds
Started	Jul 16 07:44:11 PM PDT 24
Finished	Jul 16 07:44:25 PM PDT 24
Peak memory	251868 kb
Host	smart-42965bcd-d400-4f44-b525-3e771046a001
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320130526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.2320130526
Directory	/workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/4.sram_ctrl_access_during_key_req.460035410
Short name	T179
Test name
Test status
Simulation time	3167537491 ps
CPU time	744.55 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:54:09 PM PDT 24
Peak memory	373488 kb
Host	smart-68da74c3-ced9-40e0-9fd0-f24465c25e07
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460035410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.sram_ctrl_access_during_key_req.460035410
Directory	/workspace/4.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/4.sram_ctrl_alert_test.1527756530
Short name	T383
Test name
Test status
Simulation time	16134220 ps
CPU time	0.64 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:41:47 PM PDT 24
Peak memory	202572 kb
Host	smart-c3f6cbd6-3167-4bea-9139-3c11d80581eb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527756530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.1527756530
Directory	/workspace/4.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.sram_ctrl_bijection.3475517487
Short name	T9
Test name
Test status
Simulation time	34219782278 ps
CPU time	71.78 seconds
Started	Jul 16 07:41:19 PM PDT 24
Finished	Jul 16 07:42:51 PM PDT 24
Peak memory	202888 kb
Host	smart-d0105591-29bd-4388-afdc-5abf47f7777a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475517487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 3475517487
Directory	/workspace/4.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/4.sram_ctrl_executable.199331383
Short name	T258
Test name
Test status
Simulation time	11742328613 ps
CPU time	974.92 seconds
Started	Jul 16 07:41:19 PM PDT 24
Finished	Jul 16 07:57:55 PM PDT 24
Peak memory	374516 kb
Host	smart-eb2dcd35-0b18-448a-bc5f-b0cb747ed17a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199331383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable .199331383
Directory	/workspace/4.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/4.sram_ctrl_lc_escalation.171797533
Short name	T558
Test name
Test status
Simulation time	3806611928 ps
CPU time	7.35 seconds
Started	Jul 16 07:41:26 PM PDT 24
Finished	Jul 16 07:41:53 PM PDT 24
Peak memory	202936 kb
Host	smart-27136eaf-07ad-4ecd-87c8-a0bf72a895e6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171797533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca lation.171797533
Directory	/workspace/4.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/4.sram_ctrl_max_throughput.916525198
Short name	T489
Test name
Test status
Simulation time	510255472 ps
CPU time	103.57 seconds
Started	Jul 16 07:41:16 PM PDT 24
Finished	Jul 16 07:43:19 PM PDT 24
Peak memory	369448 kb
Host	smart-c29eff61-5cce-42bc-aa9b-e8bbf7af457d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916525198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.sram_ctrl_max_throughput.916525198
Directory	/workspace/4.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2370936356
Short name	T441
Test name
Test status
Simulation time	220421930 ps
CPU time	3.24 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:41:47 PM PDT 24
Peak memory	211108 kb
Host	smart-9c0e2e9b-f491-4720-8f37-6bf64672d223
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370936356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.2370936356
Directory	/workspace/4.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_walk.2365752287
Short name	T823
Test name
Test status
Simulation time	363890631 ps
CPU time	8.63 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:54 PM PDT 24
Peak memory	211032 kb
Host	smart-370017f1-d146-4c2f-ac62-69229176f5a8
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365752287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.2365752287
Directory	/workspace/4.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/4.sram_ctrl_multiple_keys.3081395832
Short name	T650
Test name
Test status
Simulation time	26831081054 ps
CPU time	387.53 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 07:48:09 PM PDT 24
Peak memory	343532 kb
Host	smart-a4486531-070c-421f-a875-3fb5393b2f60
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081395832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.3081395832
Directory	/workspace/4.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access.1974437987
Short name	T409
Test name
Test status
Simulation time	895144287 ps
CPU time	40.29 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 07:42:22 PM PDT 24
Peak memory	304324 kb
Host	smart-3f8b20f8-8a5d-487d-a040-c5fa60b96b99
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974437987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.1974437987
Directory	/workspace/4.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1604574224
Short name	T610
Test name
Test status
Simulation time	14646066727 ps
CPU time	183.24 seconds
Started	Jul 16 07:41:20 PM PDT 24
Finished	Jul 16 07:44:44 PM PDT 24
Peak memory	202852 kb
Host	smart-1a62cd5c-fb88-4ddf-8241-66feed3a6ea0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604574224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.1604574224
Directory	/workspace/4.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/4.sram_ctrl_ram_cfg.3878739592
Short name	T612
Test name
Test status
Simulation time	46080916 ps
CPU time	0.82 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:47 PM PDT 24
Peak memory	202836 kb
Host	smart-448d9327-a53c-4a78-afd4-58dbedcbc371
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878739592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3878739592
Directory	/workspace/4.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/4.sram_ctrl_regwen.3722777863
Short name	T856
Test name
Test status
Simulation time	9576673374 ps
CPU time	222.6 seconds
Started	Jul 16 07:41:17 PM PDT 24
Finished	Jul 16 07:45:20 PM PDT 24
Peak memory	345960 kb
Host	smart-a2ae99a0-ac07-42e8-aae9-b8079862953f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722777863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3722777863
Directory	/workspace/4.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/4.sram_ctrl_sec_cm.552968664
Short name	T30
Test name
Test status
Simulation time	230512506 ps
CPU time	3.18 seconds
Started	Jul 16 07:41:20 PM PDT 24
Finished	Jul 16 07:41:44 PM PDT 24
Peak memory	221896 kb
Host	smart-b5f2e963-3c59-48f3-a609-49d7c15405c4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552968664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_sec_cm.552968664
Directory	/workspace/4.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.sram_ctrl_smoke.1700485772
Short name	T941
Test name
Test status
Simulation time	2559931332 ps
CPU time	14.82 seconds
Started	Jul 16 07:41:19 PM PDT 24
Finished	Jul 16 07:41:55 PM PDT 24
Peak memory	202904 kb
Host	smart-65f378f8-8bfc-4637-8afd-997d15f610cc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700485772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1700485772
Directory	/workspace/4.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_all.3195219801
Short name	T79
Test name
Test status
Simulation time	10763388052 ps
CPU time	1289.95 seconds
Started	Jul 16 07:41:19 PM PDT 24
Finished	Jul 16 08:03:10 PM PDT 24
Peak memory	374612 kb
Host	smart-5da93b79-35fd-41b7-939a-272523b5ea38
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195219801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.3195219801
Directory	/workspace/4.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4087525186
Short name	T77
Test name
Test status
Simulation time	5478499725 ps
CPU time	698.27 seconds
Started	Jul 16 07:41:21 PM PDT 24
Finished	Jul 16 07:53:20 PM PDT 24
Peak memory	379916 kb
Host	smart-405f400e-53be-45cb-b599-9ad9856039cc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4087525186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.4087525186
Directory	/workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.790752779
Short name	T225
Test name
Test status
Simulation time	5674794066 ps
CPU time	261.35 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 07:46:03 PM PDT 24
Peak memory	202944 kb
Host	smart-1704e65f-5c10-473c-a20e-5f5cdf8663d0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790752779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. sram_ctrl_stress_pipeline.790752779
Directory	/workspace/4.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1611849185
Short name	T192
Test name
Test status
Simulation time	505349456 ps
CPU time	64.46 seconds
Started	Jul 16 07:41:19 PM PDT 24
Finished	Jul 16 07:42:44 PM PDT 24
Peak memory	323476 kb
Host	smart-45f91d93-634e-4f5f-9a24-5d59a45c6b97
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611849185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1611849185
Directory	/workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/40.sram_ctrl_access_during_key_req.28477147
Short name	T898
Test name
Test status
Simulation time	45664205382 ps
CPU time	1780.32 seconds
Started	Jul 16 07:44:27 PM PDT 24
Finished	Jul 16 08:14:09 PM PDT 24
Peak memory	375912 kb
Host	smart-6a95b73a-21b6-41e9-9ebf-10655d876f67
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28477147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.sram_ctrl_access_during_key_req.28477147
Directory	/workspace/40.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/40.sram_ctrl_alert_test.1129354289
Short name	T292
Test name
Test status
Simulation time	14848354 ps
CPU time	0.63 seconds
Started	Jul 16 07:44:23 PM PDT 24
Finished	Jul 16 07:44:25 PM PDT 24
Peak memory	202660 kb
Host	smart-a2d9f8c5-7e55-4207-af35-924beb53a47e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129354289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1129354289
Directory	/workspace/40.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.sram_ctrl_bijection.831760715
Short name	T688
Test name
Test status
Simulation time	2992005070 ps
CPU time	46.77 seconds
Started	Jul 16 07:44:24 PM PDT 24
Finished	Jul 16 07:45:14 PM PDT 24
Peak memory	202888 kb
Host	smart-4b1f0db2-4861-45cd-8b62-64b5b2f4e1b0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831760715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection. 831760715
Directory	/workspace/40.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/40.sram_ctrl_executable.837250487
Short name	T584
Test name
Test status
Simulation time	1761864901 ps
CPU time	97.85 seconds
Started	Jul 16 07:44:21 PM PDT 24
Finished	Jul 16 07:46:00 PM PDT 24
Peak memory	308976 kb
Host	smart-ac1b305c-00dd-42b7-9fbd-0e28ced61b30
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837250487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executabl e.837250487
Directory	/workspace/40.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/40.sram_ctrl_lc_escalation.2967062683
Short name	T892
Test name
Test status
Simulation time	99372920 ps
CPU time	1.07 seconds
Started	Jul 16 07:44:22 PM PDT 24
Finished	Jul 16 07:44:25 PM PDT 24
Peak memory	202564 kb
Host	smart-cfeec727-0dbb-4dcf-9868-d6c34cab1ec0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967062683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.2967062683
Directory	/workspace/40.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/40.sram_ctrl_max_throughput.1209495436
Short name	T834
Test name
Test status
Simulation time	462761190 ps
CPU time	82.37 seconds
Started	Jul 16 07:44:27 PM PDT 24
Finished	Jul 16 07:45:52 PM PDT 24
Peak memory	353028 kb
Host	smart-7a03995e-4635-457c-b088-02a12fc63cb4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209495436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.1209495436
Directory	/workspace/40.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.2232112719
Short name	T419
Test name
Test status
Simulation time	89469112 ps
CPU time	3.16 seconds
Started	Jul 16 07:44:23 PM PDT 24
Finished	Jul 16 07:44:29 PM PDT 24
Peak memory	211004 kb
Host	smart-bbed8296-23ea-4bd0-a0de-4bbd95ab8ef4
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232112719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.2232112719
Directory	/workspace/40.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_walk.377991593
Short name	T329
Test name
Test status
Simulation time	537952708 ps
CPU time	8.89 seconds
Started	Jul 16 07:44:23 PM PDT 24
Finished	Jul 16 07:44:34 PM PDT 24
Peak memory	211056 kb
Host	smart-b7ada84d-ce59-4c0f-9d52-baab9b1839ea
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377991593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl _mem_walk.377991593
Directory	/workspace/40.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/40.sram_ctrl_multiple_keys.2224023219
Short name	T850
Test name
Test status
Simulation time	31671935862 ps
CPU time	1003.6 seconds
Started	Jul 16 07:44:24 PM PDT 24
Finished	Jul 16 08:01:10 PM PDT 24
Peak memory	371620 kb
Host	smart-fcb0a3a3-5b9f-4145-9954-13f4345ff971
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224023219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.2224023219
Directory	/workspace/40.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access.2127984976
Short name	T802
Test name
Test status
Simulation time	13979691987 ps
CPU time	22.36 seconds
Started	Jul 16 07:44:23 PM PDT 24
Finished	Jul 16 07:44:47 PM PDT 24
Peak memory	202844 kb
Host	smart-3a44f2e1-0a00-4587-ade3-83449019908e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127984976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.2127984976
Directory	/workspace/40.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.284179551
Short name	T280
Test name
Test status
Simulation time	9564237077 ps
CPU time	241.91 seconds
Started	Jul 16 07:44:25 PM PDT 24
Finished	Jul 16 07:48:30 PM PDT 24
Peak memory	202860 kb
Host	smart-f46ab587-ccc5-49ba-afae-e4b3cc947686
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284179551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.sram_ctrl_partial_access_b2b.284179551
Directory	/workspace/40.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/40.sram_ctrl_ram_cfg.4243674413
Short name	T782
Test name
Test status
Simulation time	34360638 ps
CPU time	0.79 seconds
Started	Jul 16 07:44:24 PM PDT 24
Finished	Jul 16 07:44:27 PM PDT 24
Peak memory	202864 kb
Host	smart-73eb3103-59ba-4b84-af40-fef69ee87023
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243674413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.4243674413
Directory	/workspace/40.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/40.sram_ctrl_regwen.3251642176
Short name	T897
Test name
Test status
Simulation time	2297003096 ps
CPU time	222.18 seconds
Started	Jul 16 07:44:22 PM PDT 24
Finished	Jul 16 07:48:05 PM PDT 24
Peak memory	359528 kb
Host	smart-c76275d5-caea-4812-acd1-16de62bac9ef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251642176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3251642176
Directory	/workspace/40.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/40.sram_ctrl_smoke.4225102086
Short name	T316
Test name
Test status
Simulation time	782613630 ps
CPU time	9.15 seconds
Started	Jul 16 07:44:23 PM PDT 24
Finished	Jul 16 07:44:33 PM PDT 24
Peak memory	202804 kb
Host	smart-d4cd201a-819c-4296-898e-b5d99b9183c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225102086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.4225102086
Directory	/workspace/40.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_all.3978142854
Short name	T455
Test name
Test status
Simulation time	78834964463 ps
CPU time	1588.71 seconds
Started	Jul 16 07:44:28 PM PDT 24
Finished	Jul 16 08:10:59 PM PDT 24
Peak memory	379832 kb
Host	smart-3c0d8d4e-b187-4deb-91cb-f7ad2ef15684
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978142854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.3978142854
Directory	/workspace/40.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.4082821161
Short name	T391
Test name
Test status
Simulation time	31156874039 ps
CPU time	323.4 seconds
Started	Jul 16 07:44:27 PM PDT 24
Finished	Jul 16 07:49:52 PM PDT 24
Peak memory	202900 kb
Host	smart-89a340cb-f0c8-43dc-9b96-236030173cab
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082821161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.4082821161
Directory	/workspace/40.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1413813859
Short name	T731
Test name
Test status
Simulation time	586355817 ps
CPU time	58.38 seconds
Started	Jul 16 07:44:25 PM PDT 24
Finished	Jul 16 07:45:27 PM PDT 24
Peak memory	309092 kb
Host	smart-74a2c393-d7f1-4df7-83b1-67e55a1e6bc3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413813859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1413813859
Directory	/workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.2748860886
Short name	T672
Test name
Test status
Simulation time	14255179707 ps
CPU time	1112.76 seconds
Started	Jul 16 07:44:25 PM PDT 24
Finished	Jul 16 08:03:01 PM PDT 24
Peak memory	371476 kb
Host	smart-624313f0-f98f-45f6-a4ba-c3da638667f3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748860886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.2748860886
Directory	/workspace/41.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/41.sram_ctrl_alert_test.2346326963
Short name	T590
Test name
Test status
Simulation time	30893353 ps
CPU time	0.65 seconds
Started	Jul 16 07:44:41 PM PDT 24
Finished	Jul 16 07:44:43 PM PDT 24
Peak memory	202640 kb
Host	smart-8cf584c4-2b05-4575-baba-8d3ffdb16f80
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346326963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2346326963
Directory	/workspace/41.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.sram_ctrl_bijection.2383675218
Short name	T628
Test name
Test status
Simulation time	601095336 ps
CPU time	38.77 seconds
Started	Jul 16 07:44:25 PM PDT 24
Finished	Jul 16 07:45:06 PM PDT 24
Peak memory	202800 kb
Host	smart-876b3744-84f8-47b4-9bdc-9b35487c29cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383675218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .2383675218
Directory	/workspace/41.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/41.sram_ctrl_executable.3037310961
Short name	T372
Test name
Test status
Simulation time	4215089817 ps
CPU time	190.86 seconds
Started	Jul 16 07:44:24 PM PDT 24
Finished	Jul 16 07:47:38 PM PDT 24
Peak memory	367548 kb
Host	smart-7171034e-dc86-4b96-88ce-7dec3fa52bc5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037310961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.3037310961
Directory	/workspace/41.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/41.sram_ctrl_lc_escalation.2818483911
Short name	T789
Test name
Test status
Simulation time	486673699 ps
CPU time	2.14 seconds
Started	Jul 16 07:44:25 PM PDT 24
Finished	Jul 16 07:44:30 PM PDT 24
Peak memory	202812 kb
Host	smart-1195c81b-3167-4c23-8f0a-99242810b8ba
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818483911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.2818483911
Directory	/workspace/41.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/41.sram_ctrl_max_throughput.1474327076
Short name	T213
Test name
Test status
Simulation time	103138483 ps
CPU time	45.26 seconds
Started	Jul 16 07:44:25 PM PDT 24
Finished	Jul 16 07:45:14 PM PDT 24
Peak memory	312896 kb
Host	smart-4864bcc5-8546-4899-a654-7d72e2fbcaf6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474327076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.1474327076
Directory	/workspace/41.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3518384998
Short name	T276
Test name
Test status
Simulation time	972342395 ps
CPU time	5.9 seconds
Started	Jul 16 07:44:40 PM PDT 24
Finished	Jul 16 07:44:48 PM PDT 24
Peak memory	211128 kb
Host	smart-711c592e-9a93-4ad1-a2eb-660416946692
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518384998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.3518384998
Directory	/workspace/41.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_walk.1313222864
Short name	T587
Test name
Test status
Simulation time	204985687 ps
CPU time	10.03 seconds
Started	Jul 16 07:44:42 PM PDT 24
Finished	Jul 16 07:44:53 PM PDT 24
Peak memory	211132 kb
Host	smart-ff9252fe-40b3-4bd6-94eb-ba9caa3df9e9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313222864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.1313222864
Directory	/workspace/41.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/41.sram_ctrl_multiple_keys.1050171624
Short name	T796
Test name
Test status
Simulation time	282339463125 ps
CPU time	1135.02 seconds
Started	Jul 16 07:44:27 PM PDT 24
Finished	Jul 16 08:03:24 PM PDT 24
Peak memory	376068 kb
Host	smart-430a6c36-9068-4dfb-9ed7-d1c86f4ade4c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050171624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.1050171624
Directory	/workspace/41.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access.4253502541
Short name	T381
Test name
Test status
Simulation time	1377170864 ps
CPU time	20.58 seconds
Started	Jul 16 07:44:28 PM PDT 24
Finished	Jul 16 07:44:50 PM PDT 24
Peak memory	265776 kb
Host	smart-1ec50381-c1c9-48fa-bdde-ec00ccd7685a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253502541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.4253502541
Directory	/workspace/41.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1921499296
Short name	T791
Test name
Test status
Simulation time	16327834183 ps
CPU time	305.72 seconds
Started	Jul 16 07:44:22 PM PDT 24
Finished	Jul 16 07:49:28 PM PDT 24
Peak memory	202964 kb
Host	smart-e6f3d4a6-85ef-49e5-ba56-ea3fa1e4092f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921499296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.1921499296
Directory	/workspace/41.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/41.sram_ctrl_ram_cfg.2331940259
Short name	T721
Test name
Test status
Simulation time	87597429 ps
CPU time	0.79 seconds
Started	Jul 16 07:44:43 PM PDT 24
Finished	Jul 16 07:44:45 PM PDT 24
Peak memory	202904 kb
Host	smart-b219fc80-e741-4144-9b36-1232ce3515a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331940259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2331940259
Directory	/workspace/41.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/41.sram_ctrl_regwen.1832890478
Short name	T135
Test name
Test status
Simulation time	2743842570 ps
CPU time	1018.05 seconds
Started	Jul 16 07:44:24 PM PDT 24
Finished	Jul 16 08:01:25 PM PDT 24
Peak memory	370020 kb
Host	smart-f774ea76-10cf-4e00-95aa-c3ba3169d87d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832890478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1832890478
Directory	/workspace/41.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/41.sram_ctrl_smoke.1232199651
Short name	T873
Test name
Test status
Simulation time	628173698 ps
CPU time	9.63 seconds
Started	Jul 16 07:44:26 PM PDT 24
Finished	Jul 16 07:44:38 PM PDT 24
Peak memory	202784 kb
Host	smart-e2f03f01-db2e-4396-bc1a-a9a4511b5da8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232199651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1232199651
Directory	/workspace/41.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all.2404571842
Short name	T640
Test name
Test status
Simulation time	8963355963 ps
CPU time	2002.52 seconds
Started	Jul 16 07:44:42 PM PDT 24
Finished	Jul 16 08:18:06 PM PDT 24
Peak memory	376528 kb
Host	smart-62bef3c2-ab8e-4fa5-83f9-72b1edeefdc8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404571842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.2404571842
Directory	/workspace/41.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.254974493
Short name	T554
Test name
Test status
Simulation time	39276842413 ps
CPU time	201.45 seconds
Started	Jul 16 07:44:23 PM PDT 24
Finished	Jul 16 07:47:46 PM PDT 24
Peak memory	202896 kb
Host	smart-420c3b8c-16fa-4bf6-a71c-388d06c4d47d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254974493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_stress_pipeline.254974493
Directory	/workspace/41.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2685602243
Short name	T880
Test name
Test status
Simulation time	47580977 ps
CPU time	3.02 seconds
Started	Jul 16 07:44:23 PM PDT 24
Finished	Jul 16 07:44:28 PM PDT 24
Peak memory	219176 kb
Host	smart-42a91028-af25-472b-bf68-85c4e046fdfc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685602243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2685602243
Directory	/workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3359796031
Short name	T645
Test name
Test status
Simulation time	23421402397 ps
CPU time	987.76 seconds
Started	Jul 16 07:44:41 PM PDT 24
Finished	Jul 16 08:01:10 PM PDT 24
Peak memory	371944 kb
Host	smart-fe2b5306-e585-4cd6-8500-513646e64308
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359796031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.3359796031
Directory	/workspace/42.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/42.sram_ctrl_alert_test.2954404826
Short name	T405
Test name
Test status
Simulation time	38030213 ps
CPU time	0.66 seconds
Started	Jul 16 07:44:39 PM PDT 24
Finished	Jul 16 07:44:41 PM PDT 24
Peak memory	202540 kb
Host	smart-c597a709-6071-4509-9128-0ca5d8963f3a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954404826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2954404826
Directory	/workspace/42.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.sram_ctrl_bijection.3761858015
Short name	T454
Test name
Test status
Simulation time	849166563 ps
CPU time	27.79 seconds
Started	Jul 16 07:44:40 PM PDT 24
Finished	Jul 16 07:45:09 PM PDT 24
Peak memory	202752 kb
Host	smart-eb71677e-4c98-4820-9c1f-87321b3f8033
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761858015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .3761858015
Directory	/workspace/42.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/42.sram_ctrl_executable.1481275736
Short name	T178
Test name
Test status
Simulation time	5911638042 ps
CPU time	540.84 seconds
Started	Jul 16 07:44:40 PM PDT 24
Finished	Jul 16 07:53:42 PM PDT 24
Peak memory	352188 kb
Host	smart-e11871d0-39ee-4f3e-b832-50575b7610e1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481275736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.1481275736
Directory	/workspace/42.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/42.sram_ctrl_lc_escalation.2146207519
Short name	T403
Test name
Test status
Simulation time	112804023 ps
CPU time	1.67 seconds
Started	Jul 16 07:44:41 PM PDT 24
Finished	Jul 16 07:44:44 PM PDT 24
Peak memory	210980 kb
Host	smart-0b8e6921-3c27-4fbb-b500-50b9264070ec
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146207519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.2146207519
Directory	/workspace/42.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/42.sram_ctrl_max_throughput.2022747594
Short name	T411
Test name
Test status
Simulation time	120823357 ps
CPU time	53.22 seconds
Started	Jul 16 07:44:42 PM PDT 24
Finished	Jul 16 07:45:36 PM PDT 24
Peak memory	325552 kb
Host	smart-fe7d06b5-cb56-43a6-9f60-7eabc1a00228
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022747594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.2022747594
Directory	/workspace/42.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3508756050
Short name	T53
Test name
Test status
Simulation time	1418730744 ps
CPU time	6.17 seconds
Started	Jul 16 07:44:40 PM PDT 24
Finished	Jul 16 07:44:48 PM PDT 24
Peak memory	211076 kb
Host	smart-58cda846-dec2-4755-9d10-8d346cb3ae88
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508756050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.3508756050
Directory	/workspace/42.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_walk.1353705993
Short name	T725
Test name
Test status
Simulation time	756122317 ps
CPU time	9.66 seconds
Started	Jul 16 07:44:41 PM PDT 24
Finished	Jul 16 07:44:52 PM PDT 24
Peak memory	211124 kb
Host	smart-c17ee756-a1ee-415d-9e08-02896a19d1cd
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353705993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.1353705993
Directory	/workspace/42.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/42.sram_ctrl_multiple_keys.2614980087
Short name	T241
Test name
Test status
Simulation time	46280364447 ps
CPU time	948.6 seconds
Started	Jul 16 07:44:38 PM PDT 24
Finished	Jul 16 08:00:28 PM PDT 24
Peak memory	367300 kb
Host	smart-aca37c09-efc8-49df-aca8-4ae8c26d6085
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614980087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.2614980087
Directory	/workspace/42.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access.278799504
Short name	T224
Test name
Test status
Simulation time	270780049 ps
CPU time	13.66 seconds
Started	Jul 16 07:44:38 PM PDT 24
Finished	Jul 16 07:44:52 PM PDT 24
Peak memory	202796 kb
Host	smart-42fb8251-4308-49fc-b85a-1bbd792ee51f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278799504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s ram_ctrl_partial_access.278799504
Directory	/workspace/42.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.214717584
Short name	T488
Test name
Test status
Simulation time	77253732348 ps
CPU time	537.29 seconds
Started	Jul 16 07:44:42 PM PDT 24
Finished	Jul 16 07:53:40 PM PDT 24
Peak memory	202996 kb
Host	smart-e46893f6-0b35-4dbb-b0c7-679726b78831
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214717584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.sram_ctrl_partial_access_b2b.214717584
Directory	/workspace/42.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/42.sram_ctrl_ram_cfg.3309071362
Short name	T583
Test name
Test status
Simulation time	28736517 ps
CPU time	0.78 seconds
Started	Jul 16 07:44:41 PM PDT 24
Finished	Jul 16 07:44:43 PM PDT 24
Peak memory	202884 kb
Host	smart-63e2d5a7-0653-4d01-9f7c-1a5c638a5d06
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309071362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3309071362
Directory	/workspace/42.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/42.sram_ctrl_regwen.423735138
Short name	T819
Test name
Test status
Simulation time	7023494012 ps
CPU time	575.31 seconds
Started	Jul 16 07:44:38 PM PDT 24
Finished	Jul 16 07:54:15 PM PDT 24
Peak memory	365208 kb
Host	smart-2629fd45-6899-4812-9380-684b74ba4b01
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423735138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.423735138
Directory	/workspace/42.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/42.sram_ctrl_smoke.1711111266
Short name	T450
Test name
Test status
Simulation time	7332131621 ps
CPU time	157.85 seconds
Started	Jul 16 07:44:39 PM PDT 24
Finished	Jul 16 07:47:18 PM PDT 24
Peak memory	367508 kb
Host	smart-100908d4-7fd9-4a47-adfa-8e5b958b4fc4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711111266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1711111266
Directory	/workspace/42.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all.2990890431
Short name	T78
Test name
Test status
Simulation time	125259080501 ps
CPU time	1222.45 seconds
Started	Jul 16 07:44:40 PM PDT 24
Finished	Jul 16 08:05:04 PM PDT 24
Peak memory	367576 kb
Host	smart-68db396d-f3b2-44a8-9bed-8836d6337618
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990890431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.2990890431
Directory	/workspace/42.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4041036392
Short name	T862
Test name
Test status
Simulation time	12790418998 ps
CPU time	575.07 seconds
Started	Jul 16 07:44:41 PM PDT 24
Finished	Jul 16 07:54:17 PM PDT 24
Peak memory	355408 kb
Host	smart-271a3a38-1e13-465f-b2f5-6247ea4561cb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4041036392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.4041036392
Directory	/workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1743378682
Short name	T283
Test name
Test status
Simulation time	9310224402 ps
CPU time	160.31 seconds
Started	Jul 16 07:44:39 PM PDT 24
Finished	Jul 16 07:47:21 PM PDT 24
Peak memory	202912 kb
Host	smart-65b6f757-9467-40ef-813d-818575a61a0f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743378682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.1743378682
Directory	/workspace/42.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.162168132
Short name	T925
Test name
Test status
Simulation time	498682562 ps
CPU time	76.65 seconds
Started	Jul 16 07:44:42 PM PDT 24
Finished	Jul 16 07:45:59 PM PDT 24
Peak memory	330600 kb
Host	smart-0a3a8ce6-7255-463d-a070-07c4779a8b54
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162168132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.162168132
Directory	/workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3979822326
Short name	T597
Test name
Test status
Simulation time	3772611220 ps
CPU time	1013.11 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 08:01:53 PM PDT 24
Peak memory	371668 kb
Host	smart-af859137-519b-4b9d-a05a-bcb3a75e75f8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979822326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.3979822326
Directory	/workspace/43.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/43.sram_ctrl_alert_test.591280881
Short name	T692
Test name
Test status
Simulation time	12831256 ps
CPU time	0.69 seconds
Started	Jul 16 07:44:56 PM PDT 24
Finished	Jul 16 07:44:58 PM PDT 24
Peak memory	202652 kb
Host	smart-5315f14e-e28f-4bf7-8880-f2929e88bd1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591280881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.591280881
Directory	/workspace/43.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.sram_ctrl_bijection.134793046
Short name	T793
Test name
Test status
Simulation time	21239757767 ps
CPU time	73.49 seconds
Started	Jul 16 07:44:41 PM PDT 24
Finished	Jul 16 07:45:56 PM PDT 24
Peak memory	202912 kb
Host	smart-dcce7084-0b10-4626-bcc1-cbed147dc4ca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134793046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection. 134793046
Directory	/workspace/43.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/43.sram_ctrl_executable.1652355837
Short name	T205
Test name
Test status
Simulation time	6338579171 ps
CPU time	1132.22 seconds
Started	Jul 16 07:44:56 PM PDT 24
Finished	Jul 16 08:03:50 PM PDT 24
Peak memory	374636 kb
Host	smart-fd618363-c6a1-4723-b35c-7508ca0e8d33
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652355837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.1652355837
Directory	/workspace/43.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/43.sram_ctrl_lc_escalation.2935621655
Short name	T557
Test name
Test status
Simulation time	357980217 ps
CPU time	4.16 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 07:45:04 PM PDT 24
Peak memory	202828 kb
Host	smart-285bfb6a-c2e9-4206-9c6f-554c862b4d9f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935621655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.2935621655
Directory	/workspace/43.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/43.sram_ctrl_max_throughput.2164206625
Short name	T684
Test name
Test status
Simulation time	226321550 ps
CPU time	12.77 seconds
Started	Jul 16 07:44:56 PM PDT 24
Finished	Jul 16 07:45:10 PM PDT 24
Peak memory	252920 kb
Host	smart-236fb31a-8f98-4337-a7ea-d0bcb81e0691
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164206625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.2164206625
Directory	/workspace/43.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1553099015
Short name	T100
Test name
Test status
Simulation time	67864432 ps
CPU time	4.64 seconds
Started	Jul 16 07:44:59 PM PDT 24
Finished	Jul 16 07:45:06 PM PDT 24
Peak memory	211004 kb
Host	smart-ea09d12a-0959-437b-8ff4-8693d9952af3
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553099015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.1553099015
Directory	/workspace/43.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_walk.1398281385
Short name	T883
Test name
Test status
Simulation time	146888364 ps
CPU time	4.34 seconds
Started	Jul 16 07:44:56 PM PDT 24
Finished	Jul 16 07:45:01 PM PDT 24
Peak memory	211048 kb
Host	smart-ed06fa00-40c6-4798-be5c-420a7cf26908
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398281385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.1398281385
Directory	/workspace/43.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/43.sram_ctrl_multiple_keys.3972350444
Short name	T525
Test name
Test status
Simulation time	56058965623 ps
CPU time	952.41 seconds
Started	Jul 16 07:44:40 PM PDT 24
Finished	Jul 16 08:00:33 PM PDT 24
Peak memory	367508 kb
Host	smart-22e71f07-f225-4ee9-b5f3-39b0300999d6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972350444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.3972350444
Directory	/workspace/43.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access.3036853027
Short name	T154
Test name
Test status
Simulation time	420065336 ps
CPU time	16.25 seconds
Started	Jul 16 07:44:41 PM PDT 24
Finished	Jul 16 07:44:58 PM PDT 24
Peak memory	202700 kb
Host	smart-ed50810c-59da-4455-987a-c2964dfa657b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036853027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.3036853027
Directory	/workspace/43.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3896266730
Short name	T761
Test name
Test status
Simulation time	11202653843 ps
CPU time	300.7 seconds
Started	Jul 16 07:44:39 PM PDT 24
Finished	Jul 16 07:49:41 PM PDT 24
Peak memory	202920 kb
Host	smart-46c544af-0422-439e-8ced-9a02726a40dc
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896266730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3896266730
Directory	/workspace/43.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/43.sram_ctrl_ram_cfg.9945249
Short name	T313
Test name
Test status
Simulation time	83262348 ps
CPU time	0.78 seconds
Started	Jul 16 07:44:56 PM PDT 24
Finished	Jul 16 07:44:58 PM PDT 24
Peak memory	202816 kb
Host	smart-eb928b2f-0e5c-4af7-9084-f964f4e8ceb0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9945249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.9945249
Directory	/workspace/43.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/43.sram_ctrl_regwen.1925815609
Short name	T322
Test name
Test status
Simulation time	4084042640 ps
CPU time	409.89 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 07:51:50 PM PDT 24
Peak memory	375336 kb
Host	smart-81dca16f-6f56-4287-8d4f-c61a1775fc36
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925815609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1925815609
Directory	/workspace/43.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/43.sram_ctrl_smoke.37385545
Short name	T619
Test name
Test status
Simulation time	200790561 ps
CPU time	47.13 seconds
Started	Jul 16 07:44:38 PM PDT 24
Finished	Jul 16 07:45:26 PM PDT 24
Peak memory	304284 kb
Host	smart-d8e665aa-985f-4b15-a5e1-d2f294af4b53
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37385545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.37385545
Directory	/workspace/43.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all.1798292206
Short name	T19
Test name
Test status
Simulation time	52546056318 ps
CPU time	2352.37 seconds
Started	Jul 16 07:44:56 PM PDT 24
Finished	Jul 16 08:24:09 PM PDT 24
Peak memory	383372 kb
Host	smart-118ebfad-0608-4513-b063-f83f24b7995c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798292206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.1798292206
Directory	/workspace/43.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2051918436
Short name	T240
Test name
Test status
Simulation time	751299687 ps
CPU time	392.7 seconds
Started	Jul 16 07:45:00 PM PDT 24
Finished	Jul 16 07:51:34 PM PDT 24
Peak memory	379228 kb
Host	smart-37326ee2-e2c6-4441-8cb2-f3d4a8336082
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2051918436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.2051918436
Directory	/workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2797551605
Short name	T739
Test name
Test status
Simulation time	2298821648 ps
CPU time	242.65 seconds
Started	Jul 16 07:44:40 PM PDT 24
Finished	Jul 16 07:48:44 PM PDT 24
Peak memory	202936 kb
Host	smart-2d2e128f-bad1-45f3-acdf-6cc9f871b3b5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797551605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.2797551605
Directory	/workspace/43.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.565711427
Short name	T63
Test name
Test status
Simulation time	121341316 ps
CPU time	34.73 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 07:45:35 PM PDT 24
Peak memory	295680 kb
Host	smart-3ce0b6c4-628f-4448-8aff-01c5ce23b2fb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565711427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_throughput_w_partial_write.565711427
Directory	/workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3289876404
Short name	T496
Test name
Test status
Simulation time	3283628013 ps
CPU time	383.87 seconds
Started	Jul 16 07:44:57 PM PDT 24
Finished	Jul 16 07:51:22 PM PDT 24
Peak memory	364460 kb
Host	smart-e4b8b47e-577e-45c9-9e08-8797de10d2a3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289876404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.3289876404
Directory	/workspace/44.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/44.sram_ctrl_alert_test.2478122116
Short name	T221
Test name
Test status
Simulation time	30875903 ps
CPU time	0.66 seconds
Started	Jul 16 07:45:00 PM PDT 24
Finished	Jul 16 07:45:02 PM PDT 24
Peak memory	202272 kb
Host	smart-23ba3af8-09ab-4c43-9626-1653bb7c3801
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478122116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2478122116
Directory	/workspace/44.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.sram_ctrl_bijection.424966330
Short name	T580
Test name
Test status
Simulation time	30077597731 ps
CPU time	90.66 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 07:46:30 PM PDT 24
Peak memory	202952 kb
Host	smart-468f1748-09e9-4638-9426-a7a9ff1a2a5b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424966330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection. 424966330
Directory	/workspace/44.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/44.sram_ctrl_executable.2142879
Short name	T35
Test name
Test status
Simulation time	2373017226 ps
CPU time	813.43 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 07:58:33 PM PDT 24
Peak memory	367672 kb
Host	smart-3b0b1199-f848-4d57-8b4a-1e53dd395903
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.2142879
Directory	/workspace/44.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/44.sram_ctrl_lc_escalation.4260891582
Short name	T860
Test name
Test status
Simulation time	267644563 ps
CPU time	1.22 seconds
Started	Jul 16 07:45:01 PM PDT 24
Finished	Jul 16 07:45:04 PM PDT 24
Peak memory	213628 kb
Host	smart-d19a4589-8469-4e8f-9d51-3929a69259c4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260891582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.4260891582
Directory	/workspace/44.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/44.sram_ctrl_max_throughput.2400631762
Short name	T161
Test name
Test status
Simulation time	90270364 ps
CPU time	30.08 seconds
Started	Jul 16 07:44:57 PM PDT 24
Finished	Jul 16 07:45:28 PM PDT 24
Peak memory	286672 kb
Host	smart-b00370dd-fc8b-4595-8704-4bed539cf678
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400631762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.2400631762
Directory	/workspace/44.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2869556205
Short name	T615
Test name
Test status
Simulation time	253630087 ps
CPU time	3.34 seconds
Started	Jul 16 07:45:01 PM PDT 24
Finished	Jul 16 07:45:06 PM PDT 24
Peak memory	210932 kb
Host	smart-75360618-4bf5-4235-87af-236fcd03978b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869556205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.2869556205
Directory	/workspace/44.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_walk.1968779941
Short name	T51
Test name
Test status
Simulation time	884983238 ps
CPU time	10.45 seconds
Started	Jul 16 07:45:00 PM PDT 24
Finished	Jul 16 07:45:12 PM PDT 24
Peak memory	202840 kb
Host	smart-83ac3bcd-7f2f-435a-ba46-77adeaa7ffd8
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968779941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1968779941
Directory	/workspace/44.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/44.sram_ctrl_multiple_keys.2790966593
Short name	T397
Test name
Test status
Simulation time	7641811194 ps
CPU time	1754.55 seconds
Started	Jul 16 07:44:56 PM PDT 24
Finished	Jul 16 08:14:13 PM PDT 24
Peak memory	375468 kb
Host	smart-5b2f8724-26d6-4485-9412-9b6da234d31b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790966593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.2790966593
Directory	/workspace/44.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access.2747994856
Short name	T499
Test name
Test status
Simulation time	417671987 ps
CPU time	7.66 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 07:45:08 PM PDT 24
Peak memory	202844 kb
Host	smart-61eec26f-2db9-4b08-81ad-483d8b8b28b7
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747994856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.2747994856
Directory	/workspace/44.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2263615190
Short name	T115
Test name
Test status
Simulation time	36313372435 ps
CPU time	168.61 seconds
Started	Jul 16 07:45:00 PM PDT 24
Finished	Jul 16 07:47:51 PM PDT 24
Peak memory	202944 kb
Host	smart-024fad5d-c066-432c-8d07-e73fc17fe849
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263615190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.2263615190
Directory	/workspace/44.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/44.sram_ctrl_ram_cfg.3027769677
Short name	T912
Test name
Test status
Simulation time	36810598 ps
CPU time	0.8 seconds
Started	Jul 16 07:44:57 PM PDT 24
Finished	Jul 16 07:44:59 PM PDT 24
Peak memory	202840 kb
Host	smart-12bd8062-1508-4578-b76a-175e901298d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027769677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3027769677
Directory	/workspace/44.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/44.sram_ctrl_regwen.3439102986
Short name	T300
Test name
Test status
Simulation time	5154369847 ps
CPU time	118.74 seconds
Started	Jul 16 07:44:57 PM PDT 24
Finished	Jul 16 07:46:57 PM PDT 24
Peak memory	333860 kb
Host	smart-6d4dd722-7716-4213-bce5-4cdebc3d7692
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439102986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3439102986
Directory	/workspace/44.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/44.sram_ctrl_smoke.3961042341
Short name	T176
Test name
Test status
Simulation time	515483391 ps
CPU time	12.46 seconds
Started	Jul 16 07:44:57 PM PDT 24
Finished	Jul 16 07:45:11 PM PDT 24
Peak memory	202676 kb
Host	smart-de62a0d4-3230-4eed-9742-d5a01377d5d3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961042341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3961042341
Directory	/workspace/44.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all.2531107289
Short name	T600
Test name
Test status
Simulation time	185809296321 ps
CPU time	4176.29 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 08:54:37 PM PDT 24
Peak memory	375708 kb
Host	smart-71b49290-04c1-4672-91fd-586485ab95ba
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531107289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.2531107289
Directory	/workspace/44.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2978442916
Short name	T663
Test name
Test status
Simulation time	1217012181 ps
CPU time	114.55 seconds
Started	Jul 16 07:44:59 PM PDT 24
Finished	Jul 16 07:46:55 PM PDT 24
Peak memory	323184 kb
Host	smart-d70797dd-6d30-466b-a318-1e59315c3fbb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2978442916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2978442916
Directory	/workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3821404903
Short name	T616
Test name
Test status
Simulation time	2522793719 ps
CPU time	248.49 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 07:49:08 PM PDT 24
Peak memory	202904 kb
Host	smart-b257fc1f-9e1c-4b50-a925-e958397dbeac
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821404903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.3821404903
Directory	/workspace/44.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4165954282
Short name	T629
Test name
Test status
Simulation time	330365008 ps
CPU time	21.62 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 07:45:21 PM PDT 24
Peak memory	270252 kb
Host	smart-5a312738-5339-418d-8131-83e61fbdc1b3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165954282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.4165954282
Directory	/workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.302452983
Short name	T779
Test name
Test status
Simulation time	8301531317 ps
CPU time	489.46 seconds
Started	Jul 16 07:45:00 PM PDT 24
Finished	Jul 16 07:53:12 PM PDT 24
Peak memory	355256 kb
Host	smart-c82859c8-c25c-45ec-b75d-5bb046d0ca7a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302452983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 45.sram_ctrl_access_during_key_req.302452983
Directory	/workspace/45.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/45.sram_ctrl_alert_test.1032574983
Short name	T15
Test name
Test status
Simulation time	26902747 ps
CPU time	0.65 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:45:37 PM PDT 24
Peak memory	202260 kb
Host	smart-90714f71-eede-4655-9dfe-8133fda3573e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032574983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1032574983
Directory	/workspace/45.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.sram_ctrl_bijection.385538710
Short name	T319
Test name
Test status
Simulation time	806149771 ps
CPU time	17.21 seconds
Started	Jul 16 07:44:59 PM PDT 24
Finished	Jul 16 07:45:18 PM PDT 24
Peak memory	202720 kb
Host	smart-6eff1079-af97-4b75-be66-fbdf370bd1ba
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385538710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection. 385538710
Directory	/workspace/45.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/45.sram_ctrl_executable.3494187070
Short name	T591
Test name
Test status
Simulation time	2524707365 ps
CPU time	734.73 seconds
Started	Jul 16 07:45:01 PM PDT 24
Finished	Jul 16 07:57:17 PM PDT 24
Peak memory	374684 kb
Host	smart-f67c4787-def7-40d8-b058-e6bb114ddd2a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494187070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.3494187070
Directory	/workspace/45.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/45.sram_ctrl_lc_escalation.4205583260
Short name	T828
Test name
Test status
Simulation time	431820506 ps
CPU time	1.67 seconds
Started	Jul 16 07:45:00 PM PDT 24
Finished	Jul 16 07:45:04 PM PDT 24
Peak memory	202728 kb
Host	smart-a0e6a90f-a8ad-46ef-9b50-92fce44a8776
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205583260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.4205583260
Directory	/workspace/45.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/45.sram_ctrl_max_throughput.3361898650
Short name	T191
Test name
Test status
Simulation time	95959073 ps
CPU time	7.72 seconds
Started	Jul 16 07:45:01 PM PDT 24
Finished	Jul 16 07:45:10 PM PDT 24
Peak memory	239092 kb
Host	smart-373dbd51-7a53-4a23-b940-ce4915bb0af1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361898650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.3361898650
Directory	/workspace/45.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2306091292
Short name	T303
Test name
Test status
Simulation time	96987526 ps
CPU time	3.09 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:45:39 PM PDT 24
Peak memory	211020 kb
Host	smart-78ccb73e-6c92-4a80-aab2-ccdcc9596683
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306091292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.2306091292
Directory	/workspace/45.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_walk.303589943
Short name	T621
Test name
Test status
Simulation time	71371822 ps
CPU time	4.67 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:45:40 PM PDT 24
Peak memory	211072 kb
Host	smart-aa6c808f-7bf2-4743-820f-64c778be9529
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303589943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _mem_walk.303589943
Directory	/workspace/45.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/45.sram_ctrl_multiple_keys.1935834639
Short name	T442
Test name
Test status
Simulation time	7779704141 ps
CPU time	1416.68 seconds
Started	Jul 16 07:44:59 PM PDT 24
Finished	Jul 16 08:08:37 PM PDT 24
Peak memory	369468 kb
Host	smart-b68f2212-7e5b-4085-beda-ade4b2e985ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935834639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.1935834639
Directory	/workspace/45.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access.1400043288
Short name	T32
Test name
Test status
Simulation time	1063886415 ps
CPU time	16.24 seconds
Started	Jul 16 07:45:00 PM PDT 24
Finished	Jul 16 07:45:18 PM PDT 24
Peak memory	261552 kb
Host	smart-99146a43-15ca-41c9-9fc8-d83b54fd609e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400043288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.1400043288
Directory	/workspace/45.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3225161871
Short name	T918
Test name
Test status
Simulation time	12042458226 ps
CPU time	232.36 seconds
Started	Jul 16 07:45:01 PM PDT 24
Finished	Jul 16 07:48:55 PM PDT 24
Peak memory	202932 kb
Host	smart-747badba-2b65-492d-8b9a-a663c2210d9e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225161871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.3225161871
Directory	/workspace/45.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/45.sram_ctrl_ram_cfg.2238017913
Short name	T227
Test name
Test status
Simulation time	31298407 ps
CPU time	0.78 seconds
Started	Jul 16 07:45:33 PM PDT 24
Finished	Jul 16 07:45:35 PM PDT 24
Peak memory	202856 kb
Host	smart-48fc3518-984e-44b9-b704-6d651cbd0739
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238017913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2238017913
Directory	/workspace/45.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/45.sram_ctrl_regwen.2603676591
Short name	T422
Test name
Test status
Simulation time	71406792640 ps
CPU time	1398.94 seconds
Started	Jul 16 07:45:00 PM PDT 24
Finished	Jul 16 08:08:21 PM PDT 24
Peak memory	373724 kb
Host	smart-e21c7ef5-82bc-4d6a-9f36-37ccf4211bc4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603676591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2603676591
Directory	/workspace/45.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/45.sram_ctrl_smoke.1283685307
Short name	T346
Test name
Test status
Simulation time	1465085866 ps
CPU time	7.92 seconds
Started	Jul 16 07:44:58 PM PDT 24
Finished	Jul 16 07:45:08 PM PDT 24
Peak memory	202788 kb
Host	smart-415535b8-5fc6-498b-972f-b8ca41e81981
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283685307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1283685307
Directory	/workspace/45.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all.1784718433
Short name	T697
Test name
Test status
Simulation time	29938134947 ps
CPU time	2848.34 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 08:33:06 PM PDT 24
Peak memory	375816 kb
Host	smart-fdde7dbb-bbdb-4f79-b81e-9308cb8477ba
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784718433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.1784718433
Directory	/workspace/45.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.4085448714
Short name	T659
Test name
Test status
Simulation time	23437008949 ps
CPU time	296.23 seconds
Started	Jul 16 07:44:59 PM PDT 24
Finished	Jul 16 07:49:57 PM PDT 24
Peak memory	202940 kb
Host	smart-64498a12-5300-4d2d-a4c4-d013d4b8d09d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085448714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.4085448714
Directory	/workspace/45.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4101484816
Short name	T812
Test name
Test status
Simulation time	125147029 ps
CPU time	73.06 seconds
Started	Jul 16 07:45:01 PM PDT 24
Finished	Jul 16 07:46:16 PM PDT 24
Peak memory	331520 kb
Host	smart-462e6c1c-186b-4ea9-b94a-c32f9cc50594
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101484816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.4101484816
Directory	/workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1439526105
Short name	T350
Test name
Test status
Simulation time	9794096228 ps
CPU time	78.01 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:46:54 PM PDT 24
Peak memory	318900 kb
Host	smart-1d5ada24-b4ae-4a4d-be49-9d46019177e1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439526105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.1439526105
Directory	/workspace/46.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/46.sram_ctrl_alert_test.2643282949
Short name	T831
Test name
Test status
Simulation time	23989280 ps
CPU time	0.67 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:45:37 PM PDT 24
Peak memory	202580 kb
Host	smart-8072aff0-909a-4068-8e85-ce4716e8f92b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643282949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2643282949
Directory	/workspace/46.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.sram_ctrl_bijection.528978761
Short name	T920
Test name
Test status
Simulation time	2812176502 ps
CPU time	63.23 seconds
Started	Jul 16 07:45:33 PM PDT 24
Finished	Jul 16 07:46:37 PM PDT 24
Peak memory	203000 kb
Host	smart-c63f83dd-b8ac-46bf-89cd-5d8d9afa7bd3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528978761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection. 528978761
Directory	/workspace/46.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/46.sram_ctrl_executable.1616623190
Short name	T62
Test name
Test status
Simulation time	17019434720 ps
CPU time	1038.7 seconds
Started	Jul 16 07:45:33 PM PDT 24
Finished	Jul 16 08:02:53 PM PDT 24
Peak memory	352696 kb
Host	smart-b0bede3c-aa42-4c7a-8a8f-6a50283c31e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616623190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.1616623190
Directory	/workspace/46.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/46.sram_ctrl_lc_escalation.1248937807
Short name	T433
Test name
Test status
Simulation time	590674703 ps
CPU time	7.42 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 07:45:44 PM PDT 24
Peak memory	202800 kb
Host	smart-5d7371c5-dde5-4511-8229-996e7da4a973
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248937807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.1248937807
Directory	/workspace/46.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/46.sram_ctrl_max_throughput.2070778852
Short name	T207
Test name
Test status
Simulation time	519456596 ps
CPU time	116.89 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 07:47:34 PM PDT 24
Peak memory	362796 kb
Host	smart-d3fbfa95-d1f3-41c2-942f-1efad6f85207
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070778852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.2070778852
Directory	/workspace/46.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2506989558
Short name	T312
Test name
Test status
Simulation time	291481198 ps
CPU time	3.06 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:45:38 PM PDT 24
Peak memory	211032 kb
Host	smart-be92e594-ad39-48f7-b05f-29e7871e6eb4
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506989558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.2506989558
Directory	/workspace/46.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_walk.1095869239
Short name	T508
Test name
Test status
Simulation time	438974102 ps
CPU time	9.76 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 07:45:47 PM PDT 24
Peak memory	211012 kb
Host	smart-3908b023-275b-4841-ae67-24a05924ec0e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095869239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.1095869239
Directory	/workspace/46.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/46.sram_ctrl_multiple_keys.958724717
Short name	T39
Test name
Test status
Simulation time	26567543402 ps
CPU time	1518.44 seconds
Started	Jul 16 07:45:33 PM PDT 24
Finished	Jul 16 08:10:52 PM PDT 24
Peak memory	376440 kb
Host	smart-79398ead-303f-432c-b99a-0fa358ed0134
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958724717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip le_keys.958724717
Directory	/workspace/46.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access.565813605
Short name	T671
Test name
Test status
Simulation time	422673823 ps
CPU time	3.66 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 07:45:41 PM PDT 24
Peak memory	215320 kb
Host	smart-eb547c29-f252-40dc-8578-826c2ed70829
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565813605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s ram_ctrl_partial_access.565813605
Directory	/workspace/46.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2742720284
Short name	T138
Test name
Test status
Simulation time	6392330540 ps
CPU time	153.76 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 07:48:11 PM PDT 24
Peak memory	202904 kb
Host	smart-b4537cb8-c785-42ee-af3c-ac73346fe8ed
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742720284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.2742720284
Directory	/workspace/46.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/46.sram_ctrl_ram_cfg.2189663064
Short name	T371
Test name
Test status
Simulation time	31915547 ps
CPU time	0.78 seconds
Started	Jul 16 07:45:36 PM PDT 24
Finished	Jul 16 07:45:39 PM PDT 24
Peak memory	202884 kb
Host	smart-369f8720-2a9d-412b-ad4d-c7afd1222486
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189663064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2189663064
Directory	/workspace/46.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/46.sram_ctrl_regwen.586754592
Short name	T928
Test name
Test status
Simulation time	8169016104 ps
CPU time	579.43 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 07:55:17 PM PDT 24
Peak memory	365112 kb
Host	smart-0315c0d2-7935-4ee6-a106-d13a3f61dad1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586754592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.586754592
Directory	/workspace/46.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/46.sram_ctrl_smoke.3882352747
Short name	T449
Test name
Test status
Simulation time	131134067 ps
CPU time	119.1 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 07:47:36 PM PDT 24
Peak memory	357932 kb
Host	smart-7fee74f4-bb98-40e9-b4a7-0775ef9d73f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882352747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3882352747
Directory	/workspace/46.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_all.1935416768
Short name	T20
Test name
Test status
Simulation time	49610305883 ps
CPU time	4288.95 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 08:57:05 PM PDT 24
Peak memory	375016 kb
Host	smart-ba2f8e33-efb6-4ee3-a821-14dc24093355
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935416768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.1935416768
Directory	/workspace/46.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1621678691
Short name	T781
Test name
Test status
Simulation time	3473012512 ps
CPU time	322.91 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:50:59 PM PDT 24
Peak memory	373800 kb
Host	smart-a765cbe7-2e7f-42d4-9064-29f2c3978d50
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1621678691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1621678691
Directory	/workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3338615983
Short name	T934
Test name
Test status
Simulation time	2643579464 ps
CPU time	271.52 seconds
Started	Jul 16 07:45:32 PM PDT 24
Finished	Jul 16 07:50:05 PM PDT 24
Peak memory	202932 kb
Host	smart-eb21f6f7-5d71-4dee-94ca-9ffde13fd199
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338615983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.3338615983
Directory	/workspace/46.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3273389390
Short name	T836
Test name
Test status
Simulation time	346299578 ps
CPU time	23.65 seconds
Started	Jul 16 07:45:32 PM PDT 24
Finished	Jul 16 07:45:56 PM PDT 24
Peak memory	277008 kb
Host	smart-70ce6265-c669-46b7-93fc-a5d94e617fbf
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273389390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3273389390
Directory	/workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2076192639
Short name	T598
Test name
Test status
Simulation time	2376351905 ps
CPU time	681.28 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 07:56:58 PM PDT 24
Peak memory	370320 kb
Host	smart-99b482d7-2ad9-40e4-8d81-d4ed9c87c77f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076192639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.2076192639
Directory	/workspace/47.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/47.sram_ctrl_alert_test.2428748535
Short name	T13
Test name
Test status
Simulation time	38667959 ps
CPU time	0.66 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:45:37 PM PDT 24
Peak memory	202564 kb
Host	smart-10c2a330-d4c1-44e4-87a5-41e7a5690141
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428748535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.2428748535
Directory	/workspace/47.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.sram_ctrl_bijection.2359744044
Short name	T458
Test name
Test status
Simulation time	6643215389 ps
CPU time	69.73 seconds
Started	Jul 16 07:45:36 PM PDT 24
Finished	Jul 16 07:46:48 PM PDT 24
Peak memory	202912 kb
Host	smart-17bfffa5-ce4b-4ec3-bd4a-1a852453f457
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359744044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .2359744044
Directory	/workspace/47.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/47.sram_ctrl_executable.1408246383
Short name	T308
Test name
Test status
Simulation time	41721781405 ps
CPU time	849.96 seconds
Started	Jul 16 07:45:33 PM PDT 24
Finished	Jul 16 07:59:45 PM PDT 24
Peak memory	374276 kb
Host	smart-d89408e0-47b9-4e43-a256-1dd4cdce9a74
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408246383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.1408246383
Directory	/workspace/47.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/47.sram_ctrl_lc_escalation.1607885834
Short name	T231
Test name
Test status
Simulation time	325847572 ps
CPU time	3.83 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:45:39 PM PDT 24
Peak memory	211028 kb
Host	smart-68340633-6ea6-4879-b729-05aade9785c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607885834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.1607885834
Directory	/workspace/47.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/47.sram_ctrl_max_throughput.713185053
Short name	T582
Test name
Test status
Simulation time	63339307 ps
CPU time	3.43 seconds
Started	Jul 16 07:45:32 PM PDT 24
Finished	Jul 16 07:45:37 PM PDT 24
Peak memory	219236 kb
Host	smart-9e53f852-7590-4d38-b5c9-34cbce627ece
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713185053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.sram_ctrl_max_throughput.713185053
Directory	/workspace/47.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.840854038
Short name	T66
Test name
Test status
Simulation time	197483826 ps
CPU time	5.03 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:45:41 PM PDT 24
Peak memory	210968 kb
Host	smart-ce54595b-d1cc-44d9-8b91-f1c7a2283144
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840854038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_mem_partial_access.840854038
Directory	/workspace/47.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_walk.3321577889
Short name	T380
Test name
Test status
Simulation time	9295626453 ps
CPU time	12.05 seconds
Started	Jul 16 07:45:33 PM PDT 24
Finished	Jul 16 07:45:46 PM PDT 24
Peak memory	211180 kb
Host	smart-720fc0f8-8414-44f5-bc30-2841bdd66fd2
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321577889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.3321577889
Directory	/workspace/47.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/47.sram_ctrl_multiple_keys.1492524345
Short name	T876
Test name
Test status
Simulation time	14820062251 ps
CPU time	935.37 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 08:01:12 PM PDT 24
Peak memory	375744 kb
Host	smart-b23f44e0-85f3-4364-8ea8-c4321a778aaf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492524345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.1492524345
Directory	/workspace/47.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access.1462179161
Short name	T395
Test name
Test status
Simulation time	175682091 ps
CPU time	18.05 seconds
Started	Jul 16 07:45:33 PM PDT 24
Finished	Jul 16 07:45:53 PM PDT 24
Peak memory	258568 kb
Host	smart-a111c2a7-c1c7-4f9a-9671-9efcaf3c8b15
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462179161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.1462179161
Directory	/workspace/47.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3415992255
Short name	T392
Test name
Test status
Simulation time	27823612991 ps
CPU time	361.89 seconds
Started	Jul 16 07:45:34 PM PDT 24
Finished	Jul 16 07:51:38 PM PDT 24
Peak memory	202944 kb
Host	smart-a7cf9650-a800-4827-b37c-127c968c4a49
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415992255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.3415992255
Directory	/workspace/47.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/47.sram_ctrl_regwen.1373153157
Short name	T704
Test name
Test status
Simulation time	858809924 ps
CPU time	32.71 seconds
Started	Jul 16 07:45:36 PM PDT 24
Finished	Jul 16 07:46:11 PM PDT 24
Peak memory	242604 kb
Host	smart-eb7519d9-d231-4a69-8707-5e704149cd65
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373153157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.1373153157
Directory	/workspace/47.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/47.sram_ctrl_smoke.458975676
Short name	T479
Test name
Test status
Simulation time	304844052 ps
CPU time	2.24 seconds
Started	Jul 16 07:45:35 PM PDT 24
Finished	Jul 16 07:45:40 PM PDT 24
Peak memory	204916 kb
Host	smart-a9c1f330-7760-402d-85b5-37de3ecbc497
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458975676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.458975676
Directory	/workspace/47.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all.3261031428
Short name	T910
Test name
Test status
Simulation time	10687736334 ps
CPU time	1945.71 seconds
Started	Jul 16 07:45:32 PM PDT 24
Finished	Jul 16 08:17:59 PM PDT 24
Peak memory	374716 kb
Host	smart-c51cbd72-51d8-4e11-b1d7-b62863094c53
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261031428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.3261031428
Directory	/workspace/47.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1635961778
Short name	T681
Test name
Test status
Simulation time	8845726748 ps
CPU time	389.82 seconds
Started	Jul 16 07:45:37 PM PDT 24
Finished	Jul 16 07:52:08 PM PDT 24
Peak memory	378876 kb
Host	smart-5b823a3c-76a4-459c-96ad-a71603e338d8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1635961778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1635961778
Directory	/workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3594890251
Short name	T116
Test name
Test status
Simulation time	2777873918 ps
CPU time	252.22 seconds
Started	Jul 16 07:45:33 PM PDT 24
Finished	Jul 16 07:49:47 PM PDT 24
Peak memory	202940 kb
Host	smart-39ffce22-fff1-4d11-8a2d-8adcb2565563
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594890251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.3594890251
Directory	/workspace/47.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1276586492
Short name	T777
Test name
Test status
Simulation time	101217999 ps
CPU time	2.49 seconds
Started	Jul 16 07:45:33 PM PDT 24
Finished	Jul 16 07:45:37 PM PDT 24
Peak memory	217612 kb
Host	smart-d0f48cc1-8b03-4e42-9b22-2f2b4b38b866
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276586492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1276586492
Directory	/workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2485563891
Short name	T917
Test name
Test status
Simulation time	6408492066 ps
CPU time	1055.35 seconds
Started	Jul 16 07:46:22 PM PDT 24
Finished	Jul 16 08:04:02 PM PDT 24
Peak memory	374356 kb
Host	smart-3cf8ec22-80e7-4243-a178-1111f7d3be2b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485563891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.2485563891
Directory	/workspace/48.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/48.sram_ctrl_alert_test.2430384046
Short name	T12
Test name
Test status
Simulation time	17863149 ps
CPU time	0.66 seconds
Started	Jul 16 07:46:19 PM PDT 24
Finished	Jul 16 07:46:21 PM PDT 24
Peak memory	202640 kb
Host	smart-e1e26215-2eb0-4400-abf2-cc52049c7619
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430384046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.2430384046
Directory	/workspace/48.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.sram_ctrl_bijection.3731579709
Short name	T222
Test name
Test status
Simulation time	4462634487 ps
CPU time	81.23 seconds
Started	Jul 16 07:46:19 PM PDT 24
Finished	Jul 16 07:47:43 PM PDT 24
Peak memory	202820 kb
Host	smart-99c0cc92-683c-4663-bf75-27223ac4bd52
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731579709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .3731579709
Directory	/workspace/48.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/48.sram_ctrl_executable.2252058315
Short name	T90
Test name
Test status
Simulation time	65363661103 ps
CPU time	1219.04 seconds
Started	Jul 16 07:46:20 PM PDT 24
Finished	Jul 16 08:06:41 PM PDT 24
Peak memory	374500 kb
Host	smart-cf8d3c23-b620-4943-934b-2e3ea918d4ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252058315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2252058315
Directory	/workspace/48.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/48.sram_ctrl_lc_escalation.4184334935
Short name	T643
Test name
Test status
Simulation time	411637507 ps
CPU time	4.45 seconds
Started	Jul 16 07:46:18 PM PDT 24
Finished	Jul 16 07:46:24 PM PDT 24
Peak memory	202824 kb
Host	smart-fdc2ad92-bf6e-4aeb-9580-f1962eda302b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184334935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.4184334935
Directory	/workspace/48.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/48.sram_ctrl_max_throughput.3788537536
Short name	T872
Test name
Test status
Simulation time	111598072 ps
CPU time	26.94 seconds
Started	Jul 16 07:46:19 PM PDT 24
Finished	Jul 16 07:46:49 PM PDT 24
Peak memory	289696 kb
Host	smart-c1e3f926-277f-45be-aee9-a00947c510db
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788537536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.3788537536
Directory	/workspace/48.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2196356797
Short name	T857
Test name
Test status
Simulation time	202405786 ps
CPU time	5.98 seconds
Started	Jul 16 07:46:20 PM PDT 24
Finished	Jul 16 07:46:28 PM PDT 24
Peak memory	211076 kb
Host	smart-41e72058-302f-4a69-8072-f936f817e612
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196356797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.2196356797
Directory	/workspace/48.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_walk.2869759967
Short name	T824
Test name
Test status
Simulation time	1641856757 ps
CPU time	11.29 seconds
Started	Jul 16 07:46:21 PM PDT 24
Finished	Jul 16 07:46:36 PM PDT 24
Peak memory	211028 kb
Host	smart-0424665b-25a0-4491-a778-10c790f92d8f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869759967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.2869759967
Directory	/workspace/48.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/48.sram_ctrl_multiple_keys.3409525973
Short name	T149
Test name
Test status
Simulation time	18430704806 ps
CPU time	601.66 seconds
Started	Jul 16 07:46:18 PM PDT 24
Finished	Jul 16 07:56:20 PM PDT 24
Peak memory	375820 kb
Host	smart-f7378412-1fa7-41b2-ae47-d1535b5f1d3c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409525973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.3409525973
Directory	/workspace/48.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access.1340340731
Short name	T185
Test name
Test status
Simulation time	408982382 ps
CPU time	4.33 seconds
Started	Jul 16 07:46:20 PM PDT 24
Finished	Jul 16 07:46:27 PM PDT 24
Peak memory	212056 kb
Host	smart-531d306e-2593-485e-b970-5fc8940bd67c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340340731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1340340731
Directory	/workspace/48.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2308223764
Short name	T895
Test name
Test status
Simulation time	9521076425 ps
CPU time	242.45 seconds
Started	Jul 16 07:46:18 PM PDT 24
Finished	Jul 16 07:50:22 PM PDT 24
Peak memory	202876 kb
Host	smart-05ba4f31-eeaf-494d-abc7-1ebe9dd3aa3d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308223764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.2308223764
Directory	/workspace/48.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/48.sram_ctrl_ram_cfg.1431680085
Short name	T439
Test name
Test status
Simulation time	50665347 ps
CPU time	0.75 seconds
Started	Jul 16 07:46:21 PM PDT 24
Finished	Jul 16 07:46:25 PM PDT 24
Peak memory	202852 kb
Host	smart-4d1135c2-eee2-4091-be51-0611ee219f31
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431680085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1431680085
Directory	/workspace/48.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/48.sram_ctrl_regwen.3559555513
Short name	T794
Test name
Test status
Simulation time	18486676994 ps
CPU time	333.85 seconds
Started	Jul 16 07:46:21 PM PDT 24
Finished	Jul 16 07:51:58 PM PDT 24
Peak memory	350644 kb
Host	smart-57506f3f-bdc1-4f01-b8e3-ca459efcf938
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559555513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3559555513
Directory	/workspace/48.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/48.sram_ctrl_smoke.1473340801
Short name	T769
Test name
Test status
Simulation time	148594934 ps
CPU time	138.84 seconds
Started	Jul 16 07:46:21 PM PDT 24
Finished	Jul 16 07:48:44 PM PDT 24
Peak memory	367224 kb
Host	smart-7e74db17-f7c3-4621-bea9-e4e14c949598
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473340801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1473340801
Directory	/workspace/48.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1849163124
Short name	T354
Test name
Test status
Simulation time	944258702 ps
CPU time	423.14 seconds
Started	Jul 16 07:46:20 PM PDT 24
Finished	Jul 16 07:53:25 PM PDT 24
Peak memory	369048 kb
Host	smart-2c327485-8313-4ff9-907c-03618bcc6e8d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1849163124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1849163124
Directory	/workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1921344942
Short name	T274
Test name
Test status
Simulation time	11466417747 ps
CPU time	293.11 seconds
Started	Jul 16 07:46:23 PM PDT 24
Finished	Jul 16 07:51:20 PM PDT 24
Peak memory	202828 kb
Host	smart-340853c2-9349-4f55-beee-5130c4e03b22
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921344942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1921344942
Directory	/workspace/48.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2980993812
Short name	T119
Test name
Test status
Simulation time	161457911 ps
CPU time	153.92 seconds
Started	Jul 16 07:46:17 PM PDT 24
Finished	Jul 16 07:48:52 PM PDT 24
Peak memory	369336 kb
Host	smart-198b5092-6d34-4464-beb3-aa8acc0428b6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980993812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.2980993812
Directory	/workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/49.sram_ctrl_access_during_key_req.198626322
Short name	T447
Test name
Test status
Simulation time	3021628582 ps
CPU time	972.37 seconds
Started	Jul 16 07:46:18 PM PDT 24
Finished	Jul 16 08:02:32 PM PDT 24
Peak memory	374412 kb
Host	smart-7d37c1ca-aa5f-4c67-b3e0-71b9e50606d3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198626322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 49.sram_ctrl_access_during_key_req.198626322
Directory	/workspace/49.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/49.sram_ctrl_alert_test.648300399
Short name	T278
Test name
Test status
Simulation time	25405157 ps
CPU time	0.64 seconds
Started	Jul 16 07:46:21 PM PDT 24
Finished	Jul 16 07:46:25 PM PDT 24
Peak memory	202640 kb
Host	smart-24737667-93f8-471f-abea-152e00ebc263
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648300399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.648300399
Directory	/workspace/49.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.sram_ctrl_bijection.153574890
Short name	T362
Test name
Test status
Simulation time	14633888736 ps
CPU time	25.47 seconds
Started	Jul 16 07:46:22 PM PDT 24
Finished	Jul 16 07:46:52 PM PDT 24
Peak memory	202860 kb
Host	smart-b2e178ed-8d77-43b6-a0eb-2e84bcd628a2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153574890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection. 153574890
Directory	/workspace/49.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/49.sram_ctrl_executable.4004300006
Short name	T915
Test name
Test status
Simulation time	2312501547 ps
CPU time	99.98 seconds
Started	Jul 16 07:46:19 PM PDT 24
Finished	Jul 16 07:48:01 PM PDT 24
Peak memory	321436 kb
Host	smart-f7ccc594-b55f-447b-a698-6147ad2c894c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004300006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.4004300006
Directory	/workspace/49.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/49.sram_ctrl_lc_escalation.3774227591
Short name	T4
Test name
Test status
Simulation time	60615077 ps
CPU time	0.94 seconds
Started	Jul 16 07:46:18 PM PDT 24
Finished	Jul 16 07:46:21 PM PDT 24
Peak memory	202608 kb
Host	smart-f1323f80-aeed-48c9-9dc4-0084644d1cc3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774227591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.3774227591
Directory	/workspace/49.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/49.sram_ctrl_max_throughput.1585535375
Short name	T348
Test name
Test status
Simulation time	112790214 ps
CPU time	26.63 seconds
Started	Jul 16 07:46:19 PM PDT 24
Finished	Jul 16 07:46:47 PM PDT 24
Peak memory	280284 kb
Host	smart-cec68833-5f53-4783-ab96-dedcece17692
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585535375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.1585535375
Directory	/workspace/49.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2440020067
Short name	T567
Test name
Test status
Simulation time	188155395 ps
CPU time	2.94 seconds
Started	Jul 16 07:46:18 PM PDT 24
Finished	Jul 16 07:46:22 PM PDT 24
Peak memory	211060 kb
Host	smart-0294841f-63a9-4fbe-9374-49708ded0612
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440020067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.2440020067
Directory	/workspace/49.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_walk.3822389016
Short name	T223
Test name
Test status
Simulation time	104858485 ps
CPU time	5.26 seconds
Started	Jul 16 07:46:22 PM PDT 24
Finished	Jul 16 07:46:32 PM PDT 24
Peak memory	211112 kb
Host	smart-5c352a11-5eb3-43c0-88b5-7a447e4a076e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822389016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.3822389016
Directory	/workspace/49.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/49.sram_ctrl_multiple_keys.475020689
Short name	T829
Test name
Test status
Simulation time	12483398141 ps
CPU time	809.2 seconds
Started	Jul 16 07:46:18 PM PDT 24
Finished	Jul 16 07:59:48 PM PDT 24
Peak memory	371892 kb
Host	smart-7cfe0ea4-52a6-430e-a114-37a458017291
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475020689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip le_keys.475020689
Directory	/workspace/49.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access.1581710681
Short name	T722
Test name
Test status
Simulation time	625324074 ps
CPU time	11.57 seconds
Started	Jul 16 07:46:20 PM PDT 24
Finished	Jul 16 07:46:34 PM PDT 24
Peak memory	202788 kb
Host	smart-675ca8e0-20fe-474a-b3d7-a2b129301e8c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581710681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.1581710681
Directory	/workspace/49.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.207628772
Short name	T555
Test name
Test status
Simulation time	9751880277 ps
CPU time	208.11 seconds
Started	Jul 16 07:46:19 PM PDT 24
Finished	Jul 16 07:49:49 PM PDT 24
Peak memory	202876 kb
Host	smart-c9f6d767-e346-4d39-a434-4bb95fd270b4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207628772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.sram_ctrl_partial_access_b2b.207628772
Directory	/workspace/49.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/49.sram_ctrl_ram_cfg.4058029018
Short name	T678
Test name
Test status
Simulation time	49385837 ps
CPU time	0.76 seconds
Started	Jul 16 07:46:21 PM PDT 24
Finished	Jul 16 07:46:26 PM PDT 24
Peak memory	202868 kb
Host	smart-a617f803-3a45-4585-ab6b-5a31f27f60a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058029018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.4058029018
Directory	/workspace/49.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/49.sram_ctrl_regwen.765341530
Short name	T764
Test name
Test status
Simulation time	4835719660 ps
CPU time	537.2 seconds
Started	Jul 16 07:46:20 PM PDT 24
Finished	Jul 16 07:55:20 PM PDT 24
Peak memory	359396 kb
Host	smart-1e2818e8-18d0-4f3b-b325-209db4a3e51a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765341530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.765341530
Directory	/workspace/49.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/49.sram_ctrl_smoke.3977876953
Short name	T757
Test name
Test status
Simulation time	3010478021 ps
CPU time	170.21 seconds
Started	Jul 16 07:46:21 PM PDT 24
Finished	Jul 16 07:49:14 PM PDT 24
Peak memory	365980 kb
Host	smart-d35298b0-71c5-40d7-a148-3b1bb7e7d5ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977876953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3977876953
Directory	/workspace/49.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all.972566536
Short name	T676
Test name
Test status
Simulation time	8581788148 ps
CPU time	2868.04 seconds
Started	Jul 16 07:46:18 PM PDT 24
Finished	Jul 16 08:34:07 PM PDT 24
Peak memory	374660 kb
Host	smart-c056b945-64ad-45fc-a346-9e79571d7cbb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972566536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_stress_all.972566536
Directory	/workspace/49.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2898267885
Short name	T48
Test name
Test status
Simulation time	4570651844 ps
CPU time	92.01 seconds
Started	Jul 16 07:46:22 PM PDT 24
Finished	Jul 16 07:47:58 PM PDT 24
Peak memory	311064 kb
Host	smart-4b4496d5-708d-4991-84b1-8415ba879cba
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2898267885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.2898267885
Directory	/workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1774720197
Short name	T291
Test name
Test status
Simulation time	3308680091 ps
CPU time	326.78 seconds
Started	Jul 16 07:46:19 PM PDT 24
Finished	Jul 16 07:51:48 PM PDT 24
Peak memory	203008 kb
Host	smart-4d68fc32-5130-41c1-934b-6f6fdaafee4f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774720197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.1774720197
Directory	/workspace/49.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3244359997
Short name	T706
Test name
Test status
Simulation time	172360005 ps
CPU time	117.26 seconds
Started	Jul 16 07:46:21 PM PDT 24
Finished	Jul 16 07:48:22 PM PDT 24
Peak memory	369312 kb
Host	smart-f70fb955-235c-4d02-8aee-4d92062498d8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244359997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.3244359997
Directory	/workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3981054471
Short name	T896
Test name
Test status
Simulation time	12122450286 ps
CPU time	1947.08 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 08:14:12 PM PDT 24
Peak memory	372740 kb
Host	smart-132ae18e-c7bb-4350-9a68-d3d62f7960d3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981054471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.3981054471
Directory	/workspace/5.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/5.sram_ctrl_alert_test.479673895
Short name	T720
Test name
Test status
Simulation time	124180587 ps
CPU time	0.69 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:45 PM PDT 24
Peak memory	202600 kb
Host	smart-36a93bb0-180e-452b-87e1-27f7c67f2984
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479673895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.479673895
Directory	/workspace/5.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.sram_ctrl_bijection.2600455119
Short name	T453
Test name
Test status
Simulation time	10407005183 ps
CPU time	81.69 seconds
Started	Jul 16 07:41:20 PM PDT 24
Finished	Jul 16 07:43:03 PM PDT 24
Peak memory	202940 kb
Host	smart-88102255-29e4-4bda-9275-32c39363367c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600455119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 2600455119
Directory	/workspace/5.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/5.sram_ctrl_executable.4031807932
Short name	T408
Test name
Test status
Simulation time	80196748646 ps
CPU time	1194.91 seconds
Started	Jul 16 07:41:21 PM PDT 24
Finished	Jul 16 08:01:36 PM PDT 24
Peak memory	375728 kb
Host	smart-927f1117-8a84-4cde-91a1-8d0b7fd2f757
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031807932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.4031807932
Directory	/workspace/5.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/5.sram_ctrl_lc_escalation.1625231284
Short name	T390
Test name
Test status
Simulation time	2912550982 ps
CPU time	6.98 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 07:41:49 PM PDT 24
Peak memory	202928 kb
Host	smart-a019de51-2ee7-4c08-94e3-659c819ebea7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625231284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.1625231284
Directory	/workspace/5.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/5.sram_ctrl_max_throughput.149163517
Short name	T878
Test name
Test status
Simulation time	264273219 ps
CPU time	117.31 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:43:42 PM PDT 24
Peak memory	369416 kb
Host	smart-fa84863d-fa87-4c54-bd37-ed62cf774e52
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149163517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_max_throughput.149163517
Directory	/workspace/5.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2457607237
Short name	T715
Test name
Test status
Simulation time	61548029 ps
CPU time	2.72 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:41:49 PM PDT 24
Peak memory	211044 kb
Host	smart-350b61cf-decf-48f0-a1ce-496c85bc2b2c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457607237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.2457607237
Directory	/workspace/5.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_walk.3763012266
Short name	T347
Test name
Test status
Simulation time	1682903588 ps
CPU time	6.36 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:51 PM PDT 24
Peak memory	211132 kb
Host	smart-672f4ddd-a9d0-41f9-8207-6a3e8ea4267e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763012266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.3763012266
Directory	/workspace/5.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/5.sram_ctrl_multiple_keys.1603032028
Short name	T905
Test name
Test status
Simulation time	11823904768 ps
CPU time	1040.62 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:59:05 PM PDT 24
Peak memory	373648 kb
Host	smart-78c45762-0f7c-4b5b-ab42-9216fa5d5d44
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603032028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.1603032028
Directory	/workspace/5.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access.160935456
Short name	T695
Test name
Test status
Simulation time	124713361 ps
CPU time	4.47 seconds
Started	Jul 16 07:41:19 PM PDT 24
Finished	Jul 16 07:41:44 PM PDT 24
Peak memory	202824 kb
Host	smart-42551882-b828-44bb-9674-369982890e17
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160935456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr am_ctrl_partial_access.160935456
Directory	/workspace/5.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3953847191
Short name	T858
Test name
Test status
Simulation time	61605938967 ps
CPU time	416.18 seconds
Started	Jul 16 07:41:20 PM PDT 24
Finished	Jul 16 07:48:37 PM PDT 24
Peak memory	202988 kb
Host	smart-fcfe48bc-3b8e-459c-bf12-5f6ad6119f98
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953847191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.3953847191
Directory	/workspace/5.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/5.sram_ctrl_ram_cfg.3374852109
Short name	T36
Test name
Test status
Simulation time	55729100 ps
CPU time	0.78 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:46 PM PDT 24
Peak memory	202916 kb
Host	smart-17d895b2-2168-4128-8c57-69141cf4b008
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374852109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3374852109
Directory	/workspace/5.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/5.sram_ctrl_regwen.2509503248
Short name	T1
Test name
Test status
Simulation time	18330503071 ps
CPU time	1067.19 seconds
Started	Jul 16 07:41:20 PM PDT 24
Finished	Jul 16 07:59:27 PM PDT 24
Peak memory	355232 kb
Host	smart-ce1e98eb-050b-4d25-9a63-e3d73c077535
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509503248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2509503248
Directory	/workspace/5.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/5.sram_ctrl_smoke.3406264919
Short name	T655
Test name
Test status
Simulation time	3666105815 ps
CPU time	33.4 seconds
Started	Jul 16 07:41:26 PM PDT 24
Finished	Jul 16 07:42:19 PM PDT 24
Peak memory	282548 kb
Host	smart-d5983364-b8e9-4c9f-8b8e-6d70a82dc181
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406264919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3406264919
Directory	/workspace/5.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all.2889030457
Short name	T237
Test name
Test status
Simulation time	50837282864 ps
CPU time	2277.56 seconds
Started	Jul 16 07:41:21 PM PDT 24
Finished	Jul 16 08:19:39 PM PDT 24
Peak memory	377052 kb
Host	smart-d78238f1-8dfa-4f98-aaf3-fab5fa920c97
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889030457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.2889030457
Directory	/workspace/5.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.286373380
Short name	T50
Test name
Test status
Simulation time	4576963659 ps
CPU time	61.42 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 07:42:51 PM PDT 24
Peak memory	314396 kb
Host	smart-693be102-6fc8-4d90-ba3c-151d0a036b66
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=286373380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.286373380
Directory	/workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3962630317
Short name	T765
Test name
Test status
Simulation time	8763052178 ps
CPU time	357.7 seconds
Started	Jul 16 07:41:21 PM PDT 24
Finished	Jul 16 07:47:39 PM PDT 24
Peak memory	202792 kb
Host	smart-437621cf-16a4-455c-8e31-1d5766031ac8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962630317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.3962630317
Directory	/workspace/5.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1349551502
Short name	T773
Test name
Test status
Simulation time	56904539 ps
CPU time	1.79 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:41:46 PM PDT 24
Peak memory	211032 kb
Host	smart-672d92f8-e46c-4ce1-859b-cd371f1d74b2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349551502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1349551502
Directory	/workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1181999490
Short name	T170
Test name
Test status
Simulation time	4360467011 ps
CPU time	481.94 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:49:51 PM PDT 24
Peak memory	375192 kb
Host	smart-6955b7cf-4d22-4020-ad73-b14fbbf0d443
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181999490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.1181999490
Directory	/workspace/6.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/6.sram_ctrl_alert_test.3498045978
Short name	T654
Test name
Test status
Simulation time	52737062 ps
CPU time	0.65 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 07:41:51 PM PDT 24
Peak memory	202552 kb
Host	smart-6df96f54-afec-46c2-8ec6-669356af33e0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498045978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3498045978
Directory	/workspace/6.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.sram_ctrl_bijection.3800392001
Short name	T816
Test name
Test status
Simulation time	1863818040 ps
CPU time	62.11 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:42:48 PM PDT 24
Peak memory	202408 kb
Host	smart-4fa1ae48-48e0-40b1-8857-c006b10405b2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800392001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 3800392001
Directory	/workspace/6.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/6.sram_ctrl_executable.3835710821
Short name	T215
Test name
Test status
Simulation time	9137496919 ps
CPU time	396.19 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:48:21 PM PDT 24
Peak memory	365604 kb
Host	smart-3ee301f5-8b08-41a0-94fa-2563c078c602
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835710821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.3835710821
Directory	/workspace/6.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/6.sram_ctrl_lc_escalation.1224489756
Short name	T904
Test name
Test status
Simulation time	2606652884 ps
CPU time	7.96 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:41:54 PM PDT 24
Peak memory	202812 kb
Host	smart-8b7445ad-7314-427d-8eb2-c9fe9618e903
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224489756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.1224489756
Directory	/workspace/6.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/6.sram_ctrl_max_throughput.1639260446
Short name	T887
Test name
Test status
Simulation time	304791209 ps
CPU time	22.36 seconds
Started	Jul 16 07:41:21 PM PDT 24
Finished	Jul 16 07:42:04 PM PDT 24
Peak memory	277652 kb
Host	smart-f55e4d9d-749e-4580-b697-7bf925a54a75
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639260446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.1639260446
Directory	/workspace/6.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3622835667
Short name	T33
Test name
Test status
Simulation time	95099145 ps
CPU time	5.77 seconds
Started	Jul 16 07:41:30 PM PDT 24
Finished	Jul 16 07:41:56 PM PDT 24
Peak memory	211052 kb
Host	smart-a15386ae-bce6-4cbc-ad09-d1de694a8cf6
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622835667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.3622835667
Directory	/workspace/6.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_walk.3874043415
Short name	T425
Test name
Test status
Simulation time	518781415 ps
CPU time	8.95 seconds
Started	Jul 16 07:41:27 PM PDT 24
Finished	Jul 16 07:41:57 PM PDT 24
Peak memory	211292 kb
Host	smart-9eb8c02d-26eb-436f-8f5a-1722b40fbeab
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874043415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.3874043415
Directory	/workspace/6.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/6.sram_ctrl_multiple_keys.865039827
Short name	T849
Test name
Test status
Simulation time	36235742295 ps
CPU time	1893.63 seconds
Started	Jul 16 07:41:27 PM PDT 24
Finished	Jul 16 08:13:21 PM PDT 24
Peak memory	374728 kb
Host	smart-3eed65b9-ec91-4722-abc9-d4e168c356b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865039827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multipl e_keys.865039827
Directory	/workspace/6.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access.2650797271
Short name	T701
Test name
Test status
Simulation time	1742545334 ps
CPU time	103.59 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 07:43:25 PM PDT 24
Peak memory	360160 kb
Host	smart-0130eaac-703c-4359-b868-046cdea509e9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650797271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.2650797271
Directory	/workspace/6.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3366668112
Short name	T460
Test name
Test status
Simulation time	37858554817 ps
CPU time	503.33 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:50:08 PM PDT 24
Peak memory	202900 kb
Host	smart-bc02dca0-91dc-48a0-9ceb-d80b06c807ca
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366668112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.3366668112
Directory	/workspace/6.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/6.sram_ctrl_ram_cfg.4147199459
Short name	T141
Test name
Test status
Simulation time	25540773 ps
CPU time	0.75 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:46 PM PDT 24
Peak memory	202896 kb
Host	smart-5842bc83-84ec-4a2b-b0ca-94ab9b332752
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147199459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.4147199459
Directory	/workspace/6.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/6.sram_ctrl_regwen.1223739555
Short name	T539
Test name
Test status
Simulation time	125112386332 ps
CPU time	1303.23 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 08:03:28 PM PDT 24
Peak memory	375760 kb
Host	smart-0b165d0b-2561-46a3-9b3e-188292d7658c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223739555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1223739555
Directory	/workspace/6.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/6.sram_ctrl_smoke.84498097
Short name	T855
Test name
Test status
Simulation time	2815224493 ps
CPU time	11.88 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:57 PM PDT 24
Peak memory	202952 kb
Host	smart-a7035e90-83b4-4ad4-a097-9c98c9d4f7a9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84498097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.84498097
Directory	/workspace/6.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all.761591689
Short name	T216
Test name
Test status
Simulation time	76254733081 ps
CPU time	1227.3 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 08:02:17 PM PDT 24
Peak memory	371952 kb
Host	smart-2f4085de-f3d4-41bd-9f70-85f12009aeea
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761591689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_stress_all.761591689
Directory	/workspace/6.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2038323113
Short name	T784
Test name
Test status
Simulation time	3854654717 ps
CPU time	9.54 seconds
Started	Jul 16 07:41:26 PM PDT 24
Finished	Jul 16 07:41:56 PM PDT 24
Peak memory	219476 kb
Host	smart-436c57a7-11e7-4840-b854-0d8738dec4d2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2038323113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2038323113
Directory	/workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3743697464
Short name	T247
Test name
Test status
Simulation time	12750476021 ps
CPU time	300.18 seconds
Started	Jul 16 07:41:27 PM PDT 24
Finished	Jul 16 07:46:48 PM PDT 24
Peak memory	202940 kb
Host	smart-d3dfd086-80cb-4b8a-bf2f-3d514b92200a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743697464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.3743697464
Directory	/workspace/6.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.908091640
Short name	T685
Test name
Test status
Simulation time	1819160834 ps
CPU time	146.54 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:44:11 PM PDT 24
Peak memory	369400 kb
Host	smart-5d115303-6418-44d7-91ab-515eddcf45d1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908091640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.908091640
Directory	/workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.4033845366
Short name	T281
Test name
Test status
Simulation time	1213438780 ps
CPU time	493.59 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:50:03 PM PDT 24
Peak memory	371388 kb
Host	smart-7b5375e3-a953-499a-b810-1fa7b6a4755e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033845366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.4033845366
Directory	/workspace/7.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/7.sram_ctrl_alert_test.3659985805
Short name	T891
Test name
Test status
Simulation time	14976077 ps
CPU time	0.64 seconds
Started	Jul 16 07:41:26 PM PDT 24
Finished	Jul 16 07:41:47 PM PDT 24
Peak memory	202676 kb
Host	smart-f9091cdf-b3de-4c5c-81d5-8413d421bee7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659985805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3659985805
Directory	/workspace/7.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.sram_ctrl_bijection.3349236550
Short name	T259
Test name
Test status
Simulation time	1806303468 ps
CPU time	60.96 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 07:42:51 PM PDT 24
Peak memory	202784 kb
Host	smart-4b2298d8-0ffe-4861-8820-0aa345d0125c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349236550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 3349236550
Directory	/workspace/7.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/7.sram_ctrl_executable.1185757921
Short name	T546
Test name
Test status
Simulation time	2068968272 ps
CPU time	591.18 seconds
Started	Jul 16 07:41:27 PM PDT 24
Finished	Jul 16 07:51:39 PM PDT 24
Peak memory	347580 kb
Host	smart-713da605-c721-4160-81b5-a194cc9aac23
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185757921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.1185757921
Directory	/workspace/7.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/7.sram_ctrl_lc_escalation.3805853549
Short name	T553
Test name
Test status
Simulation time	764591420 ps
CPU time	8.27 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:53 PM PDT 24
Peak memory	202744 kb
Host	smart-e030012e-5e78-498f-970b-57781f267606
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805853549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.3805853549
Directory	/workspace/7.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/7.sram_ctrl_max_throughput.3162898191
Short name	T140
Test name
Test status
Simulation time	198650909 ps
CPU time	34.69 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:42:24 PM PDT 24
Peak memory	291020 kb
Host	smart-4f860e98-e805-4d32-b4bf-099fed27f2c8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162898191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.3162898191
Directory	/workspace/7.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3475127296
Short name	T96
Test name
Test status
Simulation time	322808263 ps
CPU time	3.34 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:41:49 PM PDT 24
Peak memory	211120 kb
Host	smart-ac65db59-b0d0-4754-9ebc-986a4f44cc03
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475127296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.3475127296
Directory	/workspace/7.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_walk.2008467022
Short name	T569
Test name
Test status
Simulation time	307141378 ps
CPU time	5.8 seconds
Started	Jul 16 07:41:26 PM PDT 24
Finished	Jul 16 07:41:52 PM PDT 24
Peak memory	211060 kb
Host	smart-9f884ac7-c94a-44be-ad98-21c646647902
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008467022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2008467022
Directory	/workspace/7.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/7.sram_ctrl_multiple_keys.3951737052
Short name	T524
Test name
Test status
Simulation time	4798611273 ps
CPU time	499.32 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 07:50:09 PM PDT 24
Peak memory	374224 kb
Host	smart-1611fc92-23c1-4382-982d-330bde006b8b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951737052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.3951737052
Directory	/workspace/7.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access.3593518880
Short name	T799
Test name
Test status
Simulation time	1656987223 ps
CPU time	55.05 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:42:39 PM PDT 24
Peak memory	337644 kb
Host	smart-9e0f275f-f002-42a3-8990-bb09f4bc0962
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593518880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.3593518880
Directory	/workspace/7.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.918981175
Short name	T337
Test name
Test status
Simulation time	13489418058 ps
CPU time	299.11 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 07:46:49 PM PDT 24
Peak memory	202972 kb
Host	smart-dd46b0a5-23d3-4c04-b36c-c9443ee91849
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918981175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.sram_ctrl_partial_access_b2b.918981175
Directory	/workspace/7.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/7.sram_ctrl_ram_cfg.2809331408
Short name	T675
Test name
Test status
Simulation time	47950691 ps
CPU time	0.75 seconds
Started	Jul 16 07:41:26 PM PDT 24
Finished	Jul 16 07:41:48 PM PDT 24
Peak memory	202896 kb
Host	smart-da80f721-adc9-4161-80b9-5ef9fe470fa1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809331408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2809331408
Directory	/workspace/7.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/7.sram_ctrl_regwen.1637687792
Short name	T309
Test name
Test status
Simulation time	11363265313 ps
CPU time	392.01 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:48:22 PM PDT 24
Peak memory	347468 kb
Host	smart-3dddc07e-7fc7-4af2-9f43-1ff7aa22cf63
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637687792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1637687792
Directory	/workspace/7.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/7.sram_ctrl_smoke.187045671
Short name	T41
Test name
Test status
Simulation time	55342870 ps
CPU time	2.55 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:47 PM PDT 24
Peak memory	209876 kb
Host	smart-957c0c27-318e-43a0-b4b1-d0e4c3d00946
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187045671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.187045671
Directory	/workspace/7.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all.3633182491
Short name	T37
Test name
Test status
Simulation time	6086460602 ps
CPU time	1778.95 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 08:11:29 PM PDT 24
Peak memory	376724 kb
Host	smart-86326e8e-daa1-4ed1-8263-66caadd207ad
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633182491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.3633182491
Directory	/workspace/7.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4075577073
Short name	T47
Test name
Test status
Simulation time	16348745976 ps
CPU time	216.78 seconds
Started	Jul 16 07:41:26 PM PDT 24
Finished	Jul 16 07:45:23 PM PDT 24
Peak memory	380788 kb
Host	smart-fd9a87fb-7d73-48bd-9120-9d735f954d76
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4075577073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.4075577073
Directory	/workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3088734764
Short name	T388
Test name
Test status
Simulation time	3656698765 ps
CPU time	354.7 seconds
Started	Jul 16 07:41:19 PM PDT 24
Finished	Jul 16 07:47:34 PM PDT 24
Peak memory	202948 kb
Host	smart-6197a60f-c54b-4cc8-908a-0b80b37e314c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088734764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.3088734764
Directory	/workspace/7.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3602122894
Short name	T420
Test name
Test status
Simulation time	128223022 ps
CPU time	72.67 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 07:42:54 PM PDT 24
Peak memory	321216 kb
Host	smart-ffe5c04f-eec4-4bbd-8d66-87c2638ef75c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602122894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.3602122894
Directory	/workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1640633595
Short name	T470
Test name
Test status
Simulation time	14002266863 ps
CPU time	727.69 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:53:52 PM PDT 24
Peak memory	373672 kb
Host	smart-a1f8bd23-5d49-4a3a-a99e-7d271956affd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640633595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.1640633595
Directory	/workspace/8.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/8.sram_ctrl_alert_test.1571824055
Short name	T902
Test name
Test status
Simulation time	30271172 ps
CPU time	0.66 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:41:45 PM PDT 24
Peak memory	202668 kb
Host	smart-c4feaed5-88ac-4d85-b83d-9a3d42b71329
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571824055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.1571824055
Directory	/workspace/8.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.sram_ctrl_bijection.2746313065
Short name	T483
Test name
Test status
Simulation time	4551031373 ps
CPU time	75.8 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:43:05 PM PDT 24
Peak memory	202940 kb
Host	smart-2dd91bd2-20d3-45af-b094-f5c4fb3061fe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746313065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 2746313065
Directory	/workspace/8.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/8.sram_ctrl_executable.3584156760
Short name	T209
Test name
Test status
Simulation time	67777329697 ps
CPU time	1247.82 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 08:02:38 PM PDT 24
Peak memory	366340 kb
Host	smart-a1b782f4-9b54-4cd7-83af-88371add3a30
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584156760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.3584156760
Directory	/workspace/8.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/8.sram_ctrl_lc_escalation.4039304542
Short name	T614
Test name
Test status
Simulation time	1831077660 ps
CPU time	9.6 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:41:54 PM PDT 24
Peak memory	210908 kb
Host	smart-c27c8ee1-b8e3-41ca-a4fa-b965fec97845
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039304542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.4039304542
Directory	/workspace/8.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/8.sram_ctrl_max_throughput.4247406663
Short name	T151
Test name
Test status
Simulation time	79513644 ps
CPU time	15.41 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 07:42:05 PM PDT 24
Peak memory	272344 kb
Host	smart-869ebdc3-4dfd-49cb-930d-2d88dc904767
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247406663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.4247406663
Directory	/workspace/8.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_partial_access.62367502
Short name	T500
Test name
Test status
Simulation time	147633400 ps
CPU time	5.75 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:41:50 PM PDT 24
Peak memory	211080 kb
Host	smart-3435bad4-2c81-4ab2-94c6-762d9e473439
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62367502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_mem_partial_access.62367502
Directory	/workspace/8.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_walk.2568250933
Short name	T592
Test name
Test status
Simulation time	663141719 ps
CPU time	5.76 seconds
Started	Jul 16 07:41:30 PM PDT 24
Finished	Jul 16 07:41:57 PM PDT 24
Peak memory	211080 kb
Host	smart-477d067d-0dbd-4874-bed0-06fc1dc4a6d9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568250933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.2568250933
Directory	/workspace/8.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/8.sram_ctrl_multiple_keys.2584496962
Short name	T473
Test name
Test status
Simulation time	2464095186 ps
CPU time	857.06 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:56:07 PM PDT 24
Peak memory	369552 kb
Host	smart-d4cd33d9-c5f4-45d2-9fd8-34630e50eaa2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584496962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.2584496962
Directory	/workspace/8.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access.374140845
Short name	T940
Test name
Test status
Simulation time	527635251 ps
CPU time	4.74 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 07:41:55 PM PDT 24
Peak memory	202800 kb
Host	smart-f5b939cb-d60b-4894-ab2a-ed3e8a0db597
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374140845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr am_ctrl_partial_access.374140845
Directory	/workspace/8.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3229549768
Short name	T518
Test name
Test status
Simulation time	8363018629 ps
CPU time	190.83 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:44:55 PM PDT 24
Peak memory	202868 kb
Host	smart-c1452303-f4de-4f57-8a2b-17950bddf8fa
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229549768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.3229549768
Directory	/workspace/8.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/8.sram_ctrl_ram_cfg.2580839965
Short name	T171
Test name
Test status
Simulation time	41554200 ps
CPU time	0.79 seconds
Started	Jul 16 07:41:30 PM PDT 24
Finished	Jul 16 07:41:52 PM PDT 24
Peak memory	202864 kb
Host	smart-7acba24c-5535-4720-b907-42b461a2cb68
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580839965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2580839965
Directory	/workspace/8.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/8.sram_ctrl_regwen.2450596004
Short name	T279
Test name
Test status
Simulation time	17092537267 ps
CPU time	631.45 seconds
Started	Jul 16 07:41:30 PM PDT 24
Finished	Jul 16 07:52:22 PM PDT 24
Peak memory	366340 kb
Host	smart-79529f25-1821-410a-a17f-30ca83aac1a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450596004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2450596004
Directory	/workspace/8.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/8.sram_ctrl_smoke.2663676359
Short name	T367
Test name
Test status
Simulation time	690206923 ps
CPU time	11.02 seconds
Started	Jul 16 07:41:30 PM PDT 24
Finished	Jul 16 07:42:02 PM PDT 24
Peak memory	202812 kb
Host	smart-f6d0bd35-3a32-434a-aa69-fe349dfbbdd8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663676359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2663676359
Directory	/workspace/8.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all.1613989455
Short name	T502
Test name
Test status
Simulation time	44715847070 ps
CPU time	3461.14 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 08:39:26 PM PDT 24
Peak memory	376432 kb
Host	smart-c9eff0be-2c4d-4953-a1f5-005bb4210352
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613989455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.1613989455
Directory	/workspace/8.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.998224049
Short name	T808
Test name
Test status
Simulation time	11817813616 ps
CPU time	180.85 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 07:44:51 PM PDT 24
Peak memory	202900 kb
Host	smart-da63d261-8287-4b6c-ba04-efb848015ac0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998224049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8. sram_ctrl_stress_pipeline.998224049
Directory	/workspace/8.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1938291864
Short name	T742
Test name
Test status
Simulation time	45436472 ps
CPU time	3.3 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:48 PM PDT 24
Peak memory	219196 kb
Host	smart-3940beb9-c0ae-48b6-b9b8-cb3316133ebd
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938291864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1938291864
Directory	/workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2231785869
Short name	T368
Test name
Test status
Simulation time	2791517015 ps
CPU time	577.06 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:51:22 PM PDT 24
Peak memory	347288 kb
Host	smart-02318efd-4f40-45ff-bae1-974603aa3b7b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231785869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.2231785869
Directory	/workspace/9.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/9.sram_ctrl_alert_test.468588111
Short name	T733
Test name
Test status
Simulation time	61498314 ps
CPU time	0.67 seconds
Started	Jul 16 07:41:26 PM PDT 24
Finished	Jul 16 07:41:47 PM PDT 24
Peak memory	202644 kb
Host	smart-a558400f-a9c7-417f-ac57-5a5935efc60a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468588111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.468588111
Directory	/workspace/9.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.sram_ctrl_bijection.3156074834
Short name	T751
Test name
Test status
Simulation time	1319827976 ps
CPU time	21.92 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 07:42:04 PM PDT 24
Peak memory	202856 kb
Host	smart-71eb127b-bfcc-45e4-a443-293c1b55326d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156074834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 3156074834
Directory	/workspace/9.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/9.sram_ctrl_executable.1326766488
Short name	T485
Test name
Test status
Simulation time	3983753768 ps
CPU time	211.63 seconds
Started	Jul 16 07:41:19 PM PDT 24
Finished	Jul 16 07:45:11 PM PDT 24
Peak memory	294500 kb
Host	smart-16c33316-9418-4d65-8820-35880727de92
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326766488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.1326766488
Directory	/workspace/9.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/9.sram_ctrl_lc_escalation.2099131466
Short name	T501
Test name
Test status
Simulation time	1657643493 ps
CPU time	6.5 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 07:41:48 PM PDT 24
Peak memory	210992 kb
Host	smart-fa6d0834-0836-441f-9674-fed90334c170
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099131466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.2099131466
Directory	/workspace/9.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/9.sram_ctrl_max_throughput.1858321724
Short name	T356
Test name
Test status
Simulation time	80475823 ps
CPU time	16.48 seconds
Started	Jul 16 07:41:23 PM PDT 24
Finished	Jul 16 07:42:00 PM PDT 24
Peak memory	270116 kb
Host	smart-ff32979b-5efc-4572-9f72-b81631d8a0ee
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858321724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.1858321724
Directory	/workspace/9.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2165786562
Short name	T579
Test name
Test status
Simulation time	249519317 ps
CPU time	4.64 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:41:55 PM PDT 24
Peak memory	211084 kb
Host	smart-e698809c-0f82-4cb4-b190-8ff3c685a11f
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165786562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.2165786562
Directory	/workspace/9.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_walk.3386204108
Short name	T333
Test name
Test status
Simulation time	77965970 ps
CPU time	4.57 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:41:54 PM PDT 24
Peak memory	211100 kb
Host	smart-28bda49d-47ca-4484-a8ee-316f73f6dc49
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386204108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3386204108
Directory	/workspace/9.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/9.sram_ctrl_multiple_keys.3402871516
Short name	T560
Test name
Test status
Simulation time	16490685519 ps
CPU time	976 seconds
Started	Jul 16 07:41:25 PM PDT 24
Finished	Jul 16 07:58:02 PM PDT 24
Peak memory	373648 kb
Host	smart-3f0f8daa-80f1-4c77-a8f9-41b63cfc1c02
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402871516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.3402871516
Directory	/workspace/9.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access.2066997928
Short name	T785
Test name
Test status
Simulation time	261331004 ps
CPU time	14.37 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:41:59 PM PDT 24
Peak memory	202816 kb
Host	smart-e6a7ea65-48d7-464d-a7b1-b4ce61d91685
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066997928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.2066997928
Directory	/workspace/9.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2292012053
Short name	T651
Test name
Test status
Simulation time	25249889100 ps
CPU time	338.83 seconds
Started	Jul 16 07:41:33 PM PDT 24
Finished	Jul 16 07:47:30 PM PDT 24
Peak memory	202876 kb
Host	smart-dbbfff93-f33a-4fee-bc40-fffc71539ee9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292012053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.2292012053
Directory	/workspace/9.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/9.sram_ctrl_ram_cfg.811183838
Short name	T723
Test name
Test status
Simulation time	33830167 ps
CPU time	0.82 seconds
Started	Jul 16 07:41:32 PM PDT 24
Finished	Jul 16 07:41:52 PM PDT 24
Peak memory	202868 kb
Host	smart-359f9130-a5c7-491c-a49f-192d0b7b6e2d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811183838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.811183838
Directory	/workspace/9.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/9.sram_ctrl_regwen.1974599472
Short name	T315
Test name
Test status
Simulation time	8271573690 ps
CPU time	300.14 seconds
Started	Jul 16 07:41:29 PM PDT 24
Finished	Jul 16 07:46:50 PM PDT 24
Peak memory	353832 kb
Host	smart-32c269c8-819e-4b22-9a8c-f3bd3a0bb43e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974599472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1974599472
Directory	/workspace/9.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/9.sram_ctrl_smoke.649855795
Short name	T208
Test name
Test status
Simulation time	557346943 ps
CPU time	55.17 seconds
Started	Jul 16 07:41:30 PM PDT 24
Finished	Jul 16 07:42:46 PM PDT 24
Peak memory	320064 kb
Host	smart-6ff7b72e-2c70-4c4b-b532-200a5a0e2354
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649855795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.649855795
Directory	/workspace/9.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all.672719536
Short name	T786
Test name
Test status
Simulation time	17701147036 ps
CPU time	2323.46 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 08:20:34 PM PDT 24
Peak memory	376368 kb
Host	smart-bdc8314e-b748-467e-96b1-69fd8482db81
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672719536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_stress_all.672719536
Directory	/workspace/9.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3900424352
Short name	T57
Test name
Test status
Simulation time	5897153719 ps
CPU time	112 seconds
Started	Jul 16 07:41:22 PM PDT 24
Finished	Jul 16 07:43:36 PM PDT 24
Peak memory	333748 kb
Host	smart-449fb42d-e7bd-4d41-925b-b4167099980e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3900424352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3900424352
Directory	/workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3272188445
Short name	T233
Test name
Test status
Simulation time	18883564910 ps
CPU time	301.28 seconds
Started	Jul 16 07:41:28 PM PDT 24
Finished	Jul 16 07:46:51 PM PDT 24
Peak memory	202924 kb
Host	smart-51b07262-4b15-4fb2-8a7b-cc494a35925e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272188445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.3272188445
Directory	/workspace/9.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3457892927
Short name	T923
Test name
Test status
Simulation time	311843128 ps
CPU time	126.35 seconds
Started	Jul 16 07:41:24 PM PDT 24
Finished	Jul 16 07:43:51 PM PDT 24
Peak memory	371164 kb
Host	smart-4fb231b8-a95d-4e01-a72a-04beea58444c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457892927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3457892927
Directory	/workspace/9.sram_ctrl_throughput_w_partial_write/latest