Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13088339

1

T2

63368

T3

7821

T4

12438

full_word

54023074

1

T1

24576

T2

632049

T3

79361

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67111123	1			T1	24576		T2	695417		T3	87182
auto[TlIntgErrCmd]	101	1			T73	1		T74	5		T75	8
auto[TlIntgErrData]	98	1			T73	4		T74	4		T75	5
auto[TlIntgErrBoth]	91	1			T73	5		T74	1		T75	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30645768

1

T1

12288

T2

271774

T3

32657

auto[1]

36465645

1

T1

12288

T2

423643

T3

54525

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6242988	1			T2	24813		T3	2947		T4	6295
auto[TlIntgErrNone]	partial	auto[1]	6845085	1			T2	38555		T3	4874		T4	6143
auto[TlIntgErrNone]	full_word	auto[0]	24402647	1			T1	12288		T2	246961		T3	29710
auto[TlIntgErrNone]	full_word	auto[1]	29620403	1			T1	12288		T2	385088		T3	49651
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T73	1		T74	2		T75	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T74	2		T75	4		T144	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T149	1		T154	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T74	1		T75	1		T155	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T73	1		T74	2		T75	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T73	1		T74	2		T75	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T73	1		T155	1		T151	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T73	1		T144	1		T145	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T73	2		T75	1		T144	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T73	3		T74	1		T75	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T144	1		T155	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T144	1		T146	1		T157	1