Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	554075	1			T2	8250		T3	1414		T13	22
auto[1]	10482375	1			T2	5766		T3	338		T4	58175
auto[2]	465729	1			T2	5378		T3	1264		T13	33
auto[3]	10395891	1			T2	2862		T3	182		T4	58212

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14261868	1			T2	17159		T3	2512		T4	96786
auto[1]	2083672	1			T2	2042		T3	322		T4	9183
auto[2]	2113917	1			T2	2740		T3	316		T4	9518
auto[3]	3438613	1			T2	315		T3	48		T4	900

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8285782

1

T2

22240

T3

3197

T11

61656

auto[1]

13612288

1

T2

16

T3

1

T4

116387

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	260930	1			T2	6850		T3	1181		T13	14
auto[0]	auto[0]	auto[1]	26977	1			T2	663		T3	104		T13	6
auto[0]	auto[0]	auto[2]	26978	1			T2	667		T3	119		T13	2
auto[0]	auto[0]	auto[3]	7908	1			T2	67		T3	10		T43	1
auto[0]	auto[1]	auto[0]	3151765	1			T2	4439		T3	178		T11	25876
auto[0]	auto[1]	auto[1]	328301	1			T2	788		T3	122		T11	2172
auto[0]	auto[1]	auto[2]	317742	1			T2	449		T3	18		T11	2592
auto[0]	auto[1]	auto[3]	68072	1			T2	84		T3	20		T11	204
auto[0]	auto[2]	auto[0]	220617	1			T2	4160		T3	1074		T6	1
auto[0]	auto[2]	auto[1]	22613	1			T2	396		T3	86		T43	1
auto[0]	auto[2]	auto[2]	25524	1			T2	734		T3	95		T13	32
auto[0]	auto[2]	auto[3]	6962	1			T2	83		T3	8		T13	1
auto[0]	auto[3]	auto[0]	3111870	1			T2	1700		T3	78		T11	25974
auto[0]	auto[3]	auto[1]	312875	1			T2	191		T3	10		T11	2444
auto[0]	auto[3]	auto[2]	327749	1			T2	888		T3	84		T11	2192
auto[0]	auto[3]	auto[3]	68899	1			T2	81		T3	10		T11	202
auto[1]	auto[0]	auto[0]	7952	1			T2	2		T43	376		T69	1
auto[1]	auto[0]	auto[1]	34392	1			T2	1		T43	1691		T163	366
auto[1]	auto[0]	auto[2]	34312	1			T43	1793		T165	1		T163	413
auto[1]	auto[0]	auto[3]	154626	1			T43	7895		T165	1		T163	1714
auto[1]	auto[1]	auto[0]	3753135	1			T2	3		T4	48393		T11	30
auto[1]	auto[1]	auto[1]	678335	1			T2	2		T4	4505		T11	2
auto[1]	auto[1]	auto[2]	677114	1			T2	1		T4	4830		T11	6
auto[1]	auto[1]	auto[3]	1507911	1			T4	447		T12	653		T43	9284
auto[1]	auto[2]	auto[0]	4577	1			T2	4		T3	1		T43	228
auto[1]	auto[2]	auto[1]	19803	1			T2	1		T43	1076		T166	1
auto[1]	auto[2]	auto[2]	30178	1			T43	1705		T7	1		T163	352
auto[1]	auto[2]	auto[3]	135455	1			T43	7758		T165	2		T163	1675
auto[1]	auto[3]	auto[0]	3751022	1			T2	1		T4	48393		T11	17
auto[1]	auto[3]	auto[1]	660376	1			T4	4678		T11	1		T12	6449
auto[1]	auto[3]	auto[2]	674320	1			T2	1		T4	4688		T11	2
auto[1]	auto[3]	auto[3]	1488780	1			T4	453		T11	1		T12	614