Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	308035398	170300	0	0
ctrl_regwen_rd_A	308035398	2835	0	0
exec_rd_A	308035398	3104	0	0
exec_regwen_rd_A	308035398	3086	0	0
readback_rd_A	308035398	1709	0	0
readback_regwen_rd_A	308035398	1408	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308035398	170300	0	0
T20	262314	0	0	0
T21	0	8790	0	0
T22	43770	0	0	0
T23	409094	0	0	0
T25	143528	6959	0	0
T26	0	1903	0	0
T29	2947	0	0	0
T52	0	3419	0	0
T54	0	3329	0	0
T59	0	2571	0	0
T65	0	1988	0	0
T66	0	3452	0	0
T68	38876	0	0	0
T69	927722	0	0	0
T70	6115	0	0	0
T71	2973	0	0	0
T72	3430	0	0	0
T80	0	5554	0	0
T81	0	1621	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308035398	2835	0	0
T52	127610	251	0	0
T54	82673	0	0	0
T78	0	57	0	0
T81	13927	0	0	0
T128	0	142	0	0
T129	0	98	0	0
T130	0	177	0	0
T131	0	150	0	0
T132	0	130	0	0
T133	0	70	0	0
T134	0	321	0	0
T135	0	123	0	0
T136	172247	0	0	0
T137	65632	0	0	0
T138	26820	0	0	0
T139	5735	0	0	0
T140	290662	0	0	0
T141	205134	0	0	0
T142	149087	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308035398	3104	0	0
T52	127610	202	0	0
T54	82673	0	0	0
T78	0	50	0	0
T81	13927	0	0	0
T128	0	168	0	0
T129	0	99	0	0
T130	0	193	0	0
T131	0	170	0	0
T132	0	180	0	0
T133	0	87	0	0
T134	0	272	0	0
T135	0	120	0	0
T136	172247	0	0	0
T137	65632	0	0	0
T138	26820	0	0	0
T139	5735	0	0	0
T140	290662	0	0	0
T141	205134	0	0	0
T142	149087	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308035398	3086	0	0
T52	127610	256	0	0
T54	82673	0	0	0
T78	0	42	0	0
T81	13927	0	0	0
T128	0	156	0	0
T129	0	96	0	0
T130	0	251	0	0
T131	0	145	0	0
T132	0	180	0	0
T133	0	80	0	0
T134	0	350	0	0
T135	0	99	0	0
T136	172247	0	0	0
T137	65632	0	0	0
T138	26820	0	0	0
T139	5735	0	0	0
T140	290662	0	0	0
T141	205134	0	0	0
T142	149087	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308035398	1709	0	0
T52	127610	193	0	0
T54	82673	0	0	0
T81	13927	0	0	0
T128	0	111	0	0
T129	0	112	0	0
T130	0	139	0	0
T131	0	147	0	0
T132	0	195	0	0
T133	0	57	0	0
T134	0	331	0	0
T135	0	133	0	0
T136	172247	0	0	0
T137	65632	0	0	0
T138	26820	0	0	0
T139	5735	0	0	0
T140	290662	0	0	0
T141	205134	0	0	0
T142	149087	0	0	0
T143	0	26	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308035398	1408	0	0
T52	127610	226	0	0
T54	82673	0	0	0
T81	13927	0	0	0
T128	0	85	0	0
T129	0	99	0	0
T130	0	170	0	0
T131	0	103	0	0
T132	0	103	0	0
T133	0	49	0	0
T134	0	190	0	0
T135	0	110	0	0
T136	172247	0	0	0
T137	65632	0	0	0
T138	26820	0	0	0
T139	5735	0	0	0
T140	290662	0	0	0
T141	205134	0	0	0
T142	149087	0	0	0
T143	0	10	0	0