| T806 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1969603442 |
|
|
Jul 17 07:38:58 PM PDT 24 |
Jul 17 07:46:02 PM PDT 24 |
8798864002 ps |
| T807 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.713315907 |
|
|
Jul 17 07:38:16 PM PDT 24 |
Jul 17 07:44:08 PM PDT 24 |
26496258979 ps |
| T808 |
/workspace/coverage/default/15.sram_ctrl_partial_access.400861314 |
|
|
Jul 17 07:38:41 PM PDT 24 |
Jul 17 07:38:52 PM PDT 24 |
377505993 ps |
| T135 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.761957359 |
|
|
Jul 17 07:32:37 PM PDT 24 |
Jul 17 07:33:09 PM PDT 24 |
4319696188 ps |
| T809 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3218386586 |
|
|
Jul 17 07:33:08 PM PDT 24 |
Jul 17 07:33:30 PM PDT 24 |
95197933 ps |
| T810 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.1443335179 |
|
|
Jul 17 07:41:26 PM PDT 24 |
Jul 17 07:41:28 PM PDT 24 |
71445821 ps |
| T811 |
/workspace/coverage/default/22.sram_ctrl_bijection.3498674300 |
|
|
Jul 17 07:39:38 PM PDT 24 |
Jul 17 07:40:19 PM PDT 24 |
3665232779 ps |
| T812 |
/workspace/coverage/default/20.sram_ctrl_smoke.3919567219 |
|
|
Jul 17 07:39:34 PM PDT 24 |
Jul 17 07:39:38 PM PDT 24 |
98471155 ps |
| T813 |
/workspace/coverage/default/30.sram_ctrl_partial_access.3801381317 |
|
|
Jul 17 07:40:14 PM PDT 24 |
Jul 17 07:40:27 PM PDT 24 |
179019254 ps |
| T814 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.975055066 |
|
|
Jul 17 07:33:09 PM PDT 24 |
Jul 17 07:33:11 PM PDT 24 |
135215611 ps |
| T815 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.690819990 |
|
|
Jul 17 07:42:20 PM PDT 24 |
Jul 17 07:42:23 PM PDT 24 |
54725637 ps |
| T816 |
/workspace/coverage/default/38.sram_ctrl_partial_access.3028214430 |
|
|
Jul 17 07:40:58 PM PDT 24 |
Jul 17 07:41:05 PM PDT 24 |
589959954 ps |
| T817 |
/workspace/coverage/default/48.sram_ctrl_smoke.3519399527 |
|
|
Jul 17 07:42:16 PM PDT 24 |
Jul 17 07:42:22 PM PDT 24 |
343214830 ps |
| T818 |
/workspace/coverage/default/2.sram_ctrl_partial_access.535205311 |
|
|
Jul 17 07:33:06 PM PDT 24 |
Jul 17 07:33:22 PM PDT 24 |
861186209 ps |
| T819 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3038377544 |
|
|
Jul 17 07:40:34 PM PDT 24 |
Jul 17 07:40:36 PM PDT 24 |
11843026 ps |
| T820 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1358312369 |
|
|
Jul 17 07:40:40 PM PDT 24 |
Jul 17 08:48:10 PM PDT 24 |
12425792950 ps |
| T821 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.192154803 |
|
|
Jul 17 07:41:32 PM PDT 24 |
Jul 17 07:47:33 PM PDT 24 |
13747503144 ps |
| T30 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.4270324909 |
|
|
Jul 17 07:32:39 PM PDT 24 |
Jul 17 07:32:49 PM PDT 24 |
362910767 ps |
| T822 |
/workspace/coverage/default/21.sram_ctrl_smoke.1162783979 |
|
|
Jul 17 07:39:13 PM PDT 24 |
Jul 17 07:39:23 PM PDT 24 |
731588048 ps |
| T823 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3057936994 |
|
|
Jul 17 07:41:29 PM PDT 24 |
Jul 17 07:41:49 PM PDT 24 |
1080869729 ps |
| T824 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3835480441 |
|
|
Jul 17 07:37:42 PM PDT 24 |
Jul 17 07:44:07 PM PDT 24 |
16575615829 ps |
| T825 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2926832915 |
|
|
Jul 17 07:38:55 PM PDT 24 |
Jul 17 07:39:01 PM PDT 24 |
710881737 ps |
| T826 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1482668045 |
|
|
Jul 17 07:42:18 PM PDT 24 |
Jul 17 07:42:22 PM PDT 24 |
19674064 ps |
| T827 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.588088549 |
|
|
Jul 17 07:41:28 PM PDT 24 |
Jul 17 07:44:00 PM PDT 24 |
1047616403 ps |
| T828 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3423058385 |
|
|
Jul 17 07:39:33 PM PDT 24 |
Jul 17 07:39:41 PM PDT 24 |
387486541 ps |
| T829 |
/workspace/coverage/default/9.sram_ctrl_stress_all.569889751 |
|
|
Jul 17 07:34:11 PM PDT 24 |
Jul 17 08:46:25 PM PDT 24 |
49078633004 ps |
| T830 |
/workspace/coverage/default/18.sram_ctrl_executable.3098268482 |
|
|
Jul 17 07:38:51 PM PDT 24 |
Jul 17 07:44:12 PM PDT 24 |
36149659729 ps |
| T831 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.277686258 |
|
|
Jul 17 07:34:19 PM PDT 24 |
Jul 17 07:34:21 PM PDT 24 |
82173790 ps |
| T832 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.503088384 |
|
|
Jul 17 07:34:20 PM PDT 24 |
Jul 17 07:34:22 PM PDT 24 |
25441479 ps |
| T833 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3158404226 |
|
|
Jul 17 07:40:26 PM PDT 24 |
Jul 17 07:44:52 PM PDT 24 |
2900220578 ps |
| T834 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2037065785 |
|
|
Jul 17 07:37:47 PM PDT 24 |
Jul 17 07:37:51 PM PDT 24 |
545239111 ps |
| T835 |
/workspace/coverage/default/49.sram_ctrl_regwen.952665624 |
|
|
Jul 17 07:42:15 PM PDT 24 |
Jul 17 07:54:12 PM PDT 24 |
10098408887 ps |
| T836 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1994918562 |
|
|
Jul 17 07:41:32 PM PDT 24 |
Jul 17 07:46:55 PM PDT 24 |
18015992964 ps |
| T837 |
/workspace/coverage/default/5.sram_ctrl_partial_access.815010621 |
|
|
Jul 17 07:33:14 PM PDT 24 |
Jul 17 07:33:34 PM PDT 24 |
3748226125 ps |
| T838 |
/workspace/coverage/default/31.sram_ctrl_partial_access.750232654 |
|
|
Jul 17 07:40:23 PM PDT 24 |
Jul 17 07:42:40 PM PDT 24 |
2442175231 ps |
| T839 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.3769996548 |
|
|
Jul 17 07:38:58 PM PDT 24 |
Jul 17 07:39:05 PM PDT 24 |
756421922 ps |
| T840 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3426536544 |
|
|
Jul 17 07:33:17 PM PDT 24 |
Jul 17 07:34:22 PM PDT 24 |
133883551 ps |
| T841 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.3226336406 |
|
|
Jul 17 07:40:16 PM PDT 24 |
Jul 17 07:40:23 PM PDT 24 |
436806360 ps |
| T842 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2367015288 |
|
|
Jul 17 07:40:19 PM PDT 24 |
Jul 17 07:40:38 PM PDT 24 |
75787982 ps |
| T843 |
/workspace/coverage/default/39.sram_ctrl_bijection.411785549 |
|
|
Jul 17 07:40:55 PM PDT 24 |
Jul 17 07:41:49 PM PDT 24 |
884304906 ps |
| T844 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.889391369 |
|
|
Jul 17 07:40:51 PM PDT 24 |
Jul 17 07:41:02 PM PDT 24 |
182171652 ps |
| T845 |
/workspace/coverage/default/12.sram_ctrl_executable.1457223031 |
|
|
Jul 17 07:37:43 PM PDT 24 |
Jul 17 07:51:54 PM PDT 24 |
4589376672 ps |
| T846 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.2211997295 |
|
|
Jul 17 07:40:15 PM PDT 24 |
Jul 17 07:40:17 PM PDT 24 |
80782408 ps |
| T847 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2397739236 |
|
|
Jul 17 07:40:08 PM PDT 24 |
Jul 17 08:04:38 PM PDT 24 |
70215595858 ps |
| T848 |
/workspace/coverage/default/29.sram_ctrl_stress_all.1502049821 |
|
|
Jul 17 07:40:15 PM PDT 24 |
Jul 17 08:25:23 PM PDT 24 |
15552633492 ps |
| T849 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.3432628169 |
|
|
Jul 17 07:40:51 PM PDT 24 |
Jul 17 07:40:56 PM PDT 24 |
337232444 ps |
| T850 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2962301877 |
|
|
Jul 17 07:41:30 PM PDT 24 |
Jul 17 07:42:10 PM PDT 24 |
338246050 ps |
| T851 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4287799537 |
|
|
Jul 17 07:42:16 PM PDT 24 |
Jul 17 07:46:33 PM PDT 24 |
12125135038 ps |
| T852 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1951400430 |
|
|
Jul 17 07:34:17 PM PDT 24 |
Jul 17 07:34:20 PM PDT 24 |
206343293 ps |
| T853 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2942878351 |
|
|
Jul 17 07:39:39 PM PDT 24 |
Jul 17 07:39:54 PM PDT 24 |
1315997597 ps |
| T854 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.3635544228 |
|
|
Jul 17 07:33:14 PM PDT 24 |
Jul 17 07:39:49 PM PDT 24 |
10198033209 ps |
| T855 |
/workspace/coverage/default/37.sram_ctrl_executable.3272591385 |
|
|
Jul 17 07:40:41 PM PDT 24 |
Jul 17 07:54:35 PM PDT 24 |
13983275085 ps |
| T856 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2654406054 |
|
|
Jul 17 07:41:29 PM PDT 24 |
Jul 17 07:44:08 PM PDT 24 |
4223649398 ps |
| T857 |
/workspace/coverage/default/1.sram_ctrl_stress_all.968260652 |
|
|
Jul 17 07:33:18 PM PDT 24 |
Jul 17 08:41:41 PM PDT 24 |
54666886469 ps |
| T858 |
/workspace/coverage/default/3.sram_ctrl_regwen.473131554 |
|
|
Jul 17 07:33:18 PM PDT 24 |
Jul 17 07:47:50 PM PDT 24 |
22495299792 ps |
| T859 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1551691685 |
|
|
Jul 17 07:38:19 PM PDT 24 |
Jul 17 07:38:21 PM PDT 24 |
48974338 ps |
| T860 |
/workspace/coverage/default/45.sram_ctrl_executable.3324096444 |
|
|
Jul 17 07:41:54 PM PDT 24 |
Jul 17 08:06:05 PM PDT 24 |
17892800996 ps |
| T861 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2297496035 |
|
|
Jul 17 07:42:15 PM PDT 24 |
Jul 17 07:42:22 PM PDT 24 |
1583812391 ps |
| T862 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.1086257719 |
|
|
Jul 17 07:38:55 PM PDT 24 |
Jul 17 07:41:43 PM PDT 24 |
795585366 ps |
| T863 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2414366960 |
|
|
Jul 17 07:37:10 PM PDT 24 |
Jul 17 07:56:46 PM PDT 24 |
49021319830 ps |
| T864 |
/workspace/coverage/default/14.sram_ctrl_smoke.4023159157 |
|
|
Jul 17 07:37:43 PM PDT 24 |
Jul 17 07:37:57 PM PDT 24 |
778879030 ps |
| T865 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3185843209 |
|
|
Jul 17 07:41:27 PM PDT 24 |
Jul 17 07:51:12 PM PDT 24 |
21044536634 ps |
| T866 |
/workspace/coverage/default/32.sram_ctrl_regwen.3418611341 |
|
|
Jul 17 07:40:24 PM PDT 24 |
Jul 17 07:53:49 PM PDT 24 |
6610371864 ps |
| T867 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.24753595 |
|
|
Jul 17 07:40:34 PM PDT 24 |
Jul 17 07:40:41 PM PDT 24 |
1579979416 ps |
| T868 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.4145780229 |
|
|
Jul 17 07:39:38 PM PDT 24 |
Jul 17 07:49:22 PM PDT 24 |
71726219413 ps |
| T869 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1643479475 |
|
|
Jul 17 07:40:21 PM PDT 24 |
Jul 17 07:40:25 PM PDT 24 |
243551605 ps |
| T870 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.4113559756 |
|
|
Jul 17 07:40:03 PM PDT 24 |
Jul 17 07:48:17 PM PDT 24 |
24101236079 ps |
| T871 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.92815291 |
|
|
Jul 17 07:41:28 PM PDT 24 |
Jul 17 07:41:30 PM PDT 24 |
69187808 ps |
| T872 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3523046543 |
|
|
Jul 17 07:40:15 PM PDT 24 |
Jul 17 07:42:39 PM PDT 24 |
1107633030 ps |
| T873 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2315685041 |
|
|
Jul 17 07:42:17 PM PDT 24 |
Jul 17 07:44:15 PM PDT 24 |
636036188 ps |
| T874 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3351107707 |
|
|
Jul 17 07:40:04 PM PDT 24 |
Jul 17 07:45:26 PM PDT 24 |
26836595579 ps |
| T875 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3253147326 |
|
|
Jul 17 07:37:08 PM PDT 24 |
Jul 17 07:43:17 PM PDT 24 |
21530312391 ps |
| T876 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.3047812288 |
|
|
Jul 17 07:39:38 PM PDT 24 |
Jul 17 07:39:44 PM PDT 24 |
228544599 ps |
| T877 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1669678189 |
|
|
Jul 17 07:38:50 PM PDT 24 |
Jul 17 07:42:55 PM PDT 24 |
3438079143 ps |
| T878 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3101417828 |
|
|
Jul 17 07:40:23 PM PDT 24 |
Jul 17 07:40:24 PM PDT 24 |
19159426 ps |
| T879 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1764147727 |
|
|
Jul 17 07:39:39 PM PDT 24 |
Jul 17 07:39:42 PM PDT 24 |
31599075 ps |
| T880 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.3067949765 |
|
|
Jul 17 07:40:18 PM PDT 24 |
Jul 17 07:58:00 PM PDT 24 |
19008607520 ps |
| T881 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.64412404 |
|
|
Jul 17 07:38:17 PM PDT 24 |
Jul 17 07:38:27 PM PDT 24 |
62779914 ps |
| T882 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.609480395 |
|
|
Jul 17 07:33:09 PM PDT 24 |
Jul 17 07:33:13 PM PDT 24 |
175767883 ps |
| T883 |
/workspace/coverage/default/26.sram_ctrl_smoke.513593621 |
|
|
Jul 17 07:40:04 PM PDT 24 |
Jul 17 07:42:35 PM PDT 24 |
3637616519 ps |
| T884 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2481777926 |
|
|
Jul 17 07:40:11 PM PDT 24 |
Jul 17 07:40:29 PM PDT 24 |
2204122944 ps |
| T885 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2403057916 |
|
|
Jul 17 07:38:15 PM PDT 24 |
Jul 17 07:38:21 PM PDT 24 |
194786934 ps |
| T886 |
/workspace/coverage/default/9.sram_ctrl_regwen.70009317 |
|
|
Jul 17 07:34:17 PM PDT 24 |
Jul 17 07:48:02 PM PDT 24 |
13280436701 ps |
| T887 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.1078609534 |
|
|
Jul 17 07:40:43 PM PDT 24 |
Jul 17 07:40:55 PM PDT 24 |
594858243 ps |
| T888 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.895734133 |
|
|
Jul 17 07:42:18 PM PDT 24 |
Jul 17 07:42:24 PM PDT 24 |
113932861 ps |
| T889 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.979629662 |
|
|
Jul 17 07:41:26 PM PDT 24 |
Jul 17 07:52:28 PM PDT 24 |
2522004018 ps |
| T890 |
/workspace/coverage/default/8.sram_ctrl_smoke.227365734 |
|
|
Jul 17 07:34:19 PM PDT 24 |
Jul 17 07:34:32 PM PDT 24 |
370186130 ps |
| T891 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.1151449488 |
|
|
Jul 17 07:42:18 PM PDT 24 |
Jul 17 07:43:21 PM PDT 24 |
110420916 ps |
| T892 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2675809474 |
|
|
Jul 17 07:37:43 PM PDT 24 |
Jul 17 07:37:47 PM PDT 24 |
1580335228 ps |
| T893 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.755671612 |
|
|
Jul 17 07:34:18 PM PDT 24 |
Jul 17 07:38:07 PM PDT 24 |
19578645999 ps |
| T894 |
/workspace/coverage/default/23.sram_ctrl_executable.2470797242 |
|
|
Jul 17 07:39:34 PM PDT 24 |
Jul 17 07:48:30 PM PDT 24 |
7390325691 ps |
| T895 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3540771449 |
|
|
Jul 17 07:41:33 PM PDT 24 |
Jul 17 07:41:44 PM PDT 24 |
543009839 ps |
| T896 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1742998085 |
|
|
Jul 17 07:40:30 PM PDT 24 |
Jul 17 07:40:37 PM PDT 24 |
457349449 ps |
| T897 |
/workspace/coverage/default/27.sram_ctrl_executable.3073485484 |
|
|
Jul 17 07:40:15 PM PDT 24 |
Jul 17 08:05:08 PM PDT 24 |
47915529835 ps |
| T898 |
/workspace/coverage/default/19.sram_ctrl_smoke.11782849 |
|
|
Jul 17 07:38:50 PM PDT 24 |
Jul 17 07:41:08 PM PDT 24 |
634354012 ps |
| T899 |
/workspace/coverage/default/48.sram_ctrl_partial_access.1229523360 |
|
|
Jul 17 07:42:23 PM PDT 24 |
Jul 17 07:43:14 PM PDT 24 |
957475949 ps |
| T900 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3164531895 |
|
|
Jul 17 07:38:49 PM PDT 24 |
Jul 17 07:38:59 PM PDT 24 |
2377801036 ps |
| T901 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3780576381 |
|
|
Jul 17 07:40:04 PM PDT 24 |
Jul 17 07:40:59 PM PDT 24 |
239674263 ps |
| T902 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3861446497 |
|
|
Jul 17 07:39:32 PM PDT 24 |
Jul 17 07:39:49 PM PDT 24 |
1284710103 ps |
| T903 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1575840269 |
|
|
Jul 17 07:41:34 PM PDT 24 |
Jul 17 07:41:38 PM PDT 24 |
45292983 ps |
| T904 |
/workspace/coverage/default/21.sram_ctrl_executable.629592263 |
|
|
Jul 17 07:39:30 PM PDT 24 |
Jul 17 07:48:41 PM PDT 24 |
5499541528 ps |
| T905 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3382744685 |
|
|
Jul 17 07:40:56 PM PDT 24 |
Jul 17 07:50:14 PM PDT 24 |
2216609030 ps |
| T906 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1238307876 |
|
|
Jul 17 07:39:38 PM PDT 24 |
Jul 17 07:48:16 PM PDT 24 |
1711720298 ps |
| T907 |
/workspace/coverage/default/38.sram_ctrl_alert_test.4040869155 |
|
|
Jul 17 07:40:56 PM PDT 24 |
Jul 17 07:40:58 PM PDT 24 |
86097120 ps |
| T908 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4271025712 |
|
|
Jul 17 07:37:43 PM PDT 24 |
Jul 17 07:39:06 PM PDT 24 |
520689116 ps |
| T909 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3815264899 |
|
|
Jul 17 07:34:13 PM PDT 24 |
Jul 17 07:34:20 PM PDT 24 |
1766619145 ps |
| T910 |
/workspace/coverage/default/44.sram_ctrl_alert_test.1046945448 |
|
|
Jul 17 07:41:29 PM PDT 24 |
Jul 17 07:41:32 PM PDT 24 |
53657578 ps |
| T911 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2437936371 |
|
|
Jul 17 07:32:38 PM PDT 24 |
Jul 17 07:38:41 PM PDT 24 |
3744079546 ps |
| T912 |
/workspace/coverage/default/38.sram_ctrl_regwen.266791232 |
|
|
Jul 17 07:40:56 PM PDT 24 |
Jul 17 07:52:22 PM PDT 24 |
9242559179 ps |
| T913 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.108812191 |
|
|
Jul 17 07:40:41 PM PDT 24 |
Jul 17 07:41:29 PM PDT 24 |
525377763 ps |
| T914 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.744001508 |
|
|
Jul 17 07:40:41 PM PDT 24 |
Jul 17 07:40:43 PM PDT 24 |
60250882 ps |
| T915 |
/workspace/coverage/default/18.sram_ctrl_alert_test.2033489496 |
|
|
Jul 17 07:38:50 PM PDT 24 |
Jul 17 07:38:52 PM PDT 24 |
35949809 ps |
| T916 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1757317118 |
|
|
Jul 17 07:40:06 PM PDT 24 |
Jul 17 07:40:14 PM PDT 24 |
233085705 ps |
| T31 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2064166321 |
|
|
Jul 17 07:33:14 PM PDT 24 |
Jul 17 07:33:19 PM PDT 24 |
1230021234 ps |
| T917 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.3571881532 |
|
|
Jul 17 07:40:10 PM PDT 24 |
Jul 17 07:42:49 PM PDT 24 |
2146960023 ps |
| T918 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.993904598 |
|
|
Jul 17 07:38:17 PM PDT 24 |
Jul 17 07:49:33 PM PDT 24 |
2213161928 ps |
| T919 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3575894748 |
|
|
Jul 17 07:37:47 PM PDT 24 |
Jul 17 07:37:51 PM PDT 24 |
74035226 ps |
| T920 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.4207536945 |
|
|
Jul 17 07:39:39 PM PDT 24 |
Jul 17 07:45:24 PM PDT 24 |
22783071189 ps |
| T921 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4130287847 |
|
|
Jul 17 07:40:04 PM PDT 24 |
Jul 17 07:40:16 PM PDT 24 |
68551570 ps |
| T922 |
/workspace/coverage/default/14.sram_ctrl_bijection.1975820601 |
|
|
Jul 17 07:38:16 PM PDT 24 |
Jul 17 07:39:41 PM PDT 24 |
38559796064 ps |
| T923 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.209795769 |
|
|
Jul 17 07:42:18 PM PDT 24 |
Jul 17 07:48:32 PM PDT 24 |
4805800722 ps |
| T924 |
/workspace/coverage/default/2.sram_ctrl_regwen.150679249 |
|
|
Jul 17 07:33:07 PM PDT 24 |
Jul 17 07:52:18 PM PDT 24 |
3815397927 ps |
| T925 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1018061242 |
|
|
Jul 17 07:40:25 PM PDT 24 |
Jul 17 07:40:41 PM PDT 24 |
3924142030 ps |
| T926 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2644713193 |
|
|
Jul 17 07:40:16 PM PDT 24 |
Jul 17 07:40:21 PM PDT 24 |
367163053 ps |
| T927 |
/workspace/coverage/default/1.sram_ctrl_smoke.365853658 |
|
|
Jul 17 07:32:40 PM PDT 24 |
Jul 17 07:32:48 PM PDT 24 |
53070363 ps |
| T928 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2278093778 |
|
|
Jul 17 07:41:30 PM PDT 24 |
Jul 17 07:41:52 PM PDT 24 |
94996447 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_alert_test.3731638800 |
|
|
Jul 17 07:41:25 PM PDT 24 |
Jul 17 07:41:27 PM PDT 24 |
19836677 ps |
| T930 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.3593434427 |
|
|
Jul 17 07:41:25 PM PDT 24 |
Jul 17 07:41:32 PM PDT 24 |
318309942 ps |
| T931 |
/workspace/coverage/default/11.sram_ctrl_partial_access.2899309829 |
|
|
Jul 17 07:37:09 PM PDT 24 |
Jul 17 07:38:49 PM PDT 24 |
570924174 ps |
| T932 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2164374334 |
|
|
Jul 17 07:37:45 PM PDT 24 |
Jul 17 07:42:08 PM PDT 24 |
2683551299 ps |
| T933 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2123934551 |
|
|
Jul 17 07:34:18 PM PDT 24 |
Jul 17 07:34:24 PM PDT 24 |
154137700 ps |
| T934 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2888097306 |
|
|
Jul 17 07:41:30 PM PDT 24 |
Jul 17 07:43:16 PM PDT 24 |
279962622 ps |
| T935 |
/workspace/coverage/default/44.sram_ctrl_smoke.192064625 |
|
|
Jul 17 07:41:35 PM PDT 24 |
Jul 17 07:43:33 PM PDT 24 |
189085552 ps |
| T936 |
/workspace/coverage/default/20.sram_ctrl_bijection.3266287070 |
|
|
Jul 17 07:39:29 PM PDT 24 |
Jul 17 07:40:02 PM PDT 24 |
2916181892 ps |
| T937 |
/workspace/coverage/default/27.sram_ctrl_alert_test.236003358 |
|
|
Jul 17 07:40:15 PM PDT 24 |
Jul 17 07:40:16 PM PDT 24 |
114315546 ps |
| T938 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3024042211 |
|
|
Jul 17 07:42:14 PM PDT 24 |
Jul 17 07:44:10 PM PDT 24 |
450795579 ps |
| T939 |
/workspace/coverage/default/40.sram_ctrl_bijection.1975144523 |
|
|
Jul 17 07:41:33 PM PDT 24 |
Jul 17 07:42:05 PM PDT 24 |
7238863654 ps |
| T940 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2418119629 |
|
|
Jul 17 07:38:54 PM PDT 24 |
Jul 17 07:38:59 PM PDT 24 |
67223784 ps |
| T941 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.2627626775 |
|
|
Jul 17 07:40:32 PM PDT 24 |
Jul 17 07:49:43 PM PDT 24 |
8311335108 ps |
| T942 |
/workspace/coverage/default/46.sram_ctrl_executable.2322784540 |
|
|
Jul 17 07:42:19 PM PDT 24 |
Jul 17 07:47:27 PM PDT 24 |
5246705492 ps |
| T943 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.440283246 |
|
|
Jul 17 07:39:32 PM PDT 24 |
Jul 17 07:43:48 PM PDT 24 |
2706376626 ps |
| T77 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3861478069 |
|
|
Jul 17 06:12:43 PM PDT 24 |
Jul 17 06:12:46 PM PDT 24 |
1203012501 ps |
| T78 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1116004128 |
|
|
Jul 17 06:10:51 PM PDT 24 |
Jul 17 06:10:55 PM PDT 24 |
1016604403 ps |
| T79 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.348108455 |
|
|
Jul 17 06:10:50 PM PDT 24 |
Jul 17 06:10:52 PM PDT 24 |
27274469 ps |
| T82 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1336224673 |
|
|
Jul 17 06:10:54 PM PDT 24 |
Jul 17 06:10:56 PM PDT 24 |
23123824 ps |
| T944 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4227112079 |
|
|
Jul 17 06:10:39 PM PDT 24 |
Jul 17 06:10:44 PM PDT 24 |
134867566 ps |
| T945 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1879545211 |
|
|
Jul 17 06:10:48 PM PDT 24 |
Jul 17 06:10:50 PM PDT 24 |
35573889 ps |
| T124 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2645683797 |
|
|
Jul 17 06:12:44 PM PDT 24 |
Jul 17 06:12:48 PM PDT 24 |
453730145 ps |
| T125 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3273587278 |
|
|
Jul 17 06:10:42 PM PDT 24 |
Jul 17 06:10:44 PM PDT 24 |
38209032 ps |
| T946 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1086908645 |
|
|
Jul 17 06:11:00 PM PDT 24 |
Jul 17 06:11:02 PM PDT 24 |
119789346 ps |
| T143 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.555150646 |
|
|
Jul 17 06:10:51 PM PDT 24 |
Jul 17 06:10:56 PM PDT 24 |
259278219 ps |
| T126 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.116732955 |
|
|
Jul 17 06:10:58 PM PDT 24 |
Jul 17 06:11:00 PM PDT 24 |
27977419 ps |
| T127 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1432498946 |
|
|
Jul 17 06:10:38 PM PDT 24 |
Jul 17 06:10:41 PM PDT 24 |
170441897 ps |
| T83 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.81887317 |
|
|
Jul 17 06:10:50 PM PDT 24 |
Jul 17 06:10:54 PM PDT 24 |
384044866 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3239888184 |
|
|
Jul 17 06:12:59 PM PDT 24 |
Jul 17 06:13:01 PM PDT 24 |
75480145 ps |
| T84 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3935573761 |
|
|
Jul 17 06:15:03 PM PDT 24 |
Jul 17 06:15:06 PM PDT 24 |
64107662 ps |
| T119 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.66375582 |
|
|
Jul 17 06:11:03 PM PDT 24 |
Jul 17 06:11:04 PM PDT 24 |
57964992 ps |
| T73 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3966173239 |
|
|
Jul 17 06:11:01 PM PDT 24 |
Jul 17 06:11:03 PM PDT 24 |
342277170 ps |
| T85 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3500765484 |
|
|
Jul 17 06:11:17 PM PDT 24 |
Jul 17 06:11:19 PM PDT 24 |
111213157 ps |
| T948 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.138825383 |
|
|
Jul 17 06:10:53 PM PDT 24 |
Jul 17 06:10:58 PM PDT 24 |
485216443 ps |
| T86 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1830033961 |
|
|
Jul 17 06:10:50 PM PDT 24 |
Jul 17 06:10:52 PM PDT 24 |
105610629 ps |
| T120 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2670192457 |
|
|
Jul 17 06:11:16 PM PDT 24 |
Jul 17 06:11:17 PM PDT 24 |
94182473 ps |
| T121 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3176579280 |
|
|
Jul 17 06:10:59 PM PDT 24 |
Jul 17 06:11:02 PM PDT 24 |
13954090 ps |
| T949 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3309589267 |
|
|
Jul 17 06:11:14 PM PDT 24 |
Jul 17 06:11:16 PM PDT 24 |
135573490 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3653648738 |
|
|
Jul 17 06:15:12 PM PDT 24 |
Jul 17 06:15:14 PM PDT 24 |
89151876 ps |
| T951 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3723516034 |
|
|
Jul 17 06:13:05 PM PDT 24 |
Jul 17 06:13:07 PM PDT 24 |
29489394 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1287123853 |
|
|
Jul 17 06:10:42 PM PDT 24 |
Jul 17 06:10:44 PM PDT 24 |
183401360 ps |
| T88 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2967590481 |
|
|
Jul 17 06:10:39 PM PDT 24 |
Jul 17 06:10:41 PM PDT 24 |
34607167 ps |
| T952 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2475671933 |
|
|
Jul 17 06:13:02 PM PDT 24 |
Jul 17 06:13:04 PM PDT 24 |
28793104 ps |
| T953 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1463303272 |
|
|
Jul 17 06:10:58 PM PDT 24 |
Jul 17 06:10:59 PM PDT 24 |
17126504 ps |
| T954 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.632776051 |
|
|
Jul 17 06:10:49 PM PDT 24 |
Jul 17 06:10:51 PM PDT 24 |
42105409 ps |
| T955 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4072584702 |
|
|
Jul 17 06:15:12 PM PDT 24 |
Jul 17 06:15:15 PM PDT 24 |
152206301 ps |
| T956 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3127986319 |
|
|
Jul 17 06:20:08 PM PDT 24 |
Jul 17 06:20:10 PM PDT 24 |
63333386 ps |
| T89 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.190307612 |
|
|
Jul 17 06:10:40 PM PDT 24 |
Jul 17 06:10:43 PM PDT 24 |
28899538 ps |
| T957 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.505067518 |
|
|
Jul 17 06:10:48 PM PDT 24 |
Jul 17 06:10:50 PM PDT 24 |
29893665 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1438023861 |
|
|
Jul 17 06:10:39 PM PDT 24 |
Jul 17 06:10:41 PM PDT 24 |
16434298 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4166590602 |
|
|
Jul 17 06:10:53 PM PDT 24 |
Jul 17 06:10:55 PM PDT 24 |
28899370 ps |
| T960 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3821214507 |
|
|
Jul 17 06:11:01 PM PDT 24 |
Jul 17 06:11:04 PM PDT 24 |
126745275 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2465794548 |
|
|
Jul 17 06:10:41 PM PDT 24 |
Jul 17 06:10:43 PM PDT 24 |
23783388 ps |
| T74 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.424161200 |
|
|
Jul 17 06:12:45 PM PDT 24 |
Jul 17 06:12:48 PM PDT 24 |
160874364 ps |
| T962 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1555682590 |
|
|
Jul 17 06:10:42 PM PDT 24 |
Jul 17 06:10:44 PM PDT 24 |
12757078 ps |
| T963 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2147986357 |
|
|
Jul 17 06:13:27 PM PDT 24 |
Jul 17 06:13:28 PM PDT 24 |
84434978 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1674637322 |
|
|
Jul 17 06:10:42 PM PDT 24 |
Jul 17 06:10:48 PM PDT 24 |
130087928 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.161216710 |
|
|
Jul 17 06:10:35 PM PDT 24 |
Jul 17 06:10:38 PM PDT 24 |
1569403054 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3281728646 |
|
|
Jul 17 06:10:49 PM PDT 24 |
Jul 17 06:10:52 PM PDT 24 |
114253555 ps |
| T75 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2939005083 |
|
|
Jul 17 06:10:49 PM PDT 24 |
Jul 17 06:10:52 PM PDT 24 |
2115332765 ps |
| T144 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2151427555 |
|
|
Jul 17 06:10:59 PM PDT 24 |
Jul 17 06:11:03 PM PDT 24 |
234659263 ps |
| T966 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1552644767 |
|
|
Jul 17 06:10:53 PM PDT 24 |
Jul 17 06:10:56 PM PDT 24 |
107100145 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3237661895 |
|
|
Jul 17 06:10:46 PM PDT 24 |
Jul 17 06:10:48 PM PDT 24 |
70776697 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.671940150 |
|
|
Jul 17 06:10:51 PM PDT 24 |
Jul 17 06:10:53 PM PDT 24 |
91716393 ps |
| T99 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3753506254 |
|
|
Jul 17 06:20:04 PM PDT 24 |
Jul 17 06:20:05 PM PDT 24 |
43584191 ps |
| T969 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2127796162 |
|
|
Jul 17 06:11:00 PM PDT 24 |
Jul 17 06:11:05 PM PDT 24 |
128479465 ps |
| T100 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3919445771 |
|
|
Jul 17 06:10:59 PM PDT 24 |
Jul 17 06:11:01 PM PDT 24 |
48951338 ps |
| T101 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2388392340 |
|
|
Jul 17 06:10:42 PM PDT 24 |
Jul 17 06:10:44 PM PDT 24 |
23002473 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3393987589 |
|
|
Jul 17 06:20:07 PM PDT 24 |
Jul 17 06:20:12 PM PDT 24 |
982917706 ps |
| T155 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3042143515 |
|
|
Jul 17 06:12:02 PM PDT 24 |
Jul 17 06:12:06 PM PDT 24 |
396519318 ps |
| T148 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3197662419 |
|
|
Jul 17 06:10:51 PM PDT 24 |
Jul 17 06:10:54 PM PDT 24 |
282110261 ps |
| T103 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1176157480 |
|
|
Jul 17 06:12:53 PM PDT 24 |
Jul 17 06:12:55 PM PDT 24 |
17780662 ps |
| T151 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.781778611 |
|
|
Jul 17 06:17:58 PM PDT 24 |
Jul 17 06:18:01 PM PDT 24 |
336198359 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4073416857 |
|
|
Jul 17 06:10:40 PM PDT 24 |
Jul 17 06:10:44 PM PDT 24 |
215237552 ps |
| T110 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3551828940 |
|
|
Jul 17 06:15:14 PM PDT 24 |
Jul 17 06:15:21 PM PDT 24 |
1064767885 ps |
| T111 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1942150923 |
|
|
Jul 17 06:12:02 PM PDT 24 |
Jul 17 06:12:05 PM PDT 24 |
360866072 ps |
| T145 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.662312368 |
|
|
Jul 17 06:10:45 PM PDT 24 |
Jul 17 06:10:49 PM PDT 24 |
479513048 ps |
| T971 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3198533292 |
|
|
Jul 17 06:15:04 PM PDT 24 |
Jul 17 06:15:07 PM PDT 24 |
129633185 ps |
| T112 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2752520100 |
|
|
Jul 17 06:10:59 PM PDT 24 |
Jul 17 06:11:03 PM PDT 24 |
728282229 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.139525385 |
|
|
Jul 17 06:15:28 PM PDT 24 |
Jul 17 06:15:30 PM PDT 24 |
30278990 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2125162827 |
|
|
Jul 17 06:10:38 PM PDT 24 |
Jul 17 06:10:40 PM PDT 24 |
15568114 ps |
| T156 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4156592877 |
|
|
Jul 17 06:10:43 PM PDT 24 |
Jul 17 06:10:46 PM PDT 24 |
115881923 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.823904100 |
|
|
Jul 17 06:10:39 PM PDT 24 |
Jul 17 06:10:42 PM PDT 24 |
522236660 ps |
| T974 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1065858073 |
|
|
Jul 17 06:12:43 PM PDT 24 |
Jul 17 06:12:44 PM PDT 24 |
32919944 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1703228503 |
|
|
Jul 17 06:10:59 PM PDT 24 |
Jul 17 06:11:03 PM PDT 24 |
1833598489 ps |
| T976 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2895941728 |
|
|
Jul 17 06:10:49 PM PDT 24 |
Jul 17 06:10:53 PM PDT 24 |
374640215 ps |
| T113 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2872384251 |
|
|
Jul 17 06:10:50 PM PDT 24 |
Jul 17 06:10:55 PM PDT 24 |
510396497 ps |
| T977 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4162230336 |
|
|
Jul 17 06:20:08 PM PDT 24 |
Jul 17 06:20:09 PM PDT 24 |
66290712 ps |
| T978 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2096728647 |
|
|
Jul 17 06:11:40 PM PDT 24 |
Jul 17 06:11:44 PM PDT 24 |
427594493 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3407438527 |
|
|
Jul 17 06:10:49 PM PDT 24 |
Jul 17 06:10:51 PM PDT 24 |
41116917 ps |
| T980 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3822599060 |
|
|
Jul 17 06:15:14 PM PDT 24 |
Jul 17 06:15:18 PM PDT 24 |
26671895 ps |
| T146 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3026276295 |
|
|
Jul 17 06:12:59 PM PDT 24 |
Jul 17 06:13:03 PM PDT 24 |
448296783 ps |
| T114 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.496028816 |
|
|
Jul 17 06:11:01 PM PDT 24 |
Jul 17 06:11:06 PM PDT 24 |
636310143 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3159282432 |
|
|
Jul 17 06:15:03 PM PDT 24 |
Jul 17 06:15:06 PM PDT 24 |
89288856 ps |
| T982 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3753087848 |
|
|
Jul 17 06:11:00 PM PDT 24 |
Jul 17 06:11:02 PM PDT 24 |
194459367 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3284921526 |
|
|
Jul 17 06:10:43 PM PDT 24 |
Jul 17 06:10:46 PM PDT 24 |
84930618 ps |
| T984 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.420129744 |
|
|
Jul 17 06:13:00 PM PDT 24 |
Jul 17 06:13:07 PM PDT 24 |
520729046 ps |
| T985 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1508274745 |
|
|
Jul 17 06:18:12 PM PDT 24 |
Jul 17 06:18:17 PM PDT 24 |
790524539 ps |
| T152 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3851613732 |
|
|
Jul 17 06:15:13 PM PDT 24 |
Jul 17 06:15:18 PM PDT 24 |
173365770 ps |
| T986 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3770699280 |
|
|
Jul 17 06:18:12 PM PDT 24 |
Jul 17 06:18:14 PM PDT 24 |
44912995 ps |
| T115 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2499055136 |
|
|
Jul 17 06:10:59 PM PDT 24 |
Jul 17 06:11:03 PM PDT 24 |
1037403426 ps |
| T987 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1213489393 |
|
|
Jul 17 06:10:41 PM PDT 24 |
Jul 17 06:10:44 PM PDT 24 |
32861387 ps |
| T988 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.546245377 |
|
|
Jul 17 06:20:10 PM PDT 24 |
Jul 17 06:20:12 PM PDT 24 |
37948969 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1195885773 |
|
|
Jul 17 06:10:49 PM PDT 24 |
Jul 17 06:10:51 PM PDT 24 |
701761904 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1951065211 |
|
|
Jul 17 06:16:06 PM PDT 24 |
Jul 17 06:16:11 PM PDT 24 |
43690748 ps |
| T991 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.15910398 |
|
|
Jul 17 06:15:13 PM PDT 24 |
Jul 17 06:15:17 PM PDT 24 |
39417853 ps |
| T157 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.991969356 |
|
|
Jul 17 06:12:02 PM PDT 24 |
Jul 17 06:12:04 PM PDT 24 |
297563702 ps |
| T992 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2160099520 |
|
|
Jul 17 06:10:50 PM PDT 24 |
Jul 17 06:10:57 PM PDT 24 |
1054129089 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2450674378 |
|
|
Jul 17 06:10:39 PM PDT 24 |
Jul 17 06:10:43 PM PDT 24 |
338791725 ps |
| T994 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1955657388 |
|
|
Jul 17 06:13:00 PM PDT 24 |
Jul 17 06:13:01 PM PDT 24 |
33515145 ps |
| T995 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1436159186 |
|
|
Jul 17 06:15:06 PM PDT 24 |
Jul 17 06:15:10 PM PDT 24 |
25360518 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3170274199 |
|
|
Jul 17 06:10:39 PM PDT 24 |
Jul 17 06:10:41 PM PDT 24 |
53122575 ps |
| T997 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.247733217 |
|
|
Jul 17 06:18:12 PM PDT 24 |
Jul 17 06:18:16 PM PDT 24 |
143682068 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3662892658 |
|
|
Jul 17 06:12:45 PM PDT 24 |
Jul 17 06:12:47 PM PDT 24 |
14527343 ps |
| T116 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3663355745 |
|
|
Jul 17 06:11:06 PM PDT 24 |
Jul 17 06:11:08 PM PDT 24 |
98765702 ps |
| T999 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1273801458 |
|
|
Jul 17 06:10:48 PM PDT 24 |
Jul 17 06:10:49 PM PDT 24 |
81907148 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3268894972 |
|
|
Jul 17 06:10:51 PM PDT 24 |
Jul 17 06:10:56 PM PDT 24 |
120957441 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1358157753 |
|
|
Jul 17 06:10:58 PM PDT 24 |
Jul 17 06:11:00 PM PDT 24 |
87973129 ps |
| T1002 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1634141185 |
|
|
Jul 17 06:17:55 PM PDT 24 |
Jul 17 06:18:00 PM PDT 24 |
2031047602 ps |
| T117 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2222828342 |
|
|
Jul 17 06:20:04 PM PDT 24 |
Jul 17 06:20:07 PM PDT 24 |
223863822 ps |
| T1003 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.446051016 |
|
|
Jul 17 06:10:39 PM PDT 24 |
Jul 17 06:10:43 PM PDT 24 |
634190335 ps |
| T147 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.888557025 |
|
|
Jul 17 06:12:03 PM PDT 24 |
Jul 17 06:12:05 PM PDT 24 |
296394766 ps |
| T1004 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2820666599 |
|
|
Jul 17 06:10:39 PM PDT 24 |
Jul 17 06:10:42 PM PDT 24 |
106710717 ps |
| T109 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1582825263 |
|
|
Jul 17 06:10:39 PM PDT 24 |
Jul 17 06:10:42 PM PDT 24 |
67704899 ps |