Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13872555

1

T2

1000

T3

795

T4

10172

full_word

53694131

1

T1

947

T2

4584

T3

210

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67566356	1			T1	947		T2	5584		T3	1005
auto[TlIntgErrCmd]	113	1			T60	5		T61	7		T62	4
auto[TlIntgErrData]	115	1			T60	8		T61	6		T62	3
auto[TlIntgErrBoth]	102	1			T60	7		T61	7		T62	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31168502

1

T1

469

T2

2754

T3

506

auto[1]

36398184

1

T1

478

T2

2830

T3

499

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6653968	1			T2	482		T3	396		T4	3245
auto[TlIntgErrNone]	partial	auto[1]	7218287	1			T2	518		T3	399		T4	6927
auto[TlIntgErrNone]	full_word	auto[0]	24514377	1			T1	469		T2	2272		T3	110
auto[TlIntgErrNone]	full_word	auto[1]	29179724	1			T1	478		T2	2312		T3	100
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T60	3		T62	1		T125	4
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T60	2		T61	6		T62	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T124	1		T130	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T61	1		T131	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T60	3		T61	4		T62	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T60	5		T61	2		T62	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T132	1		T129	1		T133	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T124	1		T134	2		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T60	3		T61	1		T62	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T60	3		T61	5		T62	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T134	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T60	1		T61	1		T125	1