Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	752855	1			T3	2		T11	27029		T12	11
auto[1]	10696793	1			T1	469		T2	2752		T3	2
auto[2]	621543	1			T11	23087		T12	7		T42	22627
auto[3]	10576097	1			T1	477		T2	2829		T3	1

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14569245	1			T1	946		T2	3739		T4	16415
auto[1]	2174062	1			T2	842		T3	1		T4	1564
auto[2]	2182746	1			T2	814		T4	1537		T8	2134
auto[3]	3721235	1			T2	186		T3	4		T4	139

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8782606

1

T1

944

T2

5576

T3

5

auto[1]

13864682

1

T1

2

T2

5

T4

16

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	257357	1			T12	10		T22	654		T77	17639
auto[0]	auto[0]	auto[1]	26383	1			T3	1		T43	2		T22	72
auto[0]	auto[0]	auto[2]	26264	1			T12	1		T43	1		T22	65
auto[0]	auto[0]	auto[3]	8728	1			T3	1		T43	1		T22	8
auto[0]	auto[1]	auto[0]	3351023	1			T1	468		T2	1853		T4	8205
auto[0]	auto[1]	auto[1]	347682	1			T2	416		T4	745		T8	1001
auto[0]	auto[1]	auto[2]	339202	1			T2	387		T4	811		T8	1107
auto[0]	auto[1]	auto[3]	72903	1			T2	94		T3	2		T4	66
auto[0]	auto[2]	auto[0]	219533	1			T22	569		T77	16096		T79	3
auto[0]	auto[2]	auto[1]	22690	1			T22	59		T77	1625		T79	17
auto[0]	auto[2]	auto[2]	25001	1			T12	7		T22	57		T77	1212
auto[0]	auto[2]	auto[3]	7083	1			T43	1		T22	4		T77	125
auto[0]	auto[3]	auto[0]	3318160	1			T1	476		T2	1885		T4	8197
auto[0]	auto[3]	auto[1]	336770	1			T2	425		T4	817		T8	1142
auto[0]	auto[3]	auto[2]	348986	1			T2	424		T4	725		T8	1027
auto[0]	auto[3]	auto[3]	74841	1			T2	92		T3	1		T4	73
auto[1]	auto[0]	auto[0]	14559	1			T11	873		T42	1005		T77	14
auto[1]	auto[0]	auto[1]	64607	1			T11	3940		T42	4707		T78	536
auto[1]	auto[0]	auto[2]	64477	1			T11	3992		T42	4534		T77	4
auto[1]	auto[0]	auto[3]	290480	1			T11	18224		T42	21130		T78	2570
auto[1]	auto[1]	auto[0]	3702200	1			T1	1		T4	4		T8	10
auto[1]	auto[1]	auto[1]	682818	1			T2	1		T8	1		T9	2
auto[1]	auto[1]	auto[2]	657865	1			T2	1		T4	1		T9	5
auto[1]	auto[1]	auto[3]	1543100	1			T11	18164		T44	4		T64	1
auto[1]	auto[2]	auto[0]	11212	1			T11	860		T42	946		T77	13
auto[1]	auto[2]	auto[1]	50058	1			T11	3660		T42	4359		T77	1
auto[1]	auto[2]	auto[2]	52139	1			T11	3419		T42	3151		T77	2
auto[1]	auto[2]	auto[3]	233827	1			T11	15148		T42	14171		T78	2297
auto[1]	auto[3]	auto[0]	3695201	1			T1	1		T2	1		T4	9
auto[1]	auto[3]	auto[1]	643054	1			T4	2		T8	1		T11	323
auto[1]	auto[3]	auto[2]	668812	1			T2	2		T9	2		T11	3450
auto[1]	auto[3]	auto[3]	1490273	1			T8	1		T11	15242		T44	2