Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	314570548	183782	0	0
ctrl_regwen_rd_A	314570548	5439	0	0
exec_rd_A	314570548	5108	0	0
exec_regwen_rd_A	314570548	5291	0	0
readback_rd_A	314570548	2816	0	0
readback_regwen_rd_A	314570548	2450	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314570548	183782	0	0
T4	106470	5278	0	0
T8	192472	0	0	0
T9	223084	0	0	0
T10	26408	0	0	0
T11	162260	0	0	0
T12	439937	0	0	0
T13	9191	0	0	0
T20	146082	7257	0	0
T25	0	3312	0	0
T29	4324	0	0	0
T44	20179	0	0	0
T52	0	1918	0	0
T53	0	3439	0	0
T57	0	1773	0	0
T59	0	2210	0	0
T68	0	4700	0	0
T69	0	8410	0	0
T70	0	1181	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314570548	5439	0	0
T7	53653	0	0	0
T39	0	116	0	0
T48	0	411	0	0
T49	0	154	0	0
T53	149716	319	0	0
T59	0	166	0	0
T69	133083	0	0	0
T70	0	100	0	0
T71	112835	0	0	0
T114	0	116	0	0
T115	0	368	0	0
T116	0	230	0	0
T117	0	132	0	0
T118	2524	0	0	0
T119	218908	0	0	0
T120	9579	0	0	0
T121	1444	0	0	0
T122	14026	0	0	0
T123	9343	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314570548	5108	0	0
T7	53653	0	0	0
T39	0	247	0	0
T48	0	312	0	0
T49	0	121	0	0
T53	149716	240	0	0
T59	0	215	0	0
T69	133083	0	0	0
T70	0	87	0	0
T71	112835	0	0	0
T114	0	121	0	0
T115	0	307	0	0
T116	0	204	0	0
T117	0	137	0	0
T118	2524	0	0	0
T119	218908	0	0	0
T120	9579	0	0	0
T121	1444	0	0	0
T122	14026	0	0	0
T123	9343	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314570548	5291	0	0
T7	53653	0	0	0
T39	0	197	0	0
T48	0	340	0	0
T49	0	93	0	0
T53	149716	283	0	0
T59	0	160	0	0
T69	133083	0	0	0
T70	0	86	0	0
T71	112835	0	0	0
T114	0	76	0	0
T115	0	308	0	0
T116	0	198	0	0
T117	0	181	0	0
T118	2524	0	0	0
T119	218908	0	0	0
T120	9579	0	0	0
T121	1444	0	0	0
T122	14026	0	0	0
T123	9343	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314570548	2816	0	0
T7	53653	0	0	0
T39	0	105	0	0
T48	0	322	0	0
T49	0	74	0	0
T53	149716	321	0	0
T59	0	180	0	0
T69	133083	0	0	0
T70	0	50	0	0
T71	112835	0	0	0
T114	0	44	0	0
T115	0	269	0	0
T116	0	214	0	0
T117	0	139	0	0
T118	2524	0	0	0
T119	218908	0	0	0
T120	9579	0	0	0
T121	1444	0	0	0
T122	14026	0	0	0
T123	9343	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314570548	2450	0	0
T7	53653	0	0	0
T39	0	98	0	0
T48	0	265	0	0
T49	0	75	0	0
T53	149716	232	0	0
T59	0	113	0	0
T69	133083	0	0	0
T70	0	43	0	0
T71	112835	0	0	0
T114	0	65	0	0
T115	0	273	0	0
T116	0	251	0	0
T117	0	146	0	0
T118	2524	0	0	0
T119	218908	0	0	0
T120	9579	0	0	0
T121	1444	0	0	0
T122	14026	0	0	0
T123	9343	0	0	0