Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13620324	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

55944468

1

T1

59081

T2

240795

T3

8123

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34672676	1			T1	32498		T2	132782		T3	4103
values[0x0]	16082031	1			T1	15574		T2	63076		T3	2016
values[0x1]	18810085	1			T1	16848		T2	69091		T3	2004

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6788042	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62776750

1

T1

62021

T2

252873

T3

8123

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	249090	1			T1	48		T2	1125		T5	90
valid_sources[0x01]	291755	1			T1	108		T2	1029		T5	87
valid_sources[0x02]	322713	1			T1	80		T2	1002		T5	98
valid_sources[0x03]	241660	1			T1	77		T2	956		T5	107
valid_sources[0x04]	282319	1			T1	60		T2	1086		T5	92
valid_sources[0x05]	294389	1			T1	146		T2	1082		T5	96
valid_sources[0x06]	265677	1			T1	87		T2	1081		T3	4061
valid_sources[0x07]	264971	1			T1	93		T2	1076		T5	112
valid_sources[0x08]	252612	1			T1	50		T2	1000		T5	113
valid_sources[0x09]	261726	1			T1	97		T2	989		T5	95
valid_sources[0x0a]	271473	1			T1	154		T2	978		T5	91
valid_sources[0x0b]	253353	1			T1	76		T2	1048		T5	97
valid_sources[0x0c]	278685	1			T1	139		T2	1061		T5	115
valid_sources[0x0d]	268493	1			T1	91		T2	938		T5	92
valid_sources[0x0e]	280050	1			T1	92		T2	1019		T5	104
valid_sources[0x0f]	291623	1			T1	101		T2	1028		T5	90
valid_sources[0x10]	274352	1			T1	121		T2	851		T5	92
valid_sources[0x11]	258403	1			T1	80		T2	914		T5	83
valid_sources[0x12]	269494	1			T1	98		T2	1072		T5	107
valid_sources[0x13]	256987	1			T1	29		T2	1009		T3	4062
valid_sources[0x14]	325817	1			T1	111		T2	954		T5	104
valid_sources[0x15]	323288	1			T1	99		T2	921		T5	80
valid_sources[0x16]	242321	1			T1	61		T2	1036		T5	104
valid_sources[0x17]	341785	1			T1	97		T2	1134		T5	97
valid_sources[0x18]	256198	1			T1	58		T2	978		T5	103
valid_sources[0x19]	260960	1			T1	104		T2	1051		T5	97
valid_sources[0x1a]	254811	1			T1	62		T2	1015		T5	95
valid_sources[0x1b]	243724	1			T1	97		T2	1071		T5	111
valid_sources[0x1c]	256098	1			T1	44		T2	1016		T5	101
valid_sources[0x1d]	255007	1			T1	53		T2	1041		T5	67
valid_sources[0x1e]	249315	1			T1	147		T2	1004		T5	101
valid_sources[0x1f]	271242	1			T1	75		T2	964		T5	84
valid_sources[0x20]	324437	1			T1	23066		T2	936		T5	104
valid_sources[0x21]	244187	1			T1	23		T2	1016		T5	93
valid_sources[0x22]	252427	1			T1	121		T2	933		T5	93
valid_sources[0x23]	269749	1			T1	78		T2	857		T5	108
valid_sources[0x24]	284936	1			T1	84		T2	1117		T5	100
valid_sources[0x25]	262538	1			T1	79		T2	1076		T5	100
valid_sources[0x26]	249535	1			T1	90		T2	1080		T5	84
valid_sources[0x27]	259159	1			T1	119		T2	1119		T5	99
valid_sources[0x28]	276451	1			T1	138		T2	1020		T5	102
valid_sources[0x29]	312990	1			T1	77		T2	1063		T5	88
valid_sources[0x2a]	252242	1			T1	79		T2	989		T5	98
valid_sources[0x2b]	236287	1			T1	52		T2	979		T5	76
valid_sources[0x2c]	248471	1			T1	49		T2	940		T5	100
valid_sources[0x2d]	252218	1			T1	62		T2	1091		T5	109
valid_sources[0x2e]	300822	1			T1	81		T2	970		T5	91
valid_sources[0x2f]	246179	1			T1	174		T2	1016		T5	99
valid_sources[0x30]	241920	1			T1	126		T2	1085		T5	101
valid_sources[0x31]	266321	1			T1	88		T2	1049		T5	102
valid_sources[0x32]	271055	1			T1	91		T2	1077		T5	91
valid_sources[0x33]	285583	1			T1	95		T2	1110		T5	75
valid_sources[0x34]	330308	1			T1	63		T2	987		T5	97
valid_sources[0x35]	255630	1			T1	46		T2	1053		T5	97
valid_sources[0x36]	282253	1			T1	8501		T2	1034		T5	108
valid_sources[0x37]	288600	1			T1	93		T2	906		T5	80
valid_sources[0x38]	317451	1			T1	51		T2	1204		T5	90
valid_sources[0x39]	251671	1			T1	91		T2	969		T5	100
valid_sources[0x3a]	259263	1			T1	130		T2	1070		T5	91
valid_sources[0x3b]	307910	1			T1	93		T2	950		T5	124
valid_sources[0x3c]	289554	1			T1	64		T2	1033		T5	93
valid_sources[0x3d]	314174	1			T1	59		T2	1111		T5	122
valid_sources[0x3e]	261127	1			T1	68		T2	1220		T5	101
valid_sources[0x3f]	287299	1			T1	103		T2	967		T5	110
valid_sources[0x40]	257592	1			T1	106		T2	1136		T5	101
valid_sources[0x41]	251114	1			T1	99		T2	1104		T5	96
valid_sources[0x42]	246296	1			T1	96		T2	1033		T5	91
valid_sources[0x43]	268159	1			T1	81		T2	1076		T5	70
valid_sources[0x44]	237220	1			T1	47		T2	1038		T5	107
valid_sources[0x45]	252294	1			T1	145		T2	955		T5	91
valid_sources[0x46]	293014	1			T1	113		T2	1028		T5	112
valid_sources[0x47]	293291	1			T1	91		T2	995		T5	90
valid_sources[0x48]	288030	1			T1	112		T2	1006		T5	104
valid_sources[0x49]	257458	1			T1	56		T2	974		T5	94
valid_sources[0x4a]	253458	1			T1	38		T2	1214		T5	107
valid_sources[0x4b]	264537	1			T1	66		T2	1031		T5	95
valid_sources[0x4c]	244440	1			T1	85		T2	1079		T5	85
valid_sources[0x4d]	255968	1			T1	87		T2	1080		T5	112
valid_sources[0x4e]	313178	1			T1	109		T2	1010		T5	92
valid_sources[0x4f]	252134	1			T1	127		T2	906		T5	83
valid_sources[0x50]	285095	1			T1	60		T2	989		T5	90
valid_sources[0x51]	245699	1			T1	64		T2	1135		T5	99
valid_sources[0x52]	275455	1			T1	108		T2	995		T5	87
valid_sources[0x53]	263960	1			T1	45		T2	914		T5	105
valid_sources[0x54]	256311	1			T1	95		T2	988		T5	81
valid_sources[0x55]	280772	1			T1	53		T2	987		T5	111
valid_sources[0x56]	301385	1			T1	59		T2	1054		T5	80
valid_sources[0x57]	265785	1			T1	49		T2	1012		T5	95
valid_sources[0x58]	239764	1			T1	89		T2	1075		T5	87
valid_sources[0x59]	243682	1			T1	130		T2	1079		T5	84
valid_sources[0x5a]	281569	1			T1	86		T2	1092		T5	90
valid_sources[0x5b]	325272	1			T1	103		T2	1076		T5	91
valid_sources[0x5c]	257116	1			T1	78		T2	972		T5	96
valid_sources[0x5d]	300530	1			T1	97		T2	894		T5	92
valid_sources[0x5e]	253434	1			T1	82		T2	1076		T5	92
valid_sources[0x5f]	247740	1			T1	88		T2	1045		T5	94
valid_sources[0x60]	302544	1			T1	37		T2	952		T5	89
valid_sources[0x61]	288244	1			T1	121		T2	1030		T5	114
valid_sources[0x62]	260114	1			T1	89		T2	1124		T5	91
valid_sources[0x63]	245986	1			T1	73		T2	1017		T5	100
valid_sources[0x64]	249070	1			T1	81		T2	943		T5	91
valid_sources[0x65]	272359	1			T1	27		T2	1040		T5	111
valid_sources[0x66]	321969	1			T1	115		T2	1145		T5	85
valid_sources[0x67]	265788	1			T1	29		T2	1176		T5	80
valid_sources[0x68]	273791	1			T1	101		T2	1053		T5	106
valid_sources[0x69]	261438	1			T1	103		T2	1030		T5	108
valid_sources[0x6a]	264435	1			T1	60		T2	1008		T5	96
valid_sources[0x6b]	253057	1			T1	38		T2	1019		T5	101
valid_sources[0x6c]	267788	1			T1	61		T2	992		T5	103
valid_sources[0x6d]	371515	1			T1	88		T2	1067		T5	117
valid_sources[0x6e]	257140	1			T1	116		T2	1254		T5	91
valid_sources[0x6f]	267499	1			T1	160		T2	1080		T5	97
valid_sources[0x70]	238579	1			T1	84		T2	1148		T5	89
valid_sources[0x71]	283697	1			T1	107		T2	1050		T5	95
valid_sources[0x72]	245513	1			T1	143		T2	1143		T5	90
valid_sources[0x73]	314234	1			T1	81		T2	1146		T5	96
valid_sources[0x74]	269021	1			T1	101		T2	927		T5	119
valid_sources[0x75]	268181	1			T1	58		T2	961		T5	82
valid_sources[0x76]	241266	1			T1	65		T2	974		T5	88
valid_sources[0x77]	280534	1			T1	95		T2	986		T5	99
valid_sources[0x78]	260410	1			T1	112		T2	887		T5	105
valid_sources[0x79]	269732	1			T1	40		T2	1128		T5	96
valid_sources[0x7a]	285038	1			T1	103		T2	1012		T5	89
valid_sources[0x7b]	258725	1			T1	74		T2	1141		T5	67
valid_sources[0x7c]	259139	1			T1	69		T2	953		T5	90
valid_sources[0x7d]	244891	1			T1	58		T2	997		T5	107
valid_sources[0x7e]	249314	1			T1	54		T2	1004		T5	92
valid_sources[0x7f]	257445	1			T1	96		T2	1056		T5	93
valid_sources[0x80]	277703	1			T1	123		T2	1141		T5	87

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27866504

1

T1

29593

T2

120731

T3

4103

values[0x0]

all_enables

biggest_size

14038179

1

T1

14710

T2

59540

T3

2016

values[0x1]

all_enables

biggest_size

14039785

1

T1

14778

T2

60524

T3

2004

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35139	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118858

1

T1

4

T2

9

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46079	1			T11	8		T27	15		T21	14
values[0x0]	52158	1			T1	3		T2	25		T3	1
values[0x1]	55760	1			T1	6		T2	31		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26822	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

127175

1

T1

6

T2

16

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	820	1			T21	1		T8	1		T22	1
valid_sources[0x01]	499	1			T1	5		T27	4		T22	3
valid_sources[0x02]	809	1			T44	1		T21	1		T8	3
valid_sources[0x03]	880	1			T22	8		T25	5		T26	7
valid_sources[0x04]	710	1			T13	1		T21	1		T142	1
valid_sources[0x05]	526	1			T27	1		T21	1		T22	8
valid_sources[0x06]	445	1			T11	42		T13	1		T21	1
valid_sources[0x07]	353	1			T22	7		T25	10		T26	5
valid_sources[0x08]	481	1			T22	7		T25	4		T26	5
valid_sources[0x09]	628	1			T44	2		T21	1		T22	7
valid_sources[0x0a]	902	1			T27	1		T22	1		T25	7
valid_sources[0x0b]	447	1			T21	1		T22	5		T25	5
valid_sources[0x0c]	645	1			T27	2		T22	2		T25	6
valid_sources[0x0d]	449	1			T22	2		T25	12		T26	1
valid_sources[0x0e]	738	1			T45	1		T22	3		T68	1
valid_sources[0x0f]	673	1			T22	3		T25	3		T143	1
valid_sources[0x10]	797	1			T2	2		T22	3		T25	10
valid_sources[0x11]	599	1			T27	1		T45	1		T22	6
valid_sources[0x12]	640	1			T5	12		T22	2		T25	4
valid_sources[0x13]	904	1			T21	1		T22	2		T25	7
valid_sources[0x14]	629	1			T44	1		T22	11		T25	3
valid_sources[0x15]	452	1			T44	1		T21	1		T22	5
valid_sources[0x16]	506	1			T44	2		T21	1		T8	1
valid_sources[0x17]	605	1			T22	3		T25	10		T26	2
valid_sources[0x18]	664	1			T45	1		T22	4		T25	8
valid_sources[0x19]	760	1			T21	1		T22	6		T25	2
valid_sources[0x1a]	452	1			T27	1		T44	1		T22	4
valid_sources[0x1b]	704	1			T22	5		T25	1		T26	18
valid_sources[0x1c]	767	1			T2	1		T21	1		T61	1
valid_sources[0x1d]	1058	1			T80	5		T21	2		T8	1
valid_sources[0x1e]	772	1			T8	1		T22	6		T25	1
valid_sources[0x1f]	645	1			T27	1		T22	4		T25	4
valid_sources[0x20]	545	1			T3	2		T27	1		T44	1
valid_sources[0x21]	719	1			T22	6		T25	1		T26	17
valid_sources[0x22]	912	1			T2	2		T61	1		T22	2
valid_sources[0x23]	455	1			T21	1		T22	1		T68	1
valid_sources[0x24]	624	1			T13	1		T43	2		T44	2
valid_sources[0x25]	437	1			T44	1		T22	8		T25	1
valid_sources[0x26]	700	1			T27	1		T22	6		T25	6
valid_sources[0x27]	573	1			T22	6		T25	6		T26	4
valid_sources[0x28]	693	1			T21	1		T22	4		T25	6
valid_sources[0x29]	402	1			T21	1		T22	2		T25	2
valid_sources[0x2a]	451	1			T27	1		T14	1		T22	5
valid_sources[0x2b]	454	1			T27	1		T14	3		T45	1
valid_sources[0x2c]	442	1			T1	1		T27	1		T22	6
valid_sources[0x2d]	512	1			T22	2		T25	8		T26	5
valid_sources[0x2e]	743	1			T13	1		T61	1		T45	2
valid_sources[0x2f]	635	1			T8	1		T22	5		T68	1
valid_sources[0x30]	497	1			T61	1		T22	4		T25	6
valid_sources[0x31]	487	1			T21	2		T45	1		T22	2
valid_sources[0x32]	445	1			T22	3		T25	14		T26	11
valid_sources[0x33]	625	1			T112	2		T22	4		T25	6
valid_sources[0x34]	852	1			T8	1		T22	5		T25	10
valid_sources[0x35]	693	1			T2	2		T25	4		T26	5
valid_sources[0x36]	363	1			T75	1		T22	8		T25	12
valid_sources[0x37]	791	1			T13	1		T8	1		T45	1
valid_sources[0x38]	459	1			T22	3		T68	1		T25	10
valid_sources[0x39]	785	1			T21	3		T22	2		T25	2
valid_sources[0x3a]	544	1			T22	5		T25	4		T83	5
valid_sources[0x3b]	812	1			T44	1		T25	7		T26	1
valid_sources[0x3c]	414	1			T22	2		T25	4		T144	5
valid_sources[0x3d]	771	1			T68	1		T25	10		T26	2
valid_sources[0x3e]	402	1			T4	1		T21	1		T22	7
valid_sources[0x3f]	476	1			T13	2		T44	1		T22	4
valid_sources[0x40]	634	1			T27	1		T22	3		T25	3
valid_sources[0x41]	982	1			T22	7		T25	5		T26	8
valid_sources[0x42]	1116	1			T27	1		T20	1		T21	1
valid_sources[0x43]	669	1			T20	1		T22	6		T68	1
valid_sources[0x44]	547	1			T21	1		T8	1		T22	1
valid_sources[0x45]	513	1			T27	1		T22	8		T68	1
valid_sources[0x46]	553	1			T27	1		T75	1		T21	1
valid_sources[0x47]	792	1			T20	1		T22	7		T25	12
valid_sources[0x48]	582	1			T2	3		T30	1		T45	1
valid_sources[0x49]	526	1			T22	4		T25	5		T26	11
valid_sources[0x4a]	640	1			T22	1		T25	3		T83	1
valid_sources[0x4b]	603	1			T27	4		T21	1		T22	1
valid_sources[0x4c]	505	1			T22	4		T68	1		T25	8
valid_sources[0x4d]	571	1			T13	1		T45	1		T22	2
valid_sources[0x4e]	428	1			T75	1		T21	1		T25	14
valid_sources[0x4f]	395	1			T44	1		T45	1		T22	3
valid_sources[0x50]	423	1			T22	2		T25	1		T26	4
valid_sources[0x51]	489	1			T22	5		T25	3		T26	19
valid_sources[0x52]	677	1			T8	2		T68	1		T25	6
valid_sources[0x53]	539	1			T27	3		T44	1		T45	2
valid_sources[0x54]	588	1			T21	1		T22	3		T25	4
valid_sources[0x55]	593	1			T27	1		T8	3		T22	8
valid_sources[0x56]	590	1			T2	1		T13	1		T22	7
valid_sources[0x57]	524	1			T21	2		T8	1		T22	6
valid_sources[0x58]	984	1			T27	2		T14	1		T21	1
valid_sources[0x59]	391	1			T13	1		T21	2		T22	4
valid_sources[0x5a]	616	1			T22	3		T25	2		T145	1
valid_sources[0x5b]	727	1			T61	1		T45	1		T22	1
valid_sources[0x5c]	416	1			T44	1		T21	1		T22	10
valid_sources[0x5d]	734	1			T13	1		T22	3		T25	3
valid_sources[0x5e]	503	1			T21	1		T22	2		T25	10
valid_sources[0x5f]	698	1			T44	1		T21	1		T60	1
valid_sources[0x60]	423	1			T21	1		T22	4		T25	4
valid_sources[0x61]	533	1			T22	9		T25	9		T26	2
valid_sources[0x62]	425	1			T14	1		T22	6		T25	3
valid_sources[0x63]	480	1			T27	2		T21	1		T22	9
valid_sources[0x64]	842	1			T22	4		T25	3		T79	3
valid_sources[0x65]	448	1			T27	1		T61	1		T22	1
valid_sources[0x66]	582	1			T8	2		T45	1		T22	3
valid_sources[0x67]	545	1			T9	2		T21	3		T45	1
valid_sources[0x68]	449	1			T44	2		T20	3		T22	3
valid_sources[0x69]	931	1			T21	1		T22	1		T25	3
valid_sources[0x6a]	340	1			T21	2		T45	1		T22	2
valid_sources[0x6b]	674	1			T27	2		T14	1		T22	6
valid_sources[0x6c]	471	1			T22	3		T68	1		T25	9
valid_sources[0x6d]	787	1			T27	1		T14	1		T21	1
valid_sources[0x6e]	862	1			T21	1		T8	2		T22	7
valid_sources[0x6f]	638	1			T22	2		T25	12		T26	3
valid_sources[0x70]	652	1			T44	1		T45	1		T22	1
valid_sources[0x71]	648	1			T27	2		T21	1		T22	2
valid_sources[0x72]	684	1			T4	1		T27	1		T44	1
valid_sources[0x73]	582	1			T22	4		T25	5		T26	2
valid_sources[0x74]	613	1			T27	1		T44	1		T45	1
valid_sources[0x75]	1099	1			T22	5		T68	1		T25	5
valid_sources[0x76]	444	1			T22	5		T68	1		T25	3
valid_sources[0x77]	528	1			T10	2		T21	2		T22	2
valid_sources[0x78]	439	1			T27	2		T21	2		T22	2
valid_sources[0x79]	693	1			T21	1		T45	1		T22	3
valid_sources[0x7a]	581	1			T44	1		T22	3		T25	5
valid_sources[0x7b]	399	1			T21	1		T22	3		T25	4
valid_sources[0x7c]	609	1			T20	1		T22	1		T25	7
valid_sources[0x7d]	461	1			T21	1		T22	3		T25	4
valid_sources[0x7e]	666	1			T22	1		T25	8		T26	10
valid_sources[0x7f]	839	1			T22	6		T25	4		T26	21
valid_sources[0x80]	545	1			T22	3		T25	5		T26	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33154

1

T11

3

T27

8

T21

6

values[0x0]

all_enables

biggest_size

43850

1

T1

2

T2

6

T5

2

values[0x1]

all_enables

biggest_size

41854

1

T1

2

T2

3

T5

1