Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13323598

1

T1

5839

T2

19378

T4

10475

full_word

51336812

1

T1

59081

T2

192576

T3

8123

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64660100	1			T1	64920		T2	211954		T3	8123
auto[TlIntgErrCmd]	106	1			T72	4		T73	12		T74	6
auto[TlIntgErrData]	100	1			T72	9		T73	3		T74	11
auto[TlIntgErrBoth]	104	1			T72	7		T73	5		T74	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29717773

1

T1

32498

T2

79787

T3

4103

auto[1]

34942637

1

T1

32422

T2

132167

T3

4020

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6385143	1			T1	2905		T2	7275		T4	5172
auto[TlIntgErrNone]	partial	auto[1]	6938186	1			T1	2934		T2	12103		T4	5303
auto[TlIntgErrNone]	full_word	auto[0]	23332480	1			T1	29593		T2	72512		T3	4103
auto[TlIntgErrNone]	full_word	auto[1]	28004291	1			T1	29488		T2	120064		T3	4020
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T72	1		T73	4		T74	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T72	3		T73	5		T74	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T74	1		T133	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T73	3		T74	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T72	4		T73	1		T74	6
auto[TlIntgErrData]	partial	auto[1]	43	1			T72	4		T73	1		T74	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T73	1		T74	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T72	1		T74	2		T140	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T72	2		T140	1		T133	7
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T72	5		T73	1		T74	1
auto[TlIntgErrBoth]	full_word	auto[0]	13	1			T73	3		T136	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T73	1		T74	2		T140	1