Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	536137	1			T1	3113		T2	23		T10	5619
auto[1]	10250734	1			T1	704		T2	581		T3	4102
auto[2]	434096	1			T1	2854		T2	29		T10	4137
auto[3]	10157931	1			T1	427		T2	569		T3	4019

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13937023	1			T1	5483		T2	879		T3	8121
auto[1]	2033248	1			T1	810		T2	111		T4	7618
auto[2]	2058209	1			T1	718		T2	190		T4	7624
auto[3]	3350418	1			T1	87		T2	22		T4	728

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8283248

1

T1

7091

T2

1202

T3

8114

auto[1]

13095650

1

T1

7

T3

7

T4

96288

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	192657	1			T1	2586		T2	22		T11	1204
auto[0]	auto[0]	auto[1]	19867	1			T1	264		T11	131		T13	76
auto[0]	auto[0]	auto[2]	19843	1			T1	245		T2	1		T11	129
auto[0]	auto[0]	auto[3]	5367	1			T1	16		T11	18		T13	2
auto[0]	auto[1]	auto[0]	3217931	1			T1	361		T2	460		T3	4101
auto[0]	auto[1]	auto[1]	330958	1			T1	281		T2	73		T11	120
auto[0]	auto[1]	auto[2]	325007	1			T1	38		T2	41		T11	14
auto[0]	auto[1]	auto[3]	64041	1			T1	24		T2	7		T11	12
auto[0]	auto[2]	auto[0]	158952	1			T1	2358		T11	1160		T13	390
auto[0]	auto[2]	auto[1]	16207	1			T1	251		T11	119		T13	44
auto[0]	auto[2]	auto[2]	20171	1			T1	218		T2	27		T11	80
auto[0]	auto[2]	auto[3]	4804	1			T1	22		T2	2		T11	9
auto[0]	auto[3]	auto[0]	3186349	1			T1	172		T2	397		T3	4013
auto[0]	auto[3]	auto[1]	321753	1			T1	13		T2	38		T11	6
auto[0]	auto[3]	auto[2]	333396	1			T1	217		T2	121		T11	103
auto[0]	auto[3]	auto[3]	65945	1			T1	25		T2	13		T11	8
auto[1]	auto[0]	auto[0]	9822	1			T1	1		T10	171		T11	1
auto[1]	auto[0]	auto[1]	44309	1			T1	1		T10	837		T80	423
auto[1]	auto[0]	auto[2]	44634	1			T10	841		T80	437		T75	432
auto[1]	auto[0]	auto[3]	199638	1			T10	3770		T80	2037		T75	1805
auto[1]	auto[1]	auto[0]	3582667	1			T3	1		T4	40311		T10	310
auto[1]	auto[1]	auto[1]	652440	1			T4	3609		T10	2481		T80	1327
auto[1]	auto[1]	auto[2]	634733	1			T4	3943		T10	1453		T80	761
auto[1]	auto[1]	auto[3]	1442957	1			T4	381		T10	11233		T80	5886
auto[1]	auto[2]	auto[0]	6480	1			T1	5		T11	1		T13	1
auto[1]	auto[2]	auto[1]	28321	1			T11	1		T82	1		T132	2
auto[1]	auto[2]	auto[2]	36277	1			T10	809		T80	401		T75	344
auto[1]	auto[2]	auto[3]	162884	1			T10	3328		T80	1774		T75	1611
auto[1]	auto[3]	auto[0]	3582165	1			T3	6		T4	40007		T10	127
auto[1]	auto[3]	auto[1]	619393	1			T4	4009		T10	672		T80	379
auto[1]	auto[3]	auto[2]	644148	1			T4	3681		T10	2450		T42	1
auto[1]	auto[3]	auto[3]	1404782	1			T4	347		T10	10854		T80	5758