Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	288671770	170905	0	0
ctrl_regwen_rd_A	288671770	3599	0	0
exec_rd_A	288671770	3319	0	0
exec_regwen_rd_A	288671770	3647	0	0
readback_rd_A	288671770	2280	0	0
readback_regwen_rd_A	288671770	1948	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288671770	170905	0	0
T22	23852	1408	0	0
T23	119965	0	0	0
T25	23974	1812	0	0
T26	23334	1722	0	0
T33	0	3413	0	0
T54	0	976	0	0
T56	17321	0	0	0
T58	0	6365	0	0
T59	0	10630	0	0
T66	0	1638	0	0
T68	253645	0	0	0
T69	4914	0	0	0
T70	91236	0	0	0
T71	854086	0	0	0
T79	0	2713	0	0
T81	0	2553	0	0
T82	198095	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288671770	3599	0	0
T24	451927	0	0	0
T33	0	272	0	0
T50	0	223	0	0
T53	9323	0	0	0
T79	148739	258	0	0
T118	0	451	0	0
T119	0	202	0	0
T120	0	118	0	0
T121	0	397	0	0
T122	0	307	0	0
T123	0	138	0	0
T124	0	4	0	0
T125	14194	0	0	0
T126	22933	0	0	0
T127	30293	0	0	0
T128	19115	0	0	0
T129	76188	0	0	0
T130	45806	0	0	0
T131	29076	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288671770	3319	0	0
T24	451927	0	0	0
T33	0	203	0	0
T50	0	197	0	0
T53	9323	0	0	0
T79	148739	295	0	0
T118	0	301	0	0
T119	0	204	0	0
T120	0	115	0	0
T121	0	348	0	0
T122	0	373	0	0
T123	0	189	0	0
T124	0	3	0	0
T125	14194	0	0	0
T126	22933	0	0	0
T127	30293	0	0	0
T128	19115	0	0	0
T129	76188	0	0	0
T130	45806	0	0	0
T131	29076	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288671770	3647	0	0
T24	451927	0	0	0
T33	0	290	0	0
T50	0	222	0	0
T53	9323	0	0	0
T79	148739	225	0	0
T118	0	452	0	0
T119	0	228	0	0
T120	0	138	0	0
T121	0	303	0	0
T122	0	383	0	0
T123	0	194	0	0
T124	0	5	0	0
T125	14194	0	0	0
T126	22933	0	0	0
T127	30293	0	0	0
T128	19115	0	0	0
T129	76188	0	0	0
T130	45806	0	0	0
T131	29076	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288671770	2280	0	0
T24	451927	0	0	0
T33	0	243	0	0
T50	0	190	0	0
T53	9323	0	0	0
T79	148739	153	0	0
T118	0	380	0	0
T119	0	233	0	0
T120	0	90	0	0
T121	0	241	0	0
T122	0	388	0	0
T123	0	122	0	0
T124	0	3	0	0
T125	14194	0	0	0
T126	22933	0	0	0
T127	30293	0	0	0
T128	19115	0	0	0
T129	76188	0	0	0
T130	45806	0	0	0
T131	29076	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288671770	1948	0	0
T24	451927	0	0	0
T33	0	174	0	0
T50	0	187	0	0
T53	9323	0	0	0
T79	148739	160	0	0
T118	0	351	0	0
T119	0	219	0	0
T120	0	34	0	0
T121	0	221	0	0
T122	0	230	0	0
T123	0	148	0	0
T124	0	2	0	0
T125	14194	0	0	0
T126	22933	0	0	0
T127	30293	0	0	0
T128	19115	0	0	0
T129	76188	0	0	0
T130	45806	0	0	0
T131	29076	0	0	0