Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13632987	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58728515

1

T1

6142

T2

267115

T3

39977

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36066078	1			T1	2048		T2	146796		T3	110146
values[0x0]	16788744	1			T1	2045		T2	71123		T3	36706
values[0x1]	19506680	1			T1	2049		T2	75955		T3	73483

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6793281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65568221

1

T1

6142

T2

280633

T3

130760

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	280121	1			T1	40		T2	1168		T3	864
valid_sources[0x01]	330894	1			T1	36		T2	1184		T3	835
valid_sources[0x02]	300726	1			T1	23		T2	1145		T3	868
valid_sources[0x03]	255381	1			T1	11		T2	1199		T3	880
valid_sources[0x04]	317055	1			T1	50		T2	1105		T3	878
valid_sources[0x05]	263512	1			T1	32		T2	1119		T3	962
valid_sources[0x06]	272373	1			T1	23		T2	1113		T3	869
valid_sources[0x07]	282682	1			T1	22		T2	1112		T3	905
valid_sources[0x08]	269266	1			T1	9		T2	1209		T3	921
valid_sources[0x09]	269693	1			T1	34		T2	1176		T3	879
valid_sources[0x0a]	305269	1			T1	13		T2	1202		T3	831
valid_sources[0x0b]	271645	1			T1	16		T2	1162		T3	891
valid_sources[0x0c]	276844	1			T1	4		T2	1156		T3	835
valid_sources[0x0d]	307412	1			T1	35		T2	1089		T3	902
valid_sources[0x0e]	284600	1			T1	33		T2	1081		T3	929
valid_sources[0x0f]	268013	1			T1	38		T2	1182		T3	825
valid_sources[0x10]	249290	1			T1	20		T2	1139		T3	876
valid_sources[0x11]	309382	1			T1	20		T2	1171		T3	868
valid_sources[0x12]	250867	1			T1	24		T2	1169		T3	836
valid_sources[0x13]	297256	1			T1	17		T2	1128		T3	877
valid_sources[0x14]	340031	1			T1	30		T2	1179		T3	893
valid_sources[0x15]	247896	1			T1	34		T2	1117		T3	855
valid_sources[0x16]	307899	1			T1	6		T2	1153		T3	958
valid_sources[0x17]	302975	1			T1	32		T2	1148		T3	850
valid_sources[0x18]	294520	1			T1	29		T2	1157		T3	823
valid_sources[0x19]	319803	1			T1	34		T2	1124		T3	888
valid_sources[0x1a]	258198	1			T1	26		T2	1191		T3	873
valid_sources[0x1b]	286176	1			T1	12		T2	1143		T3	849
valid_sources[0x1c]	279127	1			T1	26		T2	1165		T3	825
valid_sources[0x1d]	263594	1			T1	29		T2	1190		T3	801
valid_sources[0x1e]	332101	1			T1	17		T2	1192		T3	837
valid_sources[0x1f]	274596	1			T1	36		T2	1145		T3	863
valid_sources[0x20]	254319	1			T1	27		T2	1168		T3	858
valid_sources[0x21]	291219	1			T1	23		T2	1222		T3	922
valid_sources[0x22]	257932	1			T1	5		T2	1151		T3	821
valid_sources[0x23]	266472	1			T1	26		T2	1139		T3	812
valid_sources[0x24]	261974	1			T1	24		T2	1136		T3	862
valid_sources[0x25]	268410	1			T1	42		T2	1112		T3	867
valid_sources[0x26]	245756	1			T1	13		T2	1090		T3	820
valid_sources[0x27]	289888	1			T1	25		T2	1152		T3	917
valid_sources[0x28]	261141	1			T1	33		T2	1184		T3	930
valid_sources[0x29]	267637	1			T1	19		T2	1160		T3	853
valid_sources[0x2a]	301824	1			T1	6		T2	1112		T3	838
valid_sources[0x2b]	279769	1			T1	18		T2	1152		T3	874
valid_sources[0x2c]	246494	1			T1	17		T2	1152		T3	859
valid_sources[0x2d]	252579	1			T1	41		T2	1164		T3	895
valid_sources[0x2e]	430586	1			T1	7		T2	1184		T3	890
valid_sources[0x2f]	319472	1			T1	36		T2	1149		T3	852
valid_sources[0x30]	261843	1			T1	10		T2	1161		T3	880
valid_sources[0x31]	280013	1			T1	14		T2	1283		T3	854
valid_sources[0x32]	314136	1			T1	19		T2	1132		T3	922
valid_sources[0x33]	289576	1			T1	33		T2	1109		T3	850
valid_sources[0x34]	260027	1			T1	21		T2	1095		T3	850
valid_sources[0x35]	257499	1			T1	19		T2	1165		T3	851
valid_sources[0x36]	290720	1			T1	35		T2	1119		T3	765
valid_sources[0x37]	314586	1			T1	22		T2	1174		T3	913
valid_sources[0x38]	267594	1			T1	21		T2	1159		T3	921
valid_sources[0x39]	271788	1			T1	24		T2	1191		T3	882
valid_sources[0x3a]	302335	1			T1	15		T2	1119		T3	903
valid_sources[0x3b]	281691	1			T1	26		T2	1164		T3	918
valid_sources[0x3c]	268069	1			T1	13		T2	1135		T3	815
valid_sources[0x3d]	260780	1			T1	27		T2	1147		T3	857
valid_sources[0x3e]	280764	1			T1	28		T2	1161		T3	793
valid_sources[0x3f]	274745	1			T1	44		T2	1109		T3	829
valid_sources[0x40]	266731	1			T1	15		T2	1157		T3	870
valid_sources[0x41]	274910	1			T1	12		T2	1112		T3	917
valid_sources[0x42]	300032	1			T1	40		T2	1132		T3	873
valid_sources[0x43]	263945	1			T1	41		T2	1177		T3	851
valid_sources[0x44]	261628	1			T1	15		T2	1111		T3	825
valid_sources[0x45]	290110	1			T1	18		T2	1097		T3	860
valid_sources[0x46]	304769	1			T1	33		T2	1125		T3	868
valid_sources[0x47]	292631	1			T1	32		T2	1261		T3	852
valid_sources[0x48]	311845	1			T1	47		T2	1124		T3	820
valid_sources[0x49]	273646	1			T1	23		T2	1134		T3	883
valid_sources[0x4a]	316633	1			T1	14		T2	1094		T3	887
valid_sources[0x4b]	270644	1			T1	23		T2	1113		T3	846
valid_sources[0x4c]	323252	1			T1	38		T2	1150		T3	838
valid_sources[0x4d]	292762	1			T1	19		T2	1128		T3	769
valid_sources[0x4e]	266271	1			T1	20		T2	1173		T3	800
valid_sources[0x4f]	312454	1			T1	12		T2	1196		T3	895
valid_sources[0x50]	316206	1			T1	35		T2	1102		T3	882
valid_sources[0x51]	277790	1			T1	20		T2	1148		T3	945
valid_sources[0x52]	262263	1			T1	26		T2	1158		T3	843
valid_sources[0x53]	290184	1			T1	30		T2	1203		T3	851
valid_sources[0x54]	257477	1			T1	42		T2	1112		T3	843
valid_sources[0x55]	263237	1			T1	20		T2	1074		T3	868
valid_sources[0x56]	299392	1			T1	21		T2	1153		T3	850
valid_sources[0x57]	291624	1			T1	22		T2	1150		T3	860
valid_sources[0x58]	277558	1			T1	21		T2	1179		T3	778
valid_sources[0x59]	262589	1			T1	33		T2	1136		T3	842
valid_sources[0x5a]	268530	1			T1	9		T2	1151		T3	823
valid_sources[0x5b]	320001	1			T1	14		T2	1180		T3	852
valid_sources[0x5c]	279030	1			T1	39		T2	1122		T3	854
valid_sources[0x5d]	269718	1			T1	23		T2	1123		T3	852
valid_sources[0x5e]	269327	1			T1	11		T2	1160		T3	912
valid_sources[0x5f]	257093	1			T1	24		T2	1143		T3	849
valid_sources[0x60]	253274	1			T1	46		T2	1149		T3	914
valid_sources[0x61]	305019	1			T1	32		T2	1193		T3	818
valid_sources[0x62]	262787	1			T1	22		T2	1155		T3	822
valid_sources[0x63]	271770	1			T1	26		T2	1191		T3	918
valid_sources[0x64]	256879	1			T1	14		T2	1235		T3	807
valid_sources[0x65]	360446	1			T1	33		T2	1178		T3	865
valid_sources[0x66]	273379	1			T1	26		T2	1081		T3	852
valid_sources[0x67]	288697	1			T1	34		T2	1143		T3	887
valid_sources[0x68]	262990	1			T1	46		T2	1147		T3	824
valid_sources[0x69]	333665	1			T1	17		T2	1181		T3	853
valid_sources[0x6a]	278036	1			T1	36		T2	1183		T3	922
valid_sources[0x6b]	308394	1			T1	42		T2	1071		T3	892
valid_sources[0x6c]	259984	1			T1	16		T2	1131		T3	872
valid_sources[0x6d]	267633	1			T1	22		T2	1153		T3	880
valid_sources[0x6e]	248282	1			T1	34		T2	1069		T3	840
valid_sources[0x6f]	259175	1			T1	11		T2	1170		T3	807
valid_sources[0x70]	290320	1			T1	35		T2	1207		T3	821
valid_sources[0x71]	285923	1			T1	32		T2	1192		T3	794
valid_sources[0x72]	295316	1			T1	17		T2	1182		T3	820
valid_sources[0x73]	378709	1			T1	17		T2	1173		T3	824
valid_sources[0x74]	292879	1			T1	10		T2	1123		T3	820
valid_sources[0x75]	256997	1			T1	29		T2	1128		T3	855
valid_sources[0x76]	271550	1			T1	32		T2	1161		T3	833
valid_sources[0x77]	282915	1			T1	26		T2	1086		T3	821
valid_sources[0x78]	255212	1			T1	40		T2	1108		T3	887
valid_sources[0x79]	274812	1			T1	35		T2	1138		T3	808
valid_sources[0x7a]	317742	1			T1	22		T2	1151		T3	880
valid_sources[0x7b]	255506	1			T1	11		T2	1142		T3	877
valid_sources[0x7c]	253962	1			T1	15		T2	1178		T3	915
valid_sources[0x7d]	251984	1			T1	18		T2	1117		T3	847
valid_sources[0x7e]	268267	1			T1	11		T2	1206		T3	826
valid_sources[0x7f]	323335	1			T1	24		T2	1127		T3	854
valid_sources[0x80]	270601	1			T1	44		T2	1149		T3	906

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29255384

1

T1

2048

T2

133548

T3

19978

values[0x0]

all_enables

biggest_size

14739799

1

T1

2045

T2

67086

T3

9855

values[0x1]

all_enables

biggest_size

14733332

1

T1

2049

T2

66481

T3

10144

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35984	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149697

1

T2

1

T3

2

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53054	1			T12	1056		T6	35		T27	16
values[0x0]	63609	1			T1	6		T2	2		T3	4
values[0x1]	69018	1			T1	2		T2	4		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158700

1

T1

1

T2

1

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	636	1			T12	6		T28	1		T124	1
valid_sources[0x01]	665	1			T2	1		T12	25		T8	77
valid_sources[0x02]	844	1			T12	10		T23	5		T26	7
valid_sources[0x03]	747	1			T12	21		T23	9		T26	1
valid_sources[0x04]	501	1			T12	10		T20	2		T23	15
valid_sources[0x05]	533	1			T12	11		T6	1		T23	7
valid_sources[0x06]	620	1			T12	12		T27	25		T124	1
valid_sources[0x07]	554	1			T12	20		T50	1		T23	14
valid_sources[0x08]	591	1			T12	7		T20	1		T23	7
valid_sources[0x09]	531	1			T12	18		T20	1		T63	1
valid_sources[0x0a]	608	1			T12	15		T20	2		T23	14
valid_sources[0x0b]	1167	1			T12	11		T23	4		T26	5
valid_sources[0x0c]	723	1			T12	13		T20	1		T7	2
valid_sources[0x0d]	560	1			T12	9		T45	1		T23	21
valid_sources[0x0e]	650	1			T12	13		T45	2		T23	8
valid_sources[0x0f]	544	1			T12	16		T23	11		T26	4
valid_sources[0x10]	729	1			T12	15		T29	1		T7	1
valid_sources[0x11]	730	1			T12	16		T6	1		T45	2
valid_sources[0x12]	623	1			T2	1		T12	9		T45	2
valid_sources[0x13]	645	1			T2	1		T12	15		T6	1
valid_sources[0x14]	734	1			T12	6		T28	3		T23	6
valid_sources[0x15]	943	1			T12	18		T6	1		T43	3
valid_sources[0x16]	836	1			T4	2		T12	3		T23	7
valid_sources[0x17]	1020	1			T12	15		T124	1		T7	1
valid_sources[0x18]	958	1			T12	25		T43	5		T127	2
valid_sources[0x19]	552	1			T11	1		T12	13		T7	1
valid_sources[0x1a]	810	1			T5	1		T12	12		T23	6
valid_sources[0x1b]	578	1			T12	13		T23	12		T128	1
valid_sources[0x1c]	858	1			T2	1		T12	14		T6	4
valid_sources[0x1d]	828	1			T12	23		T20	2		T7	2
valid_sources[0x1e]	779	1			T12	20		T124	1		T7	1
valid_sources[0x1f]	774	1			T12	21		T124	1		T23	14
valid_sources[0x20]	584	1			T12	10		T6	1		T63	2
valid_sources[0x21]	971	1			T12	13		T23	3		T53	3
valid_sources[0x22]	730	1			T12	19		T20	2		T23	13
valid_sources[0x23]	833	1			T12	19		T6	1		T124	1
valid_sources[0x24]	736	1			T12	8		T23	17		T128	1
valid_sources[0x25]	852	1			T12	10		T20	2		T23	16
valid_sources[0x26]	927	1			T12	18		T6	1		T7	1
valid_sources[0x27]	563	1			T12	18		T23	5		T26	1
valid_sources[0x28]	721	1			T12	16		T23	20		T26	6
valid_sources[0x29]	731	1			T12	19		T7	1		T23	18
valid_sources[0x2a]	864	1			T12	14		T28	1		T124	1
valid_sources[0x2b]	872	1			T12	8		T6	1		T23	8
valid_sources[0x2c]	672	1			T12	19		T23	8		T26	1
valid_sources[0x2d]	685	1			T12	12		T43	1		T7	1
valid_sources[0x2e]	607	1			T12	7		T44	1		T45	1
valid_sources[0x2f]	537	1			T12	6		T23	4		T26	5
valid_sources[0x30]	974	1			T12	29		T45	4		T23	9
valid_sources[0x31]	535	1			T12	23		T6	1		T7	1
valid_sources[0x32]	833	1			T12	3		T129	4		T23	10
valid_sources[0x33]	609	1			T12	11		T6	2		T20	1
valid_sources[0x34]	697	1			T12	18		T23	5		T31	1
valid_sources[0x35]	765	1			T12	24		T124	1		T23	6
valid_sources[0x36]	825	1			T12	23		T124	1		T23	20
valid_sources[0x37]	762	1			T12	12		T23	15		T14	3
valid_sources[0x38]	775	1			T9	2		T12	21		T7	1
valid_sources[0x39]	677	1			T12	20		T6	1		T23	12
valid_sources[0x3a]	696	1			T12	17		T23	15		T26	6
valid_sources[0x3b]	652	1			T12	7		T6	1		T7	1
valid_sources[0x3c]	515	1			T12	19		T23	3		T26	3
valid_sources[0x3d]	655	1			T12	18		T6	1		T43	5
valid_sources[0x3e]	676	1			T12	8		T23	7		T26	6
valid_sources[0x3f]	578	1			T12	16		T6	1		T23	4
valid_sources[0x40]	757	1			T12	16		T23	13		T26	3
valid_sources[0x41]	596	1			T12	13		T63	1		T23	12
valid_sources[0x42]	628	1			T12	19		T6	1		T28	1
valid_sources[0x43]	647	1			T12	14		T20	2		T7	1
valid_sources[0x44]	621	1			T12	14		T23	9		T67	2
valid_sources[0x45]	1081	1			T12	24		T23	7		T26	2
valid_sources[0x46]	631	1			T12	19		T6	1		T43	1
valid_sources[0x47]	669	1			T12	25		T52	1		T23	12
valid_sources[0x48]	735	1			T12	25		T23	9		T26	2
valid_sources[0x49]	660	1			T12	24		T20	6		T23	8
valid_sources[0x4a]	746	1			T12	1		T30	1		T23	28
valid_sources[0x4b]	1342	1			T12	23		T7	2		T23	21
valid_sources[0x4c]	925	1			T12	13		T20	4		T23	13
valid_sources[0x4d]	719	1			T12	17		T23	19		T53	17
valid_sources[0x4e]	755	1			T12	10		T28	1		T23	2
valid_sources[0x4f]	834	1			T12	26		T43	1		T20	1
valid_sources[0x50]	685	1			T5	2		T12	17		T27	5
valid_sources[0x51]	563	1			T12	6		T6	2		T20	2
valid_sources[0x52]	561	1			T12	17		T23	2		T103	2
valid_sources[0x53]	815	1			T12	14		T23	12		T26	2
valid_sources[0x54]	569	1			T12	11		T124	1		T23	12
valid_sources[0x55]	628	1			T12	17		T23	6		T26	4
valid_sources[0x56]	722	1			T12	7		T124	1		T23	24
valid_sources[0x57]	711	1			T12	10		T23	26		T130	1
valid_sources[0x58]	667	1			T12	12		T6	2		T23	7
valid_sources[0x59]	873	1			T12	23		T7	1		T23	12
valid_sources[0x5a]	870	1			T12	15		T7	1		T23	17
valid_sources[0x5b]	678	1			T12	12		T20	2		T124	1
valid_sources[0x5c]	890	1			T12	11		T7	1		T129	2
valid_sources[0x5d]	633	1			T12	24		T7	1		T23	17
valid_sources[0x5e]	706	1			T12	22		T23	5		T26	1
valid_sources[0x5f]	708	1			T12	7		T23	19		T26	4
valid_sources[0x60]	531	1			T10	1		T12	20		T23	6
valid_sources[0x61]	519	1			T12	12		T19	2		T23	8
valid_sources[0x62]	757	1			T4	1		T12	19		T7	1
valid_sources[0x63]	730	1			T12	10		T28	6		T23	19
valid_sources[0x64]	943	1			T12	13		T23	13		T26	1
valid_sources[0x65]	765	1			T12	32		T7	1		T129	2
valid_sources[0x66]	1061	1			T12	26		T23	13		T131	1
valid_sources[0x67]	692	1			T4	1		T12	8		T23	13
valid_sources[0x68]	810	1			T12	12		T6	3		T23	16
valid_sources[0x69]	808	1			T12	19		T43	3		T28	1
valid_sources[0x6a]	846	1			T11	1		T12	5		T28	3
valid_sources[0x6b]	619	1			T12	15		T27	4		T45	1
valid_sources[0x6c]	659	1			T10	1		T12	12		T43	3
valid_sources[0x6d]	688	1			T12	4		T20	2		T132	2
valid_sources[0x6e]	541	1			T12	24		T20	1		T23	6
valid_sources[0x6f]	774	1			T12	11		T6	1		T68	1
valid_sources[0x70]	668	1			T12	18		T23	7		T26	9
valid_sources[0x71]	567	1			T12	20		T20	6		T23	5
valid_sources[0x72]	767	1			T12	9		T20	1		T28	5
valid_sources[0x73]	811	1			T12	13		T23	13		T74	12
valid_sources[0x74]	889	1			T12	14		T50	1		T23	12
valid_sources[0x75]	799	1			T12	26		T6	2		T20	2
valid_sources[0x76]	537	1			T12	16		T6	1		T23	1
valid_sources[0x77]	688	1			T12	22		T7	1		T23	23
valid_sources[0x78]	479	1			T3	3		T12	13		T45	1
valid_sources[0x79]	822	1			T12	13		T6	1		T102	3
valid_sources[0x7a]	781	1			T12	11		T20	2		T23	5
valid_sources[0x7b]	765	1			T4	1		T12	12		T20	3
valid_sources[0x7c]	698	1			T12	17		T45	1		T23	7
valid_sources[0x7d]	825	1			T12	13		T7	1		T23	8
valid_sources[0x7e]	679	1			T12	13		T7	1		T23	11
valid_sources[0x7f]	659	1			T12	19		T68	1		T23	6
valid_sources[0x80]	1009	1			T12	14		T27	3		T124	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40636

1

T12

984

T6

15

T27

4

values[0x0]

all_enables

biggest_size

55339

1

T2

1

T3

2

T4

1

values[0x1]

all_enables

biggest_size

53722

1

T4

2

T12

1388

T6

3