Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13333428

1

T2

26759

T3

180358

T9

899

full_word

53603246

1

T1

6142

T2

267115

T3

39977

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66936414	1			T1	6142		T2	293874		T3	220335
auto[TlIntgErrCmd]	80	1			T59	5		T60	4		T61	5
auto[TlIntgErrData]	93	1			T59	2		T60	3		T61	9
auto[TlIntgErrBoth]	87	1			T59	3		T60	3		T61	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30562621

1

T1

2048

T2

146796

T3

110146

auto[1]

36374053

1

T1

4094

T2

147078

T3

110189

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6348629	1			T2	13248		T3	90168		T9	364
auto[TlIntgErrNone]	partial	auto[1]	6984564	1			T2	13511		T3	90190		T9	535
auto[TlIntgErrNone]	full_word	auto[0]	24213888	1			T1	2048		T2	133548		T3	19978
auto[TlIntgErrNone]	full_word	auto[1]	29389333	1			T1	4094		T2	133567		T3	19999
auto[TlIntgErrCmd]	partial	auto[0]	25	1			T60	1		T61	1		T119	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T59	4		T60	3		T61	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T115	1		T118	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T59	1		T111	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T60	2		T61	3		T119	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T59	1		T61	4		T119	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T61	1		T112	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T59	1		T60	1		T61	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T59	2		T61	2		T113	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T59	1		T60	3		T61	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T111	1		T114	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T61	1		T118	1		T122	1