Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	727545	1			T5	11777		T6	8155		T20	31608
auto[1]	9877036	1			T2	123298		T3	92633		T5	12617
auto[2]	596188	1			T5	10495		T6	7393		T20	28731
auto[3]	9768595	1			T2	123615		T3	92625		T5	11513

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13307549	1			T2	203863		T3	6133		T5	1034
auto[1]	2031888	1			T2	20481		T3	27541		T5	5338
auto[2]	2052365	1			T2	20514		T3	27276		T5	6498
auto[3]	3577562	1			T2	2055		T3	124308		T5	33532

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7893281

1

T10

413

T11

5225

T12

3

auto[1]

13076083

1

T2

246913

T3

185258

T5

46402

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	312660	1			T6	6710		T20	26137		T28	18
auto[0]	auto[0]	auto[1]	32519	1			T6	685		T20	2633		T28	3
auto[0]	auto[0]	auto[2]	32051	1			T6	681		T20	2561		T28	1
auto[0]	auto[0]	auto[3]	9127	1			T6	72		T20	261		T22	2
auto[0]	auto[1]	auto[0]	2959586	1			T10	212		T11	2602		T12	2
auto[0]	auto[1]	auto[1]	308572	1			T12	1		T6	654		T43	3273
auto[0]	auto[1]	auto[2]	295766	1			T6	95		T43	3534		T44	198
auto[0]	auto[1]	auto[3]	57312	1			T6	69		T43	334		T44	23
auto[0]	auto[2]	auto[0]	254218	1			T6	6267		T20	23759		T7	4
auto[0]	auto[2]	auto[1]	26367	1			T6	625		T20	2387		T7	1
auto[0]	auto[2]	auto[2]	31447	1			T6	442		T20	2278		T28	25
auto[0]	auto[2]	auto[3]	7880	1			T6	53		T20	282		T28	2
auto[0]	auto[3]	auto[0]	2906019	1			T10	201		T11	2623		T6	540
auto[0]	auto[3]	auto[1]	291193	1			T6	53		T43	3746		T44	209
auto[0]	auto[3]	auto[2]	309530	1			T6	451		T43	3364		T44	190
auto[0]	auto[3]	auto[3]	59034	1			T6	45		T43	298		T44	12
auto[1]	auto[0]	auto[0]	11586	1			T5	391		T6	5		T20	13
auto[1]	auto[0]	auto[1]	50681	1			T5	1784		T6	2		T20	2
auto[1]	auto[0]	auto[2]	50932	1			T5	1681		T20	1		T101	481
auto[1]	auto[0]	auto[3]	227989	1			T5	7921		T101	2220		T104	1959
auto[1]	auto[1]	auto[0]	3426847	1			T2	101917		T3	3041		T5	262
auto[1]	auto[1]	auto[1]	654647	1			T2	10185		T3	13805		T5	2011
auto[1]	auto[1]	auto[2]	642120	1			T2	10200		T3	13581		T5	1152
auto[1]	auto[1]	auto[3]	1532186	1			T2	996		T3	62206		T5	9192
auto[1]	auto[2]	auto[0]	8573	1			T5	257		T6	5		T20	16
auto[1]	auto[2]	auto[1]	37075	1			T5	1112		T20	3		T21	1
auto[1]	auto[2]	auto[2]	42031	1			T5	1619		T20	5		T101	467
auto[1]	auto[2]	auto[3]	188597	1			T5	7507		T6	1		T20	1
auto[1]	auto[3]	auto[0]	3428060	1			T2	101946		T3	3092		T5	124
auto[1]	auto[3]	auto[1]	630834	1			T2	10296		T3	13736		T5	431
auto[1]	auto[3]	auto[2]	648488	1			T2	10314		T3	13695		T5	2046
auto[1]	auto[3]	auto[3]	1495437	1			T2	1059		T3	62102		T5	8912