Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
24 |
24 |
100.00 |
Total Bits 0->1 |
12 |
12 |
100.00 |
Total Bits 1->0 |
12 |
12 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
24 |
24 |
100.00 |
Port Bits 0->1 |
12 |
12 |
100.00 |
Port Bits 1->0 |
12 |
12 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T12,T6,T20 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[0] |
Yes |
Yes |
*T13,*T14,*T15 |
Yes |
T13,T14,T15 |
INPUT |
oh_i[1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[8:2] |
Yes |
Yes |
T27,T22,T63 |
Yes |
T27,T22,T63 |
INPUT |
addr_i[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
err_o |
Yes |
Yes |
T16,T17,T18 |
Yes |
T16,T17,T18 |
OUTPUT |
*Tests covering at least one bit in the range