Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	327740207	223741	0	0
ctrl_regwen_rd_A	327740207	5414	0	0
exec_rd_A	327740207	5039	0	0
exec_regwen_rd_A	327740207	5115	0	0
readback_rd_A	327740207	3615	0	0
readback_regwen_rd_A	327740207	3046	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327740207	223741	0	0
T6	226618	0	0	0
T12	144650	5276	0	0
T19	159195	0	0	0
T20	593052	0	0	0
T23	0	3648	0	0
T26	0	1016	0	0
T28	105004	0	0	0
T29	1836	0	0	0
T43	332068	0	0	0
T44	7283	0	0	0
T47	0	2311	0	0
T48	0	2242	0	0
T52	294084	0	0	0
T53	0	3658	0	0
T68	9119	0	0	0
T69	0	5298	0	0
T70	0	3730	0	0
T71	0	2461	0	0
T72	0	3266	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327740207	5414	0	0
T6	226618	0	0	0
T12	144650	406	0	0
T19	159195	0	0	0
T20	593052	0	0	0
T26	0	57	0	0
T28	105004	0	0	0
T29	1836	0	0	0
T43	332068	0	0	0
T44	7283	0	0	0
T47	0	123	0	0
T52	294084	0	0	0
T68	9119	0	0	0
T70	0	345	0	0
T71	0	199	0	0
T72	0	284	0	0
T107	0	495	0	0
T108	0	194	0	0
T109	0	403	0	0
T110	0	310	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327740207	5039	0	0
T6	226618	0	0	0
T12	144650	340	0	0
T19	159195	0	0	0
T20	593052	0	0	0
T26	0	52	0	0
T28	105004	0	0	0
T29	1836	0	0	0
T43	332068	0	0	0
T44	7283	0	0	0
T47	0	128	0	0
T52	294084	0	0	0
T68	9119	0	0	0
T70	0	312	0	0
T71	0	176	0	0
T72	0	246	0	0
T107	0	399	0	0
T108	0	170	0	0
T109	0	350	0	0
T110	0	312	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327740207	5115	0	0
T6	226618	0	0	0
T12	144650	465	0	0
T19	159195	0	0	0
T20	593052	0	0	0
T26	0	41	0	0
T28	105004	0	0	0
T29	1836	0	0	0
T43	332068	0	0	0
T44	7283	0	0	0
T47	0	149	0	0
T52	294084	0	0	0
T68	9119	0	0	0
T70	0	332	0	0
T71	0	205	0	0
T72	0	256	0	0
T107	0	399	0	0
T108	0	211	0	0
T109	0	300	0	0
T110	0	258	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327740207	3615	0	0
T6	226618	0	0	0
T12	144650	312	0	0
T19	159195	0	0	0
T20	593052	0	0	0
T26	0	42	0	0
T28	105004	0	0	0
T29	1836	0	0	0
T43	332068	0	0	0
T44	7283	0	0	0
T47	0	147	0	0
T52	294084	0	0	0
T68	9119	0	0	0
T70	0	310	0	0
T71	0	220	0	0
T72	0	159	0	0
T107	0	422	0	0
T108	0	154	0	0
T109	0	379	0	0
T110	0	311	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327740207	3046	0	0
T6	226618	0	0	0
T12	144650	295	0	0
T19	159195	0	0	0
T20	593052	0	0	0
T26	0	22	0	0
T28	105004	0	0	0
T29	1836	0	0	0
T43	332068	0	0	0
T44	7283	0	0	0
T47	0	87	0	0
T52	294084	0	0	0
T68	9119	0	0	0
T70	0	289	0	0
T71	0	122	0	0
T72	0	158	0	0
T107	0	297	0	0
T108	0	165	0	0
T109	0	271	0	0
T110	0	254	0	0