| T791 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2723623398 |
|
|
Jul 21 06:45:31 PM PDT 24 |
Jul 21 06:45:52 PM PDT 24 |
668765367 ps |
| T792 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1081728172 |
|
|
Jul 21 06:45:23 PM PDT 24 |
Jul 21 07:04:21 PM PDT 24 |
17978124206 ps |
| T793 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.296276146 |
|
|
Jul 21 06:45:44 PM PDT 24 |
Jul 21 06:45:53 PM PDT 24 |
2826945032 ps |
| T794 |
/workspace/coverage/default/25.sram_ctrl_executable.3111826518 |
|
|
Jul 21 06:45:08 PM PDT 24 |
Jul 21 06:47:11 PM PDT 24 |
3888059961 ps |
| T795 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3670980570 |
|
|
Jul 21 06:44:14 PM PDT 24 |
Jul 21 06:44:56 PM PDT 24 |
1377328289 ps |
| T796 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3910550275 |
|
|
Jul 21 06:47:36 PM PDT 24 |
Jul 21 06:50:02 PM PDT 24 |
1568126654 ps |
| T797 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.2639423497 |
|
|
Jul 21 06:46:04 PM PDT 24 |
Jul 21 06:53:51 PM PDT 24 |
7096407789 ps |
| T798 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.3089116614 |
|
|
Jul 21 06:45:37 PM PDT 24 |
Jul 21 06:45:38 PM PDT 24 |
31587380 ps |
| T799 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.269290098 |
|
|
Jul 21 06:45:42 PM PDT 24 |
Jul 21 06:46:03 PM PDT 24 |
281792642 ps |
| T800 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3031397163 |
|
|
Jul 21 06:44:45 PM PDT 24 |
Jul 21 07:32:44 PM PDT 24 |
107480945236 ps |
| T801 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3978216911 |
|
|
Jul 21 06:43:58 PM PDT 24 |
Jul 21 06:55:15 PM PDT 24 |
9354201904 ps |
| T802 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2641550002 |
|
|
Jul 21 06:45:35 PM PDT 24 |
Jul 21 06:46:13 PM PDT 24 |
1147630196 ps |
| T803 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2553379646 |
|
|
Jul 21 06:47:35 PM PDT 24 |
Jul 21 06:51:52 PM PDT 24 |
11980820240 ps |
| T804 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3595224667 |
|
|
Jul 21 06:44:15 PM PDT 24 |
Jul 21 06:46:55 PM PDT 24 |
515284148 ps |
| T32 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2064956375 |
|
|
Jul 21 06:43:38 PM PDT 24 |
Jul 21 06:43:42 PM PDT 24 |
516502087 ps |
| T805 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1468077101 |
|
|
Jul 21 06:46:21 PM PDT 24 |
Jul 21 06:46:22 PM PDT 24 |
83007171 ps |
| T806 |
/workspace/coverage/default/11.sram_ctrl_regwen.1922541434 |
|
|
Jul 21 06:44:23 PM PDT 24 |
Jul 21 06:52:37 PM PDT 24 |
11326745441 ps |
| T807 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.4271227371 |
|
|
Jul 21 06:45:24 PM PDT 24 |
Jul 21 06:50:51 PM PDT 24 |
12552735381 ps |
| T808 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.618379637 |
|
|
Jul 21 06:44:00 PM PDT 24 |
Jul 21 06:44:09 PM PDT 24 |
1123019972 ps |
| T809 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1358956118 |
|
|
Jul 21 06:43:54 PM PDT 24 |
Jul 21 06:44:59 PM PDT 24 |
2997647160 ps |
| T810 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2999586095 |
|
|
Jul 21 06:45:25 PM PDT 24 |
Jul 21 06:45:31 PM PDT 24 |
1018986187 ps |
| T811 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1723031380 |
|
|
Jul 21 06:45:39 PM PDT 24 |
Jul 21 06:45:48 PM PDT 24 |
2689005417 ps |
| T812 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3706229391 |
|
|
Jul 21 06:44:08 PM PDT 24 |
Jul 21 06:44:18 PM PDT 24 |
1768144873 ps |
| T813 |
/workspace/coverage/default/17.sram_ctrl_partial_access.3797466001 |
|
|
Jul 21 06:44:42 PM PDT 24 |
Jul 21 06:45:05 PM PDT 24 |
4675359762 ps |
| T814 |
/workspace/coverage/default/28.sram_ctrl_regwen.2158497541 |
|
|
Jul 21 06:45:23 PM PDT 24 |
Jul 21 07:02:34 PM PDT 24 |
20308604078 ps |
| T815 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.886481006 |
|
|
Jul 21 06:45:14 PM PDT 24 |
Jul 21 06:45:40 PM PDT 24 |
168799646 ps |
| T816 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.4192563452 |
|
|
Jul 21 06:44:33 PM PDT 24 |
Jul 21 06:51:00 PM PDT 24 |
7960719879 ps |
| T817 |
/workspace/coverage/default/0.sram_ctrl_smoke.4291691253 |
|
|
Jul 21 06:43:32 PM PDT 24 |
Jul 21 06:43:45 PM PDT 24 |
2249988783 ps |
| T818 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.219541556 |
|
|
Jul 21 06:44:14 PM PDT 24 |
Jul 21 06:50:57 PM PDT 24 |
68988000407 ps |
| T819 |
/workspace/coverage/default/36.sram_ctrl_bijection.4127441945 |
|
|
Jul 21 06:46:06 PM PDT 24 |
Jul 21 06:46:36 PM PDT 24 |
1368153148 ps |
| T820 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.2142569652 |
|
|
Jul 21 06:46:23 PM PDT 24 |
Jul 21 06:46:26 PM PDT 24 |
341389208 ps |
| T821 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.4046031419 |
|
|
Jul 21 06:46:06 PM PDT 24 |
Jul 21 06:49:04 PM PDT 24 |
1868711103 ps |
| T822 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2976937558 |
|
|
Jul 21 06:47:23 PM PDT 24 |
Jul 21 06:53:17 PM PDT 24 |
13353971514 ps |
| T823 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1218060685 |
|
|
Jul 21 06:44:41 PM PDT 24 |
Jul 21 06:55:50 PM PDT 24 |
25683839275 ps |
| T824 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.4209112662 |
|
|
Jul 21 06:46:01 PM PDT 24 |
Jul 21 06:52:46 PM PDT 24 |
39179500915 ps |
| T33 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.4084997560 |
|
|
Jul 21 06:43:47 PM PDT 24 |
Jul 21 06:43:52 PM PDT 24 |
429163778 ps |
| T825 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2211469096 |
|
|
Jul 21 06:47:26 PM PDT 24 |
Jul 21 06:47:27 PM PDT 24 |
41518575 ps |
| T826 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.2178998422 |
|
|
Jul 21 06:43:42 PM PDT 24 |
Jul 21 06:52:06 PM PDT 24 |
3639439083 ps |
| T827 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3109967893 |
|
|
Jul 21 06:44:43 PM PDT 24 |
Jul 21 06:45:23 PM PDT 24 |
379647946 ps |
| T828 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3754750405 |
|
|
Jul 21 06:43:46 PM PDT 24 |
Jul 21 06:43:52 PM PDT 24 |
369389995 ps |
| T829 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1903968160 |
|
|
Jul 21 06:47:35 PM PDT 24 |
Jul 21 06:48:15 PM PDT 24 |
792073819 ps |
| T830 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2519789952 |
|
|
Jul 21 06:44:28 PM PDT 24 |
Jul 21 06:44:29 PM PDT 24 |
90622508 ps |
| T831 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1002809465 |
|
|
Jul 21 06:44:42 PM PDT 24 |
Jul 21 06:44:45 PM PDT 24 |
117044553 ps |
| T832 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1929765173 |
|
|
Jul 21 06:46:20 PM PDT 24 |
Jul 21 06:47:01 PM PDT 24 |
114122804 ps |
| T833 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3032712591 |
|
|
Jul 21 06:46:36 PM PDT 24 |
Jul 21 06:46:53 PM PDT 24 |
86697393 ps |
| T834 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3463786555 |
|
|
Jul 21 06:43:52 PM PDT 24 |
Jul 21 07:03:24 PM PDT 24 |
3243618797 ps |
| T835 |
/workspace/coverage/default/9.sram_ctrl_stress_all.671628780 |
|
|
Jul 21 06:44:15 PM PDT 24 |
Jul 21 06:56:59 PM PDT 24 |
5330515836 ps |
| T836 |
/workspace/coverage/default/11.sram_ctrl_bijection.2473526285 |
|
|
Jul 21 06:44:14 PM PDT 24 |
Jul 21 06:45:00 PM PDT 24 |
717242814 ps |
| T837 |
/workspace/coverage/default/43.sram_ctrl_regwen.1824173028 |
|
|
Jul 21 06:47:09 PM PDT 24 |
Jul 21 07:03:32 PM PDT 24 |
35554538913 ps |
| T838 |
/workspace/coverage/default/0.sram_ctrl_partial_access.1007724046 |
|
|
Jul 21 06:43:35 PM PDT 24 |
Jul 21 06:43:47 PM PDT 24 |
223291657 ps |
| T839 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3955629210 |
|
|
Jul 21 06:47:45 PM PDT 24 |
Jul 21 06:47:46 PM PDT 24 |
67478029 ps |
| T840 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3613247593 |
|
|
Jul 21 06:45:31 PM PDT 24 |
Jul 21 06:45:33 PM PDT 24 |
59128522 ps |
| T841 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2180222951 |
|
|
Jul 21 06:43:45 PM PDT 24 |
Jul 21 06:44:01 PM PDT 24 |
880186649 ps |
| T842 |
/workspace/coverage/default/24.sram_ctrl_smoke.546831387 |
|
|
Jul 21 06:45:01 PM PDT 24 |
Jul 21 06:47:44 PM PDT 24 |
2388237296 ps |
| T843 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2104892952 |
|
|
Jul 21 06:46:13 PM PDT 24 |
Jul 21 06:46:19 PM PDT 24 |
553499652 ps |
| T844 |
/workspace/coverage/default/31.sram_ctrl_alert_test.4250681274 |
|
|
Jul 21 06:45:44 PM PDT 24 |
Jul 21 06:45:45 PM PDT 24 |
13474100 ps |
| T845 |
/workspace/coverage/default/42.sram_ctrl_bijection.23590822 |
|
|
Jul 21 06:46:51 PM PDT 24 |
Jul 21 06:48:02 PM PDT 24 |
4187441874 ps |
| T846 |
/workspace/coverage/default/18.sram_ctrl_smoke.607987255 |
|
|
Jul 21 06:44:39 PM PDT 24 |
Jul 21 06:44:40 PM PDT 24 |
545098083 ps |
| T847 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3044819743 |
|
|
Jul 21 06:45:37 PM PDT 24 |
Jul 21 06:46:31 PM PDT 24 |
221712728 ps |
| T848 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.79739363 |
|
|
Jul 21 06:47:15 PM PDT 24 |
Jul 21 06:52:13 PM PDT 24 |
1383187364 ps |
| T849 |
/workspace/coverage/default/2.sram_ctrl_smoke.364072635 |
|
|
Jul 21 06:43:46 PM PDT 24 |
Jul 21 06:43:59 PM PDT 24 |
1332495822 ps |
| T850 |
/workspace/coverage/default/33.sram_ctrl_stress_all.311037289 |
|
|
Jul 21 06:45:51 PM PDT 24 |
Jul 21 07:14:36 PM PDT 24 |
95256843176 ps |
| T851 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1939336742 |
|
|
Jul 21 06:43:41 PM PDT 24 |
Jul 21 06:47:16 PM PDT 24 |
5514386391 ps |
| T852 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.8606480 |
|
|
Jul 21 06:44:48 PM PDT 24 |
Jul 21 07:02:07 PM PDT 24 |
4146779337 ps |
| T853 |
/workspace/coverage/default/6.sram_ctrl_regwen.3541411086 |
|
|
Jul 21 06:44:00 PM PDT 24 |
Jul 21 07:01:45 PM PDT 24 |
2505329681 ps |
| T854 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3138802975 |
|
|
Jul 21 06:44:07 PM PDT 24 |
Jul 21 06:44:25 PM PDT 24 |
2409503029 ps |
| T855 |
/workspace/coverage/default/45.sram_ctrl_bijection.1606959310 |
|
|
Jul 21 06:47:17 PM PDT 24 |
Jul 21 06:47:45 PM PDT 24 |
1800488829 ps |
| T856 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.513875833 |
|
|
Jul 21 06:47:07 PM PDT 24 |
Jul 21 06:50:04 PM PDT 24 |
3503059952 ps |
| T857 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1105030824 |
|
|
Jul 21 06:46:41 PM PDT 24 |
Jul 21 06:49:44 PM PDT 24 |
4760591922 ps |
| T858 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.188219716 |
|
|
Jul 21 06:44:07 PM PDT 24 |
Jul 21 06:44:27 PM PDT 24 |
2791846217 ps |
| T859 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.681789201 |
|
|
Jul 21 06:43:52 PM PDT 24 |
Jul 21 06:43:58 PM PDT 24 |
460493929 ps |
| T860 |
/workspace/coverage/default/23.sram_ctrl_regwen.2845537070 |
|
|
Jul 21 06:45:01 PM PDT 24 |
Jul 21 06:57:04 PM PDT 24 |
7006030027 ps |
| T861 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1033872599 |
|
|
Jul 21 06:44:54 PM PDT 24 |
Jul 21 06:46:44 PM PDT 24 |
1520345377 ps |
| T862 |
/workspace/coverage/default/34.sram_ctrl_alert_test.1953068364 |
|
|
Jul 21 06:45:57 PM PDT 24 |
Jul 21 06:45:59 PM PDT 24 |
13192436 ps |
| T863 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2927084294 |
|
|
Jul 21 06:43:33 PM PDT 24 |
Jul 21 07:04:25 PM PDT 24 |
114568517820 ps |
| T864 |
/workspace/coverage/default/29.sram_ctrl_regwen.1997781401 |
|
|
Jul 21 06:45:29 PM PDT 24 |
Jul 21 07:03:23 PM PDT 24 |
12630198790 ps |
| T865 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.408440498 |
|
|
Jul 21 06:47:29 PM PDT 24 |
Jul 21 06:52:37 PM PDT 24 |
4652539460 ps |
| T866 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.827111127 |
|
|
Jul 21 06:46:55 PM PDT 24 |
Jul 21 06:49:15 PM PDT 24 |
767687632 ps |
| T867 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2206882882 |
|
|
Jul 21 06:44:35 PM PDT 24 |
Jul 21 06:44:36 PM PDT 24 |
200232740 ps |
| T868 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3317848051 |
|
|
Jul 21 06:47:28 PM PDT 24 |
Jul 21 06:50:04 PM PDT 24 |
207072573 ps |
| T869 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.781807044 |
|
|
Jul 21 06:47:09 PM PDT 24 |
Jul 21 06:54:00 PM PDT 24 |
6752145946 ps |
| T94 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3774883942 |
|
|
Jul 21 06:45:35 PM PDT 24 |
Jul 21 06:45:41 PM PDT 24 |
1761608951 ps |
| T870 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2650250519 |
|
|
Jul 21 06:45:14 PM PDT 24 |
Jul 21 06:45:25 PM PDT 24 |
1338045708 ps |
| T871 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3201108059 |
|
|
Jul 21 06:46:47 PM PDT 24 |
Jul 21 06:46:48 PM PDT 24 |
47411857 ps |
| T872 |
/workspace/coverage/default/8.sram_ctrl_regwen.1846224716 |
|
|
Jul 21 06:44:09 PM PDT 24 |
Jul 21 06:58:37 PM PDT 24 |
10407373419 ps |
| T873 |
/workspace/coverage/default/25.sram_ctrl_regwen.3108310191 |
|
|
Jul 21 06:45:08 PM PDT 24 |
Jul 21 06:58:52 PM PDT 24 |
196011515314 ps |
| T874 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1441212208 |
|
|
Jul 21 06:44:42 PM PDT 24 |
Jul 21 06:44:49 PM PDT 24 |
182134188 ps |
| T875 |
/workspace/coverage/default/47.sram_ctrl_bijection.2986658986 |
|
|
Jul 21 06:47:33 PM PDT 24 |
Jul 21 06:48:29 PM PDT 24 |
2317872031 ps |
| T876 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3369559103 |
|
|
Jul 21 06:44:13 PM PDT 24 |
Jul 21 06:44:19 PM PDT 24 |
577710047 ps |
| T877 |
/workspace/coverage/default/4.sram_ctrl_regwen.3638692175 |
|
|
Jul 21 06:43:51 PM PDT 24 |
Jul 21 07:05:17 PM PDT 24 |
6427550372 ps |
| T878 |
/workspace/coverage/default/23.sram_ctrl_partial_access.3625975825 |
|
|
Jul 21 06:44:59 PM PDT 24 |
Jul 21 06:47:10 PM PDT 24 |
776022749 ps |
| T879 |
/workspace/coverage/default/17.sram_ctrl_stress_all.3631524735 |
|
|
Jul 21 06:44:34 PM PDT 24 |
Jul 21 07:37:03 PM PDT 24 |
15888976662 ps |
| T880 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.3961733448 |
|
|
Jul 21 06:45:50 PM PDT 24 |
Jul 21 06:45:51 PM PDT 24 |
47104108 ps |
| T881 |
/workspace/coverage/default/28.sram_ctrl_stress_all.1515086947 |
|
|
Jul 21 06:45:25 PM PDT 24 |
Jul 21 07:12:57 PM PDT 24 |
7953824829 ps |
| T882 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1456412780 |
|
|
Jul 21 06:44:16 PM PDT 24 |
Jul 21 06:44:18 PM PDT 24 |
77878441 ps |
| T883 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.915240301 |
|
|
Jul 21 06:46:13 PM PDT 24 |
Jul 21 06:47:15 PM PDT 24 |
120121494 ps |
| T884 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3273623437 |
|
|
Jul 21 06:45:52 PM PDT 24 |
Jul 21 06:45:59 PM PDT 24 |
159823253 ps |
| T885 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2306000059 |
|
|
Jul 21 06:47:54 PM PDT 24 |
Jul 21 07:03:42 PM PDT 24 |
9932210092 ps |
| T886 |
/workspace/coverage/default/31.sram_ctrl_bijection.3532308287 |
|
|
Jul 21 06:45:35 PM PDT 24 |
Jul 21 06:46:12 PM PDT 24 |
3275173883 ps |
| T887 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1297646514 |
|
|
Jul 21 06:43:53 PM PDT 24 |
Jul 21 06:47:18 PM PDT 24 |
2163395341 ps |
| T888 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.1964776372 |
|
|
Jul 21 06:47:18 PM PDT 24 |
Jul 21 06:47:27 PM PDT 24 |
284585438 ps |
| T889 |
/workspace/coverage/default/31.sram_ctrl_executable.1254612061 |
|
|
Jul 21 06:45:41 PM PDT 24 |
Jul 21 06:57:13 PM PDT 24 |
2797571952 ps |
| T890 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2104252578 |
|
|
Jul 21 06:44:54 PM PDT 24 |
Jul 21 06:45:03 PM PDT 24 |
3409052569 ps |
| T891 |
/workspace/coverage/default/36.sram_ctrl_stress_all.3328923671 |
|
|
Jul 21 06:46:12 PM PDT 24 |
Jul 21 07:37:27 PM PDT 24 |
81510749759 ps |
| T892 |
/workspace/coverage/default/34.sram_ctrl_regwen.696262552 |
|
|
Jul 21 06:45:56 PM PDT 24 |
Jul 21 07:05:20 PM PDT 24 |
21326006644 ps |
| T893 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1662334039 |
|
|
Jul 21 06:44:42 PM PDT 24 |
Jul 21 06:44:45 PM PDT 24 |
195149702 ps |
| T894 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3368598234 |
|
|
Jul 21 06:47:50 PM PDT 24 |
Jul 21 06:53:15 PM PDT 24 |
29261130012 ps |
| T895 |
/workspace/coverage/default/46.sram_ctrl_regwen.2164865620 |
|
|
Jul 21 06:47:29 PM PDT 24 |
Jul 21 06:54:44 PM PDT 24 |
5086264765 ps |
| T896 |
/workspace/coverage/default/4.sram_ctrl_smoke.1568826628 |
|
|
Jul 21 06:43:47 PM PDT 24 |
Jul 21 06:45:32 PM PDT 24 |
235788927 ps |
| T897 |
/workspace/coverage/default/24.sram_ctrl_regwen.1184876581 |
|
|
Jul 21 06:45:01 PM PDT 24 |
Jul 21 06:50:22 PM PDT 24 |
7314084763 ps |
| T898 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1388812774 |
|
|
Jul 21 06:47:30 PM PDT 24 |
Jul 21 07:15:19 PM PDT 24 |
19102023709 ps |
| T899 |
/workspace/coverage/default/37.sram_ctrl_smoke.2544025851 |
|
|
Jul 21 06:46:12 PM PDT 24 |
Jul 21 06:46:36 PM PDT 24 |
1103355969 ps |
| T900 |
/workspace/coverage/default/42.sram_ctrl_smoke.2662676813 |
|
|
Jul 21 06:46:51 PM PDT 24 |
Jul 21 06:46:59 PM PDT 24 |
723660617 ps |
| T901 |
/workspace/coverage/default/9.sram_ctrl_bijection.1969553807 |
|
|
Jul 21 06:44:17 PM PDT 24 |
Jul 21 06:44:51 PM PDT 24 |
541207352 ps |
| T902 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1111594817 |
|
|
Jul 21 06:44:35 PM PDT 24 |
Jul 21 06:44:36 PM PDT 24 |
18849059 ps |
| T903 |
/workspace/coverage/default/5.sram_ctrl_executable.2276764996 |
|
|
Jul 21 06:43:51 PM PDT 24 |
Jul 21 06:57:29 PM PDT 24 |
167304062549 ps |
| T904 |
/workspace/coverage/default/11.sram_ctrl_smoke.3064188835 |
|
|
Jul 21 06:44:27 PM PDT 24 |
Jul 21 06:44:30 PM PDT 24 |
533680208 ps |
| T905 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3370154283 |
|
|
Jul 21 06:47:54 PM PDT 24 |
Jul 21 06:48:05 PM PDT 24 |
906281499 ps |
| T906 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.424496553 |
|
|
Jul 21 06:44:53 PM PDT 24 |
Jul 21 06:58:04 PM PDT 24 |
10522326316 ps |
| T907 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1757417523 |
|
|
Jul 21 06:43:51 PM PDT 24 |
Jul 21 06:44:48 PM PDT 24 |
543453604 ps |
| T908 |
/workspace/coverage/default/45.sram_ctrl_smoke.1958195244 |
|
|
Jul 21 06:47:12 PM PDT 24 |
Jul 21 06:49:10 PM PDT 24 |
4725634586 ps |
| T909 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.2261437433 |
|
|
Jul 21 06:45:57 PM PDT 24 |
Jul 21 06:45:58 PM PDT 24 |
29143051 ps |
| T910 |
/workspace/coverage/default/47.sram_ctrl_executable.1746994993 |
|
|
Jul 21 06:47:38 PM PDT 24 |
Jul 21 07:09:22 PM PDT 24 |
2816468146 ps |
| T911 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3828036509 |
|
|
Jul 21 06:44:35 PM PDT 24 |
Jul 21 06:49:19 PM PDT 24 |
5708541469 ps |
| T912 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1417784477 |
|
|
Jul 21 06:44:20 PM PDT 24 |
Jul 21 06:44:21 PM PDT 24 |
91462785 ps |
| T913 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4115284132 |
|
|
Jul 21 06:47:45 PM PDT 24 |
Jul 21 06:50:08 PM PDT 24 |
4150923548 ps |
| T914 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.846189571 |
|
|
Jul 21 06:43:35 PM PDT 24 |
Jul 21 06:44:03 PM PDT 24 |
190165122 ps |
| T915 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.665333504 |
|
|
Jul 21 06:47:45 PM PDT 24 |
Jul 21 06:49:07 PM PDT 24 |
217507868 ps |
| T916 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1468016559 |
|
|
Jul 21 06:46:53 PM PDT 24 |
Jul 21 06:50:08 PM PDT 24 |
1923712631 ps |
| T917 |
/workspace/coverage/default/36.sram_ctrl_smoke.2585989872 |
|
|
Jul 21 06:46:06 PM PDT 24 |
Jul 21 06:46:28 PM PDT 24 |
195259801 ps |
| T918 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1120026118 |
|
|
Jul 21 06:44:16 PM PDT 24 |
Jul 21 06:50:03 PM PDT 24 |
7490303586 ps |
| T919 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1648988566 |
|
|
Jul 21 06:43:50 PM PDT 24 |
Jul 21 06:50:28 PM PDT 24 |
16620179796 ps |
| T920 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.620385727 |
|
|
Jul 21 06:43:52 PM PDT 24 |
Jul 21 06:43:56 PM PDT 24 |
151249238 ps |
| T921 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2909184401 |
|
|
Jul 21 06:44:09 PM PDT 24 |
Jul 21 06:44:11 PM PDT 24 |
25701984 ps |
| T922 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.848859069 |
|
|
Jul 21 06:44:33 PM PDT 24 |
Jul 21 06:44:39 PM PDT 24 |
447124449 ps |
| T923 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1994869627 |
|
|
Jul 21 06:47:43 PM PDT 24 |
Jul 21 06:47:50 PM PDT 24 |
2718920724 ps |
| T924 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1698630563 |
|
|
Jul 21 06:44:30 PM PDT 24 |
Jul 21 06:44:34 PM PDT 24 |
2297219724 ps |
| T925 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.878245075 |
|
|
Jul 21 06:46:28 PM PDT 24 |
Jul 21 06:48:47 PM PDT 24 |
154797063 ps |
| T926 |
/workspace/coverage/default/35.sram_ctrl_regwen.3304840107 |
|
|
Jul 21 06:46:05 PM PDT 24 |
Jul 21 06:57:13 PM PDT 24 |
11788405340 ps |
| T927 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.993576827 |
|
|
Jul 21 06:46:22 PM PDT 24 |
Jul 21 06:46:37 PM PDT 24 |
81663767 ps |
| T928 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.474479236 |
|
|
Jul 21 06:44:30 PM PDT 24 |
Jul 21 07:01:38 PM PDT 24 |
14917835890 ps |
| T64 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.262475027 |
|
|
Jul 21 06:40:07 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
24457409 ps |
| T65 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.526217862 |
|
|
Jul 21 06:39:49 PM PDT 24 |
Jul 21 06:39:55 PM PDT 24 |
61972563 ps |
| T66 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.661575849 |
|
|
Jul 21 06:40:05 PM PDT 24 |
Jul 21 06:40:08 PM PDT 24 |
67329994 ps |
| T929 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3044041444 |
|
|
Jul 21 06:39:52 PM PDT 24 |
Jul 21 06:40:00 PM PDT 24 |
49569296 ps |
| T123 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2016845168 |
|
|
Jul 21 06:39:43 PM PDT 24 |
Jul 21 06:39:45 PM PDT 24 |
41358089 ps |
| T99 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3857356080 |
|
|
Jul 21 06:39:52 PM PDT 24 |
Jul 21 06:39:59 PM PDT 24 |
24628818 ps |
| T106 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1460678896 |
|
|
Jul 21 06:40:07 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
23772725 ps |
| T75 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1463954853 |
|
|
Jul 21 06:39:54 PM PDT 24 |
Jul 21 06:40:03 PM PDT 24 |
822712185 ps |
| T59 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1010981687 |
|
|
Jul 21 06:39:52 PM PDT 24 |
Jul 21 06:39:59 PM PDT 24 |
302184229 ps |
| T100 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1159446657 |
|
|
Jul 21 06:39:51 PM PDT 24 |
Jul 21 06:39:57 PM PDT 24 |
25410481 ps |
| T930 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3220906489 |
|
|
Jul 21 06:40:03 PM PDT 24 |
Jul 21 06:40:08 PM PDT 24 |
56439907 ps |
| T76 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1272594937 |
|
|
Jul 21 06:40:08 PM PDT 24 |
Jul 21 06:40:10 PM PDT 24 |
16457684 ps |
| T77 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3429528822 |
|
|
Jul 21 06:40:03 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
470118080 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1391890177 |
|
|
Jul 21 06:39:49 PM PDT 24 |
Jul 21 06:39:57 PM PDT 24 |
1545722183 ps |
| T79 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1881316691 |
|
|
Jul 21 06:39:53 PM PDT 24 |
Jul 21 06:40:00 PM PDT 24 |
196309823 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3641402361 |
|
|
Jul 21 06:39:42 PM PDT 24 |
Jul 21 06:39:44 PM PDT 24 |
60847838 ps |
| T81 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3683667260 |
|
|
Jul 21 06:40:01 PM PDT 24 |
Jul 21 06:40:08 PM PDT 24 |
749799573 ps |
| T82 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2471277388 |
|
|
Jul 21 06:39:51 PM PDT 24 |
Jul 21 06:39:58 PM PDT 24 |
1173898498 ps |
| T931 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4077560859 |
|
|
Jul 21 06:40:00 PM PDT 24 |
Jul 21 06:40:06 PM PDT 24 |
214055639 ps |
| T932 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2487199464 |
|
|
Jul 21 06:39:59 PM PDT 24 |
Jul 21 06:40:05 PM PDT 24 |
52722212 ps |
| T60 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.186267295 |
|
|
Jul 21 06:40:05 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
104923213 ps |
| T933 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3768005169 |
|
|
Jul 21 06:39:52 PM PDT 24 |
Jul 21 06:40:00 PM PDT 24 |
28789593 ps |
| T61 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.378918723 |
|
|
Jul 21 06:39:55 PM PDT 24 |
Jul 21 06:40:04 PM PDT 24 |
176753174 ps |
| T934 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2336492502 |
|
|
Jul 21 06:40:05 PM PDT 24 |
Jul 21 06:40:08 PM PDT 24 |
45584902 ps |
| T119 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1351398769 |
|
|
Jul 21 06:39:52 PM PDT 24 |
Jul 21 06:40:00 PM PDT 24 |
132112859 ps |
| T83 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4228538554 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
594104409 ps |
| T935 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3598625700 |
|
|
Jul 21 06:39:50 PM PDT 24 |
Jul 21 06:39:55 PM PDT 24 |
39388884 ps |
| T84 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1223181872 |
|
|
Jul 21 06:39:58 PM PDT 24 |
Jul 21 06:40:05 PM PDT 24 |
84104116 ps |
| T85 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3170250316 |
|
|
Jul 21 06:39:55 PM PDT 24 |
Jul 21 06:40:02 PM PDT 24 |
13211515 ps |
| T936 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1062510247 |
|
|
Jul 21 06:39:48 PM PDT 24 |
Jul 21 06:39:53 PM PDT 24 |
53576798 ps |
| T937 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4293404148 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:08 PM PDT 24 |
116843366 ps |
| T938 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3827063319 |
|
|
Jul 21 06:39:54 PM PDT 24 |
Jul 21 06:40:02 PM PDT 24 |
200949073 ps |
| T113 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3354668111 |
|
|
Jul 21 06:39:58 PM PDT 24 |
Jul 21 06:40:05 PM PDT 24 |
104308496 ps |
| T111 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.116412143 |
|
|
Jul 21 06:39:46 PM PDT 24 |
Jul 21 06:39:50 PM PDT 24 |
450247062 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3206759193 |
|
|
Jul 21 06:39:41 PM PDT 24 |
Jul 21 06:39:45 PM PDT 24 |
1405342661 ps |
| T939 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3484330539 |
|
|
Jul 21 06:39:55 PM PDT 24 |
Jul 21 06:40:04 PM PDT 24 |
285383181 ps |
| T940 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2378149622 |
|
|
Jul 21 06:39:47 PM PDT 24 |
Jul 21 06:39:51 PM PDT 24 |
27329680 ps |
| T941 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.159158905 |
|
|
Jul 21 06:40:07 PM PDT 24 |
Jul 21 06:40:11 PM PDT 24 |
215817246 ps |
| T96 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2043272456 |
|
|
Jul 21 06:39:51 PM PDT 24 |
Jul 21 06:39:57 PM PDT 24 |
755099377 ps |
| T112 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1713315376 |
|
|
Jul 21 06:39:40 PM PDT 24 |
Jul 21 06:39:44 PM PDT 24 |
3099531170 ps |
| T942 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.732910795 |
|
|
Jul 21 06:39:55 PM PDT 24 |
Jul 21 06:40:02 PM PDT 24 |
21688269 ps |
| T943 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1372626271 |
|
|
Jul 21 06:40:07 PM PDT 24 |
Jul 21 06:40:12 PM PDT 24 |
51128415 ps |
| T944 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2954989437 |
|
|
Jul 21 06:39:59 PM PDT 24 |
Jul 21 06:40:05 PM PDT 24 |
39562253 ps |
| T945 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1139079175 |
|
|
Jul 21 06:40:03 PM PDT 24 |
Jul 21 06:40:10 PM PDT 24 |
48706399 ps |
| T946 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1372737661 |
|
|
Jul 21 06:40:03 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
72158493 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.690354080 |
|
|
Jul 21 06:39:53 PM PDT 24 |
Jul 21 06:39:59 PM PDT 24 |
107746410 ps |
| T948 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2812834387 |
|
|
Jul 21 06:40:01 PM PDT 24 |
Jul 21 06:40:06 PM PDT 24 |
17797858 ps |
| T949 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2389390590 |
|
|
Jul 21 06:40:01 PM PDT 24 |
Jul 21 06:40:07 PM PDT 24 |
118549958 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1883675390 |
|
|
Jul 21 06:39:47 PM PDT 24 |
Jul 21 06:39:52 PM PDT 24 |
182733123 ps |
| T97 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3065534624 |
|
|
Jul 21 06:39:46 PM PDT 24 |
Jul 21 06:39:50 PM PDT 24 |
60118612 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1717318537 |
|
|
Jul 21 06:39:41 PM PDT 24 |
Jul 21 06:39:43 PM PDT 24 |
360512531 ps |
| T98 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2577649925 |
|
|
Jul 21 06:40:02 PM PDT 24 |
Jul 21 06:40:08 PM PDT 24 |
390135762 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3803739293 |
|
|
Jul 21 06:39:59 PM PDT 24 |
Jul 21 06:40:05 PM PDT 24 |
11646553 ps |
| T953 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.859633073 |
|
|
Jul 21 06:39:55 PM PDT 24 |
Jul 21 06:40:02 PM PDT 24 |
14714981 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1518000654 |
|
|
Jul 21 06:39:46 PM PDT 24 |
Jul 21 06:39:50 PM PDT 24 |
17250400 ps |
| T955 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.141031666 |
|
|
Jul 21 06:39:53 PM PDT 24 |
Jul 21 06:40:00 PM PDT 24 |
774672499 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2556582657 |
|
|
Jul 21 06:39:46 PM PDT 24 |
Jul 21 06:39:50 PM PDT 24 |
51308371 ps |
| T957 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2406013529 |
|
|
Jul 21 06:40:05 PM PDT 24 |
Jul 21 06:40:08 PM PDT 24 |
154308121 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2552340034 |
|
|
Jul 21 06:39:47 PM PDT 24 |
Jul 21 06:39:51 PM PDT 24 |
42669770 ps |
| T959 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2033458270 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:08 PM PDT 24 |
35418274 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1017262897 |
|
|
Jul 21 06:39:49 PM PDT 24 |
Jul 21 06:39:54 PM PDT 24 |
28292885 ps |
| T114 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1588252987 |
|
|
Jul 21 06:39:45 PM PDT 24 |
Jul 21 06:39:49 PM PDT 24 |
586413075 ps |
| T961 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2712681388 |
|
|
Jul 21 06:39:55 PM PDT 24 |
Jul 21 06:40:02 PM PDT 24 |
26429191 ps |
| T116 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.414456551 |
|
|
Jul 21 06:40:07 PM PDT 24 |
Jul 21 06:40:10 PM PDT 24 |
277069060 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3629556553 |
|
|
Jul 21 06:39:48 PM PDT 24 |
Jul 21 06:39:53 PM PDT 24 |
54573856 ps |
| T115 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3148430458 |
|
|
Jul 21 06:39:58 PM PDT 24 |
Jul 21 06:40:07 PM PDT 24 |
597050156 ps |
| T963 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1299135021 |
|
|
Jul 21 06:39:54 PM PDT 24 |
Jul 21 06:40:01 PM PDT 24 |
30787461 ps |
| T964 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3227915873 |
|
|
Jul 21 06:39:52 PM PDT 24 |
Jul 21 06:40:01 PM PDT 24 |
776059488 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3808678052 |
|
|
Jul 21 06:39:46 PM PDT 24 |
Jul 21 06:39:51 PM PDT 24 |
124961010 ps |
| T118 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.612390993 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
788108000 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3221399950 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:10 PM PDT 24 |
28118735 ps |
| T967 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1188160226 |
|
|
Jul 21 06:40:00 PM PDT 24 |
Jul 21 06:40:06 PM PDT 24 |
30432921 ps |
| T968 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2643515670 |
|
|
Jul 21 06:39:59 PM PDT 24 |
Jul 21 06:40:07 PM PDT 24 |
180126860 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3295177160 |
|
|
Jul 21 06:39:45 PM PDT 24 |
Jul 21 06:39:50 PM PDT 24 |
155795110 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3855430188 |
|
|
Jul 21 06:40:01 PM PDT 24 |
Jul 21 06:40:06 PM PDT 24 |
22473704 ps |
| T971 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3754235786 |
|
|
Jul 21 06:39:54 PM PDT 24 |
Jul 21 06:40:01 PM PDT 24 |
15017784 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2769753081 |
|
|
Jul 21 06:39:49 PM PDT 24 |
Jul 21 06:39:54 PM PDT 24 |
153316878 ps |
| T973 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.987524104 |
|
|
Jul 21 06:40:05 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
135097930 ps |
| T974 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.236365463 |
|
|
Jul 21 06:40:00 PM PDT 24 |
Jul 21 06:40:05 PM PDT 24 |
107235351 ps |
| T975 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1491825351 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:11 PM PDT 24 |
443926996 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1252044771 |
|
|
Jul 21 06:39:44 PM PDT 24 |
Jul 21 06:39:46 PM PDT 24 |
91772848 ps |
| T117 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.758242535 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
83318330 ps |
| T977 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1025495629 |
|
|
Jul 21 06:39:42 PM PDT 24 |
Jul 21 06:39:46 PM PDT 24 |
156590008 ps |
| T978 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1212981388 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:10 PM PDT 24 |
1093603335 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2917893427 |
|
|
Jul 21 06:39:44 PM PDT 24 |
Jul 21 06:39:47 PM PDT 24 |
178431724 ps |
| T980 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2094309077 |
|
|
Jul 21 06:39:54 PM PDT 24 |
Jul 21 06:40:03 PM PDT 24 |
73921469 ps |
| T981 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2656565442 |
|
|
Jul 21 06:39:53 PM PDT 24 |
Jul 21 06:40:00 PM PDT 24 |
113979867 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3892395568 |
|
|
Jul 21 06:39:47 PM PDT 24 |
Jul 21 06:39:51 PM PDT 24 |
48574544 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2666976986 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
406974291 ps |
| T984 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.216630281 |
|
|
Jul 21 06:39:58 PM PDT 24 |
Jul 21 06:40:06 PM PDT 24 |
1304157774 ps |
| T985 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3474094252 |
|
|
Jul 21 06:40:01 PM PDT 24 |
Jul 21 06:40:06 PM PDT 24 |
38811745 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1040770459 |
|
|
Jul 21 06:39:47 PM PDT 24 |
Jul 21 06:39:51 PM PDT 24 |
39783842 ps |
| T987 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2024136888 |
|
|
Jul 21 06:39:52 PM PDT 24 |
Jul 21 06:40:00 PM PDT 24 |
141190488 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3550177145 |
|
|
Jul 21 06:39:49 PM PDT 24 |
Jul 21 06:39:54 PM PDT 24 |
16935194 ps |
| T989 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1860081639 |
|
|
Jul 21 06:39:52 PM PDT 24 |
Jul 21 06:39:59 PM PDT 24 |
72136404 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.561063476 |
|
|
Jul 21 06:39:45 PM PDT 24 |
Jul 21 06:39:47 PM PDT 24 |
12457072 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.889000911 |
|
|
Jul 21 06:39:57 PM PDT 24 |
Jul 21 06:40:06 PM PDT 24 |
622562376 ps |
| T992 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1807185185 |
|
|
Jul 21 06:40:03 PM PDT 24 |
Jul 21 06:40:07 PM PDT 24 |
37581219 ps |
| T120 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1982068261 |
|
|
Jul 21 06:39:46 PM PDT 24 |
Jul 21 06:39:50 PM PDT 24 |
176102769 ps |
| T121 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3353937850 |
|
|
Jul 21 06:39:51 PM PDT 24 |
Jul 21 06:39:58 PM PDT 24 |
195906774 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2343509869 |
|
|
Jul 21 06:39:49 PM PDT 24 |
Jul 21 06:39:53 PM PDT 24 |
44639655 ps |
| T994 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.968682427 |
|
|
Jul 21 06:39:51 PM PDT 24 |
Jul 21 06:39:57 PM PDT 24 |
29487538 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.70381138 |
|
|
Jul 21 06:39:49 PM PDT 24 |
Jul 21 06:39:55 PM PDT 24 |
252797054 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.529956150 |
|
|
Jul 21 06:40:04 PM PDT 24 |
Jul 21 06:40:08 PM PDT 24 |
93741996 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4139093651 |
|
|
Jul 21 06:39:41 PM PDT 24 |
Jul 21 06:39:43 PM PDT 24 |
13383789 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3924287141 |
|
|
Jul 21 06:39:41 PM PDT 24 |
Jul 21 06:39:45 PM PDT 24 |
127608596 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2491152498 |
|
|
Jul 21 06:39:40 PM PDT 24 |
Jul 21 06:39:44 PM PDT 24 |
3966402769 ps |
| T1000 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.913851239 |
|
|
Jul 21 06:39:52 PM PDT 24 |
Jul 21 06:40:02 PM PDT 24 |
540580198 ps |
| T1001 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1146217975 |
|
|
Jul 21 06:40:06 PM PDT 24 |
Jul 21 06:40:09 PM PDT 24 |
15308599 ps |