SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[sram_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[sram_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 64694323 | 0 | T1 | 217035 | T2 | 253167 | T4 | 7548 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 64694146 | 1 | T1 | 217035 | T2 | 253167 | T4 | 7548 | ||||
values[1] | 15 | 1 | T67 | 1 | T128 | 1 | T129 | 1 | ||||
values[2] | 3 | 1 | T67 | 1 | T68 | 1 | T130 | 1 | ||||
values[3] | 87 | 1 | T66 | 2 | T67 | 6 | T68 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 64694143 | 1 | T1 | 217035 | T2 | 253167 | T4 | 7548 | ||||
values[1] | 21 | 1 | T67 | 1 | T131 | 1 | T129 | 1 | ||||
values[2] | 9 | 1 | T67 | 2 | T68 | 2 | T128 | 1 | ||||
values[3] | 95 | 1 | T66 | 5 | T67 | 11 | T68 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 64694053 | 1 | T1 | 217035 | T2 | 253167 | T4 | 7548 | ||||
auto[TlIntgErrCmd] | 90 | 1 | T66 | 2 | T67 | 5 | T68 | 3 | ||||
auto[TlIntgErrData] | 93 | 1 | T66 | 6 | T67 | 11 | T68 | 2 | ||||
auto[TlIntgErrBoth] | 87 | 1 | T66 | 2 | T67 | 4 | T68 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 377183 | 0 | T1 | 37 | T2 | 2 | T3 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 376991 | 1 | T1 | 37 | T2 | 2 | T3 | 10 | ||||
values[1] | 25 | 1 | T66 | 2 | T67 | 1 | T131 | 3 | ||||
values[2] | 1 | 1 | T132 | 1 | - | - | - | - | ||||
values[3] | 105 | 1 | T66 | 3 | T67 | 7 | T68 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 376997 | 1 | T1 | 37 | T2 | 2 | T3 | 10 | ||||
values[1] | 20 | 1 | T67 | 2 | T131 | 2 | T133 | 1 | ||||
values[2] | 8 | 1 | T129 | 2 | T134 | 1 | T135 | 2 | ||||
values[3] | 101 | 1 | T66 | 2 | T67 | 12 | T68 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 376913 | 1 | T1 | 37 | T2 | 2 | T3 | 10 | ||||
auto[TlIntgErrCmd] | 84 | 1 | T66 | 5 | T67 | 3 | T68 | 3 | ||||
auto[TlIntgErrData] | 78 | 1 | T66 | 2 | T67 | 8 | T68 | 6 | ||||
auto[TlIntgErrBoth] | 108 | 1 | T66 | 3 | T67 | 9 | T68 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |