Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14508005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

55040270

1

T1

197323

T2

45959

T4

6079

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34677303	1			T1	108724		T2	126644		T4	2886
values[0x0]	15988167	1			T1	52468		T2	42459		T4	1766
values[0x1]	18882805	1			T1	55843		T2	84064		T4	1882

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7233690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62314585

1

T1

207189

T2

150221

T4

6323

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	306969	1			T1	930		T2	1045		T5	215
valid_sources[0x01]	268151	1			T1	835		T2	983		T5	232
valid_sources[0x02]	253113	1			T1	1013		T2	923		T5	267
valid_sources[0x03]	323623	1			T1	858		T2	1059		T5	313
valid_sources[0x04]	285905	1			T1	789		T2	936		T5	233
valid_sources[0x05]	291834	1			T1	900		T2	840		T5	277
valid_sources[0x06]	314969	1			T1	789		T2	1006		T4	161
valid_sources[0x07]	302249	1			T1	942		T2	931		T5	255
valid_sources[0x08]	240177	1			T1	786		T2	1069		T5	266
valid_sources[0x09]	275044	1			T1	793		T2	814		T5	236
valid_sources[0x0a]	257416	1			T1	838		T2	898		T5	256
valid_sources[0x0b]	254062	1			T1	778		T2	1038		T5	256
valid_sources[0x0c]	254174	1			T1	820		T2	1029		T5	273
valid_sources[0x0d]	259911	1			T1	883		T2	861		T5	243
valid_sources[0x0e]	241565	1			T1	817		T2	918		T5	275
valid_sources[0x0f]	283382	1			T1	797		T2	925		T5	272
valid_sources[0x10]	240823	1			T1	822		T2	1066		T5	258
valid_sources[0x11]	324251	1			T1	952		T2	1084		T5	244
valid_sources[0x12]	255905	1			T1	848		T2	1105		T5	232
valid_sources[0x13]	343307	1			T1	891		T2	981		T5	232
valid_sources[0x14]	269322	1			T1	732		T2	1033		T5	273
valid_sources[0x15]	293485	1			T1	800		T2	1093		T5	264
valid_sources[0x16]	258717	1			T1	903		T2	944		T5	266
valid_sources[0x17]	272629	1			T1	847		T2	1044		T5	266
valid_sources[0x18]	249760	1			T1	722		T2	1036		T5	254
valid_sources[0x19]	298324	1			T1	819		T2	1010		T5	223
valid_sources[0x1a]	257561	1			T1	911		T2	960		T5	199
valid_sources[0x1b]	284411	1			T1	822		T2	842		T5	253
valid_sources[0x1c]	331463	1			T1	804		T2	848		T5	222
valid_sources[0x1d]	256704	1			T1	885		T2	940		T5	255
valid_sources[0x1e]	257304	1			T1	942		T2	987		T5	233
valid_sources[0x1f]	241056	1			T1	840		T2	933		T5	221
valid_sources[0x20]	234493	1			T1	873		T2	898		T5	238
valid_sources[0x21]	255722	1			T1	714		T2	914		T5	253
valid_sources[0x22]	247668	1			T1	785		T2	845		T5	238
valid_sources[0x23]	245291	1			T1	717		T2	1136		T5	282
valid_sources[0x24]	243299	1			T1	886		T2	980		T5	314
valid_sources[0x25]	240587	1			T1	750		T2	976		T5	250
valid_sources[0x26]	234504	1			T1	971		T2	1049		T5	225
valid_sources[0x27]	317919	1			T1	643		T2	929		T5	313
valid_sources[0x28]	274377	1			T1	797		T2	989		T5	263
valid_sources[0x29]	262173	1			T1	806		T2	974		T5	237
valid_sources[0x2a]	318030	1			T1	953		T2	924		T5	215
valid_sources[0x2b]	273776	1			T1	867		T2	896		T5	239
valid_sources[0x2c]	248017	1			T1	895		T2	876		T5	289
valid_sources[0x2d]	251002	1			T1	791		T2	1149		T5	257
valid_sources[0x2e]	325171	1			T1	886		T2	1002		T5	234
valid_sources[0x2f]	266934	1			T1	873		T2	1027		T5	241
valid_sources[0x30]	288083	1			T1	960		T2	1070		T5	303
valid_sources[0x31]	280898	1			T1	882		T2	971		T5	252
valid_sources[0x32]	372845	1			T1	788		T2	973		T5	245
valid_sources[0x33]	274584	1			T1	874		T2	900		T5	282
valid_sources[0x34]	242277	1			T1	830		T2	895		T5	300
valid_sources[0x35]	253022	1			T1	922		T2	1067		T5	267
valid_sources[0x36]	299583	1			T1	929		T2	963		T5	308
valid_sources[0x37]	274335	1			T1	892		T2	1066		T5	234
valid_sources[0x38]	247806	1			T1	949		T2	1229		T5	281
valid_sources[0x39]	305970	1			T1	860		T2	1128		T5	265
valid_sources[0x3a]	271978	1			T1	820		T2	1012		T5	298
valid_sources[0x3b]	255909	1			T1	802		T2	1121		T5	219
valid_sources[0x3c]	248357	1			T1	791		T2	982		T5	291
valid_sources[0x3d]	308857	1			T1	811		T2	1003		T5	285
valid_sources[0x3e]	276525	1			T1	814		T2	1087		T4	105
valid_sources[0x3f]	302933	1			T1	779		T2	879		T5	213
valid_sources[0x40]	258783	1			T1	863		T2	918		T5	256
valid_sources[0x41]	280659	1			T1	849		T2	964		T5	264
valid_sources[0x42]	301234	1			T1	796		T2	945		T5	272
valid_sources[0x43]	267188	1			T1	770		T2	949		T5	252
valid_sources[0x44]	260947	1			T1	881		T2	1082		T5	288
valid_sources[0x45]	245483	1			T1	817		T2	1004		T5	264
valid_sources[0x46]	244256	1			T1	850		T2	1003		T5	306
valid_sources[0x47]	281301	1			T1	986		T2	895		T5	247
valid_sources[0x48]	245299	1			T1	723		T2	973		T5	240
valid_sources[0x49]	328644	1			T1	768		T2	1031		T5	270
valid_sources[0x4a]	254129	1			T1	783		T2	1100		T5	250
valid_sources[0x4b]	252273	1			T1	887		T2	921		T5	235
valid_sources[0x4c]	314497	1			T1	1013		T2	833		T5	232
valid_sources[0x4d]	233758	1			T1	861		T2	822		T5	247
valid_sources[0x4e]	295108	1			T1	796		T2	954		T5	277
valid_sources[0x4f]	310006	1			T1	766		T2	967		T5	259
valid_sources[0x50]	266055	1			T1	865		T2	899		T5	250
valid_sources[0x51]	263738	1			T1	789		T2	997		T5	296
valid_sources[0x52]	236657	1			T1	852		T2	1018		T5	272
valid_sources[0x53]	259603	1			T1	772		T2	980		T5	255
valid_sources[0x54]	242191	1			T1	943		T2	1040		T5	295
valid_sources[0x55]	264509	1			T1	985		T2	842		T5	270
valid_sources[0x56]	284833	1			T1	890		T2	1121		T5	287
valid_sources[0x57]	243329	1			T1	786		T2	983		T5	222
valid_sources[0x58]	241858	1			T1	882		T2	913		T5	194
valid_sources[0x59]	280389	1			T1	875		T2	1044		T5	249
valid_sources[0x5a]	263517	1			T1	856		T2	1038		T5	283
valid_sources[0x5b]	258493	1			T1	772		T2	1107		T5	256
valid_sources[0x5c]	237639	1			T1	809		T2	779		T5	285
valid_sources[0x5d]	257421	1			T1	968		T2	970		T5	232
valid_sources[0x5e]	309034	1			T1	910		T2	1096		T5	278
valid_sources[0x5f]	245283	1			T1	828		T2	980		T5	227
valid_sources[0x60]	268037	1			T1	883		T2	1181		T5	228
valid_sources[0x61]	270206	1			T1	777		T2	970		T5	293
valid_sources[0x62]	315099	1			T1	919		T2	1000		T5	247
valid_sources[0x63]	269403	1			T1	757		T2	946		T5	275
valid_sources[0x64]	242320	1			T1	802		T2	1166		T5	257
valid_sources[0x65]	258725	1			T1	633		T2	1021		T5	232
valid_sources[0x66]	258534	1			T1	775		T2	995		T5	262
valid_sources[0x67]	293106	1			T1	806		T2	949		T5	304
valid_sources[0x68]	250223	1			T1	774		T2	1035		T4	2457
valid_sources[0x69]	301861	1			T1	737		T2	1010		T5	238
valid_sources[0x6a]	262092	1			T1	806		T2	990		T4	150
valid_sources[0x6b]	253449	1			T1	858		T2	1038		T5	213
valid_sources[0x6c]	287480	1			T1	869		T2	1098		T5	227
valid_sources[0x6d]	249196	1			T1	786		T2	1002		T5	273
valid_sources[0x6e]	242587	1			T1	781		T2	962		T5	283
valid_sources[0x6f]	281461	1			T1	923		T2	1116		T5	213
valid_sources[0x70]	272636	1			T1	1023		T2	1042		T5	225
valid_sources[0x71]	246314	1			T1	738		T2	842		T5	236
valid_sources[0x72]	309105	1			T1	771		T2	858		T5	246
valid_sources[0x73]	297058	1			T1	851		T2	949		T5	206
valid_sources[0x74]	260514	1			T1	834		T2	1038		T5	215
valid_sources[0x75]	254533	1			T1	752		T2	942		T5	303
valid_sources[0x76]	263592	1			T1	774		T2	928		T5	255
valid_sources[0x77]	269522	1			T1	847		T2	1171		T5	312
valid_sources[0x78]	269625	1			T1	894		T2	964		T5	322
valid_sources[0x79]	244382	1			T1	923		T2	901		T5	258
valid_sources[0x7a]	248224	1			T1	857		T2	1130		T5	276
valid_sources[0x7b]	304962	1			T1	948		T2	1012		T5	230
valid_sources[0x7c]	237745	1			T1	706		T2	939		T5	263
valid_sources[0x7d]	246604	1			T1	838		T2	886		T5	277
valid_sources[0x7e]	240381	1			T1	843		T2	1039		T5	250
valid_sources[0x7f]	254687	1			T1	755		T2	802		T5	272
valid_sources[0x80]	274166	1			T1	749		T2	967		T5	262

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27424712

1

T1

98819

T2

22852

T4

2640

values[0x0]

all_enables

biggest_size

13809672

1

T1

49483

T2

11487

T4

1711

values[0x1]

all_enables

biggest_size

13805886

1

T1

49021

T2

11620

T4

1728

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

128850

1

T1

3

T2

2

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48026	1			T4	337		T27	4		T23	638
values[0x0]	55657	1			T1	19		T2	2		T3	8
values[0x1]	60191	1			T1	18		T3	2		T4	525

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

137321

1

T1

5

T2

2

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	884	1			T1	1		T4	2		T19	1
valid_sources[0x01]	807	1			T4	5		T28	1		T19	1
valid_sources[0x02]	549	1			T4	5		T7	1		T107	1
valid_sources[0x03]	567	1			T4	1		T28	1		T27	2
valid_sources[0x04]	761	1			T4	7		T26	19		T21	18
valid_sources[0x05]	599	1			T4	8		T42	1		T23	3
valid_sources[0x06]	699	1			T1	1		T4	8		T142	2
valid_sources[0x07]	565	1			T4	9		T28	1		T142	1
valid_sources[0x08]	730	1			T4	6		T7	2		T26	1
valid_sources[0x09]	526	1			T4	9		T42	1		T7	2
valid_sources[0x0a]	919	1			T4	4		T19	1		T7	1
valid_sources[0x0b]	871	1			T4	2		T19	1		T7	1
valid_sources[0x0c]	699	1			T4	3		T96	1		T8	1
valid_sources[0x0d]	695	1			T4	9		T42	2		T19	1
valid_sources[0x0e]	703	1			T4	4		T42	2		T82	1
valid_sources[0x0f]	590	1			T4	7		T7	2		T97	6
valid_sources[0x10]	528	1			T4	5		T8	6		T69	7
valid_sources[0x11]	441	1			T4	3		T19	1		T7	1
valid_sources[0x12]	555	1			T4	7		T7	1		T107	1
valid_sources[0x13]	555	1			T4	10		T7	1		T142	1
valid_sources[0x14]	592	1			T4	4		T27	1		T29	1
valid_sources[0x15]	553	1			T4	4		T42	1		T23	4
valid_sources[0x16]	587	1			T4	1		T23	10		T7	2
valid_sources[0x17]	685	1			T4	8		T27	1		T72	1
valid_sources[0x18]	523	1			T4	5		T42	1		T7	1
valid_sources[0x19]	723	1			T4	6		T7	3		T142	1
valid_sources[0x1a]	456	1			T1	1		T4	4		T13	1
valid_sources[0x1b]	538	1			T4	7		T13	2		T7	1
valid_sources[0x1c]	893	1			T4	8		T23	233		T147	1
valid_sources[0x1d]	839	1			T4	8		T7	2		T148	1
valid_sources[0x1e]	497	1			T4	3		T28	1		T7	1
valid_sources[0x1f]	491	1			T4	4		T64	2		T21	17
valid_sources[0x20]	781	1			T4	14		T19	1		T7	1
valid_sources[0x21]	638	1			T4	2		T11	4		T28	1
valid_sources[0x22]	479	1			T4	4		T142	1		T149	1
valid_sources[0x23]	560	1			T4	10		T7	1		T26	9
valid_sources[0x24]	561	1			T4	4		T13	3		T28	1
valid_sources[0x25]	682	1			T4	8		T25	3		T42	1
valid_sources[0x26]	694	1			T4	10		T50	1		T19	1
valid_sources[0x27]	424	1			T1	1		T4	1		T5	1
valid_sources[0x28]	557	1			T4	5		T19	1		T142	1
valid_sources[0x29]	551	1			T4	2		T28	1		T7	1
valid_sources[0x2a]	442	1			T4	4		T7	1		T26	1
valid_sources[0x2b]	648	1			T4	6		T19	1		T142	1
valid_sources[0x2c]	658	1			T4	2		T48	1		T19	1
valid_sources[0x2d]	449	1			T1	3		T4	5		T19	1
valid_sources[0x2e]	598	1			T4	11		T28	1		T107	1
valid_sources[0x2f]	664	1			T4	6		T71	1		T19	1
valid_sources[0x30]	731	1			T4	7		T149	2		T80	1
valid_sources[0x31]	580	1			T4	4		T19	2		T140	1
valid_sources[0x32]	779	1			T4	2		T23	169		T8	4
valid_sources[0x33]	608	1			T4	4		T7	1		T26	21
valid_sources[0x34]	742	1			T4	4		T10	1		T28	1
valid_sources[0x35]	735	1			T1	1		T4	3		T26	1
valid_sources[0x36]	804	1			T4	12		T23	6		T26	2
valid_sources[0x37]	862	1			T4	4		T12	10		T7	1
valid_sources[0x38]	504	1			T4	3		T26	1		T21	22
valid_sources[0x39]	479	1			T4	3		T13	1		T52	3
valid_sources[0x3a]	623	1			T4	3		T19	1		T7	1
valid_sources[0x3b]	621	1			T4	9		T7	1		T80	1
valid_sources[0x3c]	786	1			T4	3		T7	2		T26	25
valid_sources[0x3d]	882	1			T4	12		T27	1		T7	1
valid_sources[0x3e]	684	1			T4	6		T7	2		T26	10
valid_sources[0x3f]	716	1			T4	4		T19	1		T142	2
valid_sources[0x40]	548	1			T4	5		T7	1		T26	12
valid_sources[0x41]	856	1			T4	7		T13	1		T7	3
valid_sources[0x42]	658	1			T4	8		T7	1		T57	3
valid_sources[0x43]	615	1			T4	7		T7	1		T96	2
valid_sources[0x44]	943	1			T4	9		T5	2		T106	3
valid_sources[0x45]	758	1			T4	1		T7	3		T26	53
valid_sources[0x46]	678	1			T1	2		T4	7		T44	1
valid_sources[0x47]	536	1			T4	7		T11	4		T23	4
valid_sources[0x48]	547	1			T4	3		T19	1		T7	1
valid_sources[0x49]	546	1			T1	1		T4	5		T19	1
valid_sources[0x4a]	657	1			T4	10		T7	2		T26	20
valid_sources[0x4b]	482	1			T4	3		T7	1		T108	3
valid_sources[0x4c]	772	1			T4	2		T27	1		T150	1
valid_sources[0x4d]	438	1			T1	1		T4	3		T28	1
valid_sources[0x4e]	666	1			T26	1		T21	30		T51	7
valid_sources[0x4f]	931	1			T4	4		T26	2		T80	2
valid_sources[0x50]	521	1			T4	4		T7	1		T151	2
valid_sources[0x51]	641	1			T4	9		T23	122		T19	1
valid_sources[0x52]	481	1			T4	5		T28	1		T50	1
valid_sources[0x53]	667	1			T4	13		T27	1		T7	1
valid_sources[0x54]	644	1			T4	10		T23	160		T7	3
valid_sources[0x55]	629	1			T4	8		T28	1		T23	6
valid_sources[0x56]	570	1			T4	3		T22	1		T152	1
valid_sources[0x57]	602	1			T4	4		T7	3		T21	15
valid_sources[0x58]	757	1			T4	4		T19	2		T153	14
valid_sources[0x59]	583	1			T4	6		T50	1		T19	1
valid_sources[0x5a]	652	1			T4	6		T154	1		T26	3
valid_sources[0x5b]	607	1			T4	4		T13	2		T7	1
valid_sources[0x5c]	638	1			T4	1		T19	1		T7	1
valid_sources[0x5d]	774	1			T4	5		T56	1		T19	1
valid_sources[0x5e]	615	1			T4	3		T23	3		T19	1
valid_sources[0x5f]	538	1			T1	2		T4	9		T148	1
valid_sources[0x60]	547	1			T4	6		T13	2		T7	1
valid_sources[0x61]	548	1			T4	6		T28	2		T7	1
valid_sources[0x62]	775	1			T4	5		T23	101		T7	1
valid_sources[0x63]	738	1			T4	1		T23	162		T7	2
valid_sources[0x64]	873	1			T4	2		T140	1		T152	1
valid_sources[0x65]	643	1			T4	9		T27	1		T142	2
valid_sources[0x66]	704	1			T4	3		T62	1		T23	176
valid_sources[0x67]	773	1			T4	2		T26	49		T21	16
valid_sources[0x68]	823	1			T4	4		T48	1		T142	1
valid_sources[0x69]	508	1			T4	7		T42	1		T72	1
valid_sources[0x6a]	694	1			T4	3		T19	1		T21	21
valid_sources[0x6b]	491	1			T4	2		T26	4		T80	1
valid_sources[0x6c]	715	1			T4	6		T10	5		T19	1
valid_sources[0x6d]	608	1			T4	1		T19	2		T7	1
valid_sources[0x6e]	632	1			T4	2		T7	2		T26	28
valid_sources[0x6f]	683	1			T4	4		T28	1		T52	2
valid_sources[0x70]	554	1			T1	3		T4	7		T19	1
valid_sources[0x71]	704	1			T4	4		T19	1		T7	1
valid_sources[0x72]	926	1			T4	1		T23	103		T142	1
valid_sources[0x73]	560	1			T4	3		T26	14		T21	15
valid_sources[0x74]	574	1			T4	7		T7	1		T26	10
valid_sources[0x75]	713	1			T4	4		T19	3		T26	48
valid_sources[0x76]	921	1			T4	4		T23	189		T142	1
valid_sources[0x77]	498	1			T4	1		T19	1		T7	1
valid_sources[0x78]	635	1			T2	2		T4	6		T28	1
valid_sources[0x79]	582	1			T4	5		T19	1		T142	1
valid_sources[0x7a]	540	1			T4	12		T19	1		T55	1
valid_sources[0x7b]	628	1			T4	2		T23	3		T14	1
valid_sources[0x7c]	637	1			T4	5		T150	1		T26	1
valid_sources[0x7d]	501	1			T4	11		T7	1		T139	2
valid_sources[0x7e]	699	1			T4	3		T56	1		T26	5
valid_sources[0x7f]	540	1			T4	3		T11	2		T19	1
valid_sources[0x80]	544	1			T4	5		T50	1		T62	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35623

1

T4

308

T27

1

T23

577

values[0x0]

all_enables

biggest_size

47602

1

T1

3

T2

2

T3

3

values[0x1]

all_enables

biggest_size

45625

1

T3

1

T4

479

T9

1