Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14230556

1

T1

19712

T2

207208

T4

1360

full_word

50463767

1

T1

197323

T2

45959

T4

6188

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64694053	1			T1	217035		T2	253167		T4	7548
auto[TlIntgErrCmd]	90	1			T66	2		T67	5		T68	3
auto[TlIntgErrData]	93	1			T66	6		T67	11		T68	2
auto[TlIntgErrBoth]	87	1			T66	2		T67	4		T68	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29778996

1

T1

108724

T2

126644

T4

3088

auto[1]

34915327

1

T1

108311

T2

126523

T4

4460

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6840358	1			T1	9905		T2	103792		T4	427
auto[TlIntgErrNone]	partial	auto[1]	7389955	1			T1	9807		T2	103416		T4	933
auto[TlIntgErrNone]	full_word	auto[0]	22938516	1			T1	98819		T2	22852		T4	2661
auto[TlIntgErrNone]	full_word	auto[1]	27525224	1			T1	98504		T2	23107		T4	3527
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T66	2		T67	2		T68	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T67	1		T68	1		T131	7
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T67	2		T136	1		T135	3
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T68	1		T133	1		T137	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T66	2		T67	4		T68	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T66	4		T67	6		T131	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T67	1		T129	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T68	1		T131	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T66	1		T67	1		T68	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T66	1		T67	3		T68	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T68	1		T138	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T130	1		T135	1		-	-