Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	655862	1			T2	15981		T5	141		T9	15
auto[1]	10432568	1			T1	50571		T2	16773		T4	2488
auto[2]	547909	1			T2	15721		T5	80		T9	10
auto[3]	10326019	1			T1	50395		T2	17283		T4	2445

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13988226	1			T1	84257		T2	1308		T4	4101
auto[1]	2100765	1			T1	7961		T2	7160		T4	382
auto[2]	2127558	1			T1	7974		T2	9447		T4	408
auto[3]	3745809	1			T1	774		T2	47843		T4	42

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8228128

1

T1

100867

T4

4926

T5

2363

auto[1]

13734230

1

T1

99

T2

65758

T4

7

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	226700	1			T5	128		T13	1377		T27	9
auto[0]	auto[0]	auto[1]	23856	1			T5	7		T13	113		T27	1
auto[0]	auto[0]	auto[2]	23964	1			T5	5		T13	148		T65	45
auto[0]	auto[0]	auto[3]	8969	1			T5	1		T9	15		T13	6
auto[0]	auto[1]	auto[0]	3145277	1			T1	42155		T4	2050		T5	844
auto[0]	auto[1]	auto[1]	327921	1			T1	3785		T4	190		T5	157
auto[0]	auto[1]	auto[2]	319657	1			T1	4212		T4	217		T5	83
auto[0]	auto[1]	auto[3]	78432	1			T1	372		T4	27		T5	13
auto[0]	auto[2]	auto[0]	193153	1			T13	1203		T23	645		T6	13
auto[0]	auto[2]	auto[1]	20177	1			T13	119		T23	68		T19	155
auto[0]	auto[2]	auto[2]	22232	1			T5	72		T10	1		T13	78
auto[0]	auto[2]	auto[3]	7178	1			T5	8		T9	10		T10	1
auto[0]	auto[3]	auto[0]	3108796	1			T1	42030		T4	2045		T5	725
auto[0]	auto[3]	auto[1]	316223	1			T1	4164		T4	191		T5	70
auto[0]	auto[3]	auto[2]	326485	1			T1	3749		T4	191		T5	220
auto[0]	auto[3]	auto[3]	79108	1			T1	400		T4	15		T5	30
auto[1]	auto[0]	auto[0]	12191	1			T2	532		T10	143		T13	1
auto[1]	auto[0]	auto[1]	55696	1			T2	2407		T10	677		T13	2
auto[1]	auto[0]	auto[2]	55619	1			T2	2401		T10	663		T107	1091
auto[1]	auto[0]	auto[3]	248867	1			T2	10641		T10	3031		T107	4721
auto[1]	auto[1]	auto[0]	3650210	1			T1	35		T2	332		T4	3
auto[1]	auto[1]	auto[1]	680755	1			T1	5		T2	2763		T4	1
auto[1]	auto[1]	auto[2]	658883	1			T1	6		T2	1541		T10	1213
auto[1]	auto[1]	auto[3]	1571433	1			T1	1		T2	12137		T10	10558
auto[1]	auto[2]	auto[0]	8159	1			T2	302		T13	1		T23	3
auto[1]	auto[2]	auto[1]	36152	1			T2	1432		T145	4996		T146	1
auto[1]	auto[2]	auto[2]	47111	1			T2	2482		T10	615		T19	1
auto[1]	auto[2]	auto[3]	213747	1			T2	11505		T10	2718		T107	4325
auto[1]	auto[3]	auto[0]	3643740	1			T1	37		T2	142		T4	3
auto[1]	auto[3]	auto[1]	639985	1			T1	7		T2	558		T10	560
auto[1]	auto[3]	auto[2]	673607	1			T1	7		T2	3023		T10	2228
auto[1]	auto[3]	auto[3]	1538075	1			T1	1		T2	13560		T10	10162