Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	294899193	195791	0	0
ctrl_regwen_rd_A	294899193	3278	0	0
exec_rd_A	294899193	3369	0	0
exec_regwen_rd_A	294899193	3566	0	0
readback_rd_A	294899193	1456	0	0
readback_regwen_rd_A	294899193	1259	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294899193	195791	0	0
T4	13702	1183	0	0
T5	439881	0	0	0
T9	9305	0	0	0
T10	142913	0	0	0
T11	65788	0	0	0
T12	33159	0	0	0
T13	640091	0	0	0
T21	0	7126	0	0
T23	0	3657	0	0
T24	175606	0	0	0
T26	0	4650	0	0
T44	12177	0	0	0
T45	150528	0	0	0
T46	0	3081	0	0
T51	0	5444	0	0
T60	0	4713	0	0
T77	0	2849	0	0
T78	0	1538	0	0
T79	0	3882	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294899193	3278	0	0
T51	128349	192	0	0
T78	0	99	0	0
T81	152400	0	0	0
T111	0	60	0	0
T112	0	130	0	0
T113	0	118	0	0
T114	0	22	0	0
T115	0	114	0	0
T116	0	132	0	0
T117	0	205	0	0
T118	0	227	0	0
T119	8854	0	0	0
T120	7768	0	0	0
T121	14993	0	0	0
T122	79674	0	0	0
T123	17043	0	0	0
T124	43610	0	0	0
T125	91945	0	0	0
T126	73761	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294899193	3369	0	0
T51	128349	158	0	0
T78	0	52	0	0
T81	152400	0	0	0
T111	0	48	0	0
T112	0	113	0	0
T113	0	90	0	0
T114	0	44	0	0
T115	0	102	0	0
T116	0	141	0	0
T117	0	188	0	0
T118	0	228	0	0
T119	8854	0	0	0
T120	7768	0	0	0
T121	14993	0	0	0
T122	79674	0	0	0
T123	17043	0	0	0
T124	43610	0	0	0
T125	91945	0	0	0
T126	73761	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294899193	3566	0	0
T51	128349	217	0	0
T78	0	98	0	0
T81	152400	0	0	0
T111	0	68	0	0
T112	0	141	0	0
T113	0	130	0	0
T114	0	63	0	0
T115	0	143	0	0
T116	0	142	0	0
T117	0	220	0	0
T118	0	341	0	0
T119	8854	0	0	0
T120	7768	0	0	0
T121	14993	0	0	0
T122	79674	0	0	0
T123	17043	0	0	0
T124	43610	0	0	0
T125	91945	0	0	0
T126	73761	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294899193	1456	0	0
T51	128349	171	0	0
T78	0	75	0	0
T81	152400	0	0	0
T111	0	11	0	0
T112	0	133	0	0
T113	0	58	0	0
T114	0	27	0	0
T115	0	109	0	0
T116	0	135	0	0
T117	0	146	0	0
T118	0	271	0	0
T119	8854	0	0	0
T120	7768	0	0	0
T121	14993	0	0	0
T122	79674	0	0	0
T123	17043	0	0	0
T124	43610	0	0	0
T125	91945	0	0	0
T126	73761	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	294899193	1259	0	0
T51	128349	141	0	0
T78	0	42	0	0
T81	152400	0	0	0
T111	0	18	0	0
T112	0	117	0	0
T113	0	87	0	0
T114	0	44	0	0
T115	0	89	0	0
T116	0	75	0	0
T117	0	145	0	0
T118	0	160	0	0
T119	8854	0	0	0
T120	7768	0	0	0
T121	14993	0	0	0
T122	79674	0	0	0
T123	17043	0	0	0
T124	43610	0	0	0
T125	91945	0	0	0
T126	73761	0	0	0