Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14570298	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

62708043

1

T1

40071

T3

117120

T4

14062

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38524708	1			T1	110079		T3	644473		T4	6802
values[0x0]	17923488	1			T1	37130		T3	310067		T4	4033
values[0x1]	20830145	1			T1	73205		T3	334168		T4	4358

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7258901	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

70019440

1

T1

130681

T3

123023

T4

14624

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	293821	1			T1	844		T3	5135		T4	46
valid_sources[0x01]	290872	1			T1	881		T3	5002		T4	51
valid_sources[0x02]	354361	1			T1	914		T3	5019		T4	68
valid_sources[0x03]	282923	1			T1	840		T3	5227		T4	47
valid_sources[0x04]	300229	1			T1	938		T3	5250		T4	58
valid_sources[0x05]	345311	1			T1	920		T3	4928		T4	58
valid_sources[0x06]	288148	1			T1	865		T3	4966		T4	57
valid_sources[0x07]	312632	1			T1	873		T3	5389		T4	49
valid_sources[0x08]	265870	1			T1	878		T3	4662		T4	54
valid_sources[0x09]	366347	1			T1	844		T3	5127		T4	54
valid_sources[0x0a]	312810	1			T1	835		T3	4816		T4	37
valid_sources[0x0b]	288869	1			T1	877		T3	5195		T4	56
valid_sources[0x0c]	347420	1			T1	880		T3	5063		T4	56
valid_sources[0x0d]	310655	1			T1	840		T3	4837		T4	51
valid_sources[0x0e]	301501	1			T1	828		T3	5157		T4	54
valid_sources[0x0f]	309600	1			T1	845		T3	5148		T4	44
valid_sources[0x10]	321540	1			T1	824		T3	4743		T4	49
valid_sources[0x11]	300932	1			T1	848		T3	5350		T4	53
valid_sources[0x12]	326897	1			T1	845		T3	4736		T4	66
valid_sources[0x13]	287332	1			T1	932		T3	5171		T4	63
valid_sources[0x14]	269959	1			T1	902		T3	4968		T4	64
valid_sources[0x15]	285934	1			T1	846		T3	4451		T4	58
valid_sources[0x16]	317713	1			T1	841		T3	5013		T4	60
valid_sources[0x17]	320624	1			T1	874		T3	5101		T4	55
valid_sources[0x18]	338666	1			T1	826		T3	5249		T4	60
valid_sources[0x19]	324680	1			T1	849		T3	5602		T4	57
valid_sources[0x1a]	271358	1			T1	829		T3	4551		T4	65
valid_sources[0x1b]	295159	1			T1	913		T3	5177		T4	74
valid_sources[0x1c]	322451	1			T1	802		T3	4945		T4	55
valid_sources[0x1d]	283812	1			T1	894		T3	4737		T4	52
valid_sources[0x1e]	285805	1			T1	832		T3	5285		T4	58
valid_sources[0x1f]	282929	1			T1	840		T3	5599		T4	70
valid_sources[0x20]	276595	1			T1	861		T3	4840		T4	61
valid_sources[0x21]	368062	1			T1	899		T3	5510		T4	52
valid_sources[0x22]	276277	1			T1	863		T3	5322		T4	42
valid_sources[0x23]	314025	1			T1	864		T3	5368		T4	78
valid_sources[0x24]	338983	1			T1	905		T3	5066		T4	42
valid_sources[0x25]	381547	1			T1	873		T3	4893		T4	65
valid_sources[0x26]	283873	1			T1	846		T3	5016		T4	67
valid_sources[0x27]	287782	1			T1	861		T3	4710		T4	57
valid_sources[0x28]	281906	1			T1	837		T3	4879		T4	58
valid_sources[0x29]	274299	1			T1	808		T3	5032		T4	50
valid_sources[0x2a]	274334	1			T1	842		T3	5124		T4	76
valid_sources[0x2b]	306713	1			T1	868		T3	4952		T4	58
valid_sources[0x2c]	312276	1			T1	869		T3	4823		T4	60
valid_sources[0x2d]	283749	1			T1	833		T3	4955		T4	76
valid_sources[0x2e]	308338	1			T1	893		T3	5094		T4	52
valid_sources[0x2f]	267068	1			T1	898		T3	5064		T4	53
valid_sources[0x30]	315619	1			T1	812		T3	5293		T4	53
valid_sources[0x31]	317431	1			T1	853		T3	4951		T4	69
valid_sources[0x32]	274126	1			T1	849		T3	5431		T4	78
valid_sources[0x33]	276597	1			T1	874		T3	5355		T4	55
valid_sources[0x34]	322768	1			T1	922		T3	4871		T4	64
valid_sources[0x35]	305014	1			T1	857		T3	5044		T4	59
valid_sources[0x36]	279048	1			T1	819		T3	4817		T4	70
valid_sources[0x37]	317105	1			T1	842		T3	4697		T4	52
valid_sources[0x38]	281511	1			T1	881		T3	5493		T4	54
valid_sources[0x39]	308934	1			T1	890		T3	4847		T4	62
valid_sources[0x3a]	275069	1			T1	872		T3	4989		T4	58
valid_sources[0x3b]	267580	1			T1	834		T3	4680		T4	65
valid_sources[0x3c]	334243	1			T1	839		T3	5189		T4	49
valid_sources[0x3d]	286645	1			T1	812		T3	4871		T4	61
valid_sources[0x3e]	274372	1			T1	863		T3	5297		T4	62
valid_sources[0x3f]	279145	1			T1	941		T3	4664		T4	68
valid_sources[0x40]	295098	1			T1	803		T3	4731		T4	54
valid_sources[0x41]	290220	1			T1	895		T3	5495		T4	70
valid_sources[0x42]	427196	1			T1	845		T3	5158		T4	64
valid_sources[0x43]	278953	1			T1	922		T3	5381		T4	51
valid_sources[0x44]	298572	1			T1	856		T3	4598		T4	58
valid_sources[0x45]	313497	1			T1	792		T3	5242		T4	63
valid_sources[0x46]	319768	1			T1	851		T3	5121		T4	47
valid_sources[0x47]	267054	1			T1	856		T3	4659		T4	58
valid_sources[0x48]	309172	1			T1	909		T3	4906		T4	63
valid_sources[0x49]	288296	1			T1	890		T3	4784		T4	74
valid_sources[0x4a]	299936	1			T1	872		T3	4899		T4	60
valid_sources[0x4b]	352892	1			T1	839		T3	5069		T4	64
valid_sources[0x4c]	292043	1			T1	889		T3	4927		T4	49
valid_sources[0x4d]	287706	1			T1	863		T3	4520		T4	65
valid_sources[0x4e]	276556	1			T1	856		T3	5095		T4	70
valid_sources[0x4f]	315546	1			T1	895		T3	5176		T4	57
valid_sources[0x50]	343778	1			T1	845		T3	5469		T4	59
valid_sources[0x51]	310882	1			T1	924		T3	4801		T4	72
valid_sources[0x52]	307322	1			T1	858		T3	5018		T4	52
valid_sources[0x53]	322009	1			T1	895		T3	5392		T4	44
valid_sources[0x54]	300792	1			T1	810		T3	5080		T4	58
valid_sources[0x55]	274222	1			T1	822		T3	5467		T4	54
valid_sources[0x56]	306066	1			T1	859		T3	5237		T4	56
valid_sources[0x57]	268581	1			T1	868		T3	4821		T4	65
valid_sources[0x58]	293093	1			T1	856		T3	4848		T4	53
valid_sources[0x59]	273560	1			T1	784		T3	4878		T4	67
valid_sources[0x5a]	272749	1			T1	847		T3	5325		T4	47
valid_sources[0x5b]	290556	1			T1	816		T3	5219		T4	69
valid_sources[0x5c]	279748	1			T1	839		T3	5215		T4	42
valid_sources[0x5d]	264864	1			T1	879		T3	4794		T4	50
valid_sources[0x5e]	298737	1			T1	934		T3	5123		T4	65
valid_sources[0x5f]	300369	1			T1	810		T3	5092		T4	51
valid_sources[0x60]	319210	1			T1	823		T3	5391		T4	52
valid_sources[0x61]	286519	1			T1	815		T3	4714		T4	53
valid_sources[0x62]	342592	1			T1	865		T3	5483		T4	53
valid_sources[0x63]	271109	1			T1	868		T3	4888		T4	54
valid_sources[0x64]	270100	1			T1	915		T3	5052		T4	67
valid_sources[0x65]	307203	1			T1	833		T3	5350		T4	65
valid_sources[0x66]	266698	1			T1	837		T3	4988		T4	62
valid_sources[0x67]	302552	1			T1	882		T3	5004		T4	56
valid_sources[0x68]	276492	1			T1	887		T3	5436		T4	60
valid_sources[0x69]	294821	1			T1	813		T3	4761		T4	72
valid_sources[0x6a]	290241	1			T1	878		T3	4997		T4	59
valid_sources[0x6b]	354331	1			T1	847		T3	5221		T4	51
valid_sources[0x6c]	307991	1			T1	888		T3	5299		T4	61
valid_sources[0x6d]	276147	1			T1	850		T3	4900		T4	50
valid_sources[0x6e]	290442	1			T1	850		T3	5007		T4	54
valid_sources[0x6f]	322732	1			T1	865		T3	4793		T4	67
valid_sources[0x70]	328115	1			T1	871		T3	4896		T4	56
valid_sources[0x71]	286828	1			T1	812		T3	4913		T4	71
valid_sources[0x72]	344439	1			T1	820		T3	4873		T4	48
valid_sources[0x73]	338568	1			T1	869		T3	4984		T4	59
valid_sources[0x74]	328636	1			T1	906		T3	5207		T4	50
valid_sources[0x75]	333886	1			T1	920		T3	5101		T4	58
valid_sources[0x76]	295486	1			T1	840		T3	5217		T4	60
valid_sources[0x77]	291347	1			T1	870		T3	5325		T4	68
valid_sources[0x78]	288767	1			T1	869		T3	4929		T4	63
valid_sources[0x79]	303649	1			T1	829		T3	5166		T4	62
valid_sources[0x7a]	349483	1			T1	793		T3	4949		T4	76
valid_sources[0x7b]	321590	1			T1	887		T3	5075		T4	55
valid_sources[0x7c]	312578	1			T1	820		T3	5491		T4	55
valid_sources[0x7d]	282303	1			T1	914		T3	4436		T4	52
valid_sources[0x7e]	325350	1			T1	832		T3	5406		T4	50
valid_sources[0x7f]	271622	1			T1	868		T3	4802		T4	66
valid_sources[0x80]	282636	1			T1	871		T3	4946		T4	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31245465

1

T1

20069

T3

585997

T4

6235

values[0x0]

all_enables

biggest_size

15736520

1

T1

9962

T3

292424

T4

3863

values[0x1]

all_enables

biggest_size

15726058

1

T1

10040

T3

292782

T4

3964

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38437	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

151695

1

T1

1

T2

1

T3

145

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54934	1			T3	109		T4	593		T10	18
values[0x0]	65150	1			T1	2		T2	5		T3	202
values[0x1]	70048	1			T1	1		T2	2		T3	193

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161069

1

T1

1

T2

1

T3

191

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	747	1			T4	2		T5	7		T20	4
valid_sources[0x01]	722	1			T4	16		T5	1		T20	12
valid_sources[0x02]	904	1			T4	13		T5	1		T20	9
valid_sources[0x03]	590	1			T4	14		T5	1		T20	13
valid_sources[0x04]	821	1			T3	4		T4	13		T5	2
valid_sources[0x05]	863	1			T3	3		T4	13		T20	9
valid_sources[0x06]	610	1			T4	21		T35	1		T5	3
valid_sources[0x07]	861	1			T3	2		T4	8		T5	3
valid_sources[0x08]	630	1			T4	9		T20	11		T19	10
valid_sources[0x09]	591	1			T4	29		T5	1		T20	6
valid_sources[0x0a]	740	1			T4	15		T5	2		T20	14
valid_sources[0x0b]	690	1			T4	9		T20	16		T19	22
valid_sources[0x0c]	869	1			T3	3		T4	5		T5	4
valid_sources[0x0d]	609	1			T3	8		T4	2		T20	17
valid_sources[0x0e]	1068	1			T4	21		T20	6		T19	5
valid_sources[0x0f]	652	1			T4	14		T10	1		T20	16
valid_sources[0x10]	596	1			T3	2		T5	2		T20	17
valid_sources[0x11]	640	1			T4	12		T20	13		T19	14
valid_sources[0x12]	995	1			T3	2		T4	13		T20	1
valid_sources[0x13]	870	1			T4	25		T20	15		T136	1
valid_sources[0x14]	783	1			T4	4		T20	33		T19	22
valid_sources[0x15]	590	1			T4	11		T5	2		T20	14
valid_sources[0x16]	681	1			T3	6		T4	7		T5	2
valid_sources[0x17]	646	1			T4	8		T20	5		T19	9
valid_sources[0x18]	813	1			T4	5		T20	16		T19	12
valid_sources[0x19]	1066	1			T4	13		T20	5		T74	1
valid_sources[0x1a]	707	1			T4	9		T20	12		T19	12
valid_sources[0x1b]	560	1			T3	1		T4	13		T5	3
valid_sources[0x1c]	731	1			T3	4		T4	1		T20	12
valid_sources[0x1d]	783	1			T3	5		T4	9		T20	11
valid_sources[0x1e]	703	1			T4	7		T10	8		T5	3
valid_sources[0x1f]	765	1			T4	1		T5	1		T20	18
valid_sources[0x20]	807	1			T4	10		T75	1		T36	5
valid_sources[0x21]	803	1			T4	10		T20	5		T19	10
valid_sources[0x22]	691	1			T4	9		T34	1		T20	5
valid_sources[0x23]	560	1			T4	2		T5	2		T20	3
valid_sources[0x24]	712	1			T3	4		T4	13		T20	9
valid_sources[0x25]	791	1			T3	1		T5	5		T20	2
valid_sources[0x26]	768	1			T4	8		T5	3		T20	2
valid_sources[0x27]	593	1			T4	7		T20	1		T137	2
valid_sources[0x28]	638	1			T3	4		T4	14		T34	1
valid_sources[0x29]	695	1			T4	8		T5	1		T20	13
valid_sources[0x2a]	727	1			T4	3		T20	11		T19	11
valid_sources[0x2b]	765	1			T4	6		T5	1		T20	13
valid_sources[0x2c]	852	1			T4	8		T35	1		T5	1
valid_sources[0x2d]	645	1			T4	12		T34	3		T5	3
valid_sources[0x2e]	565	1			T4	4		T20	5		T19	3
valid_sources[0x2f]	610	1			T4	6		T10	8		T5	4
valid_sources[0x30]	716	1			T2	7		T3	1		T4	15
valid_sources[0x31]	740	1			T3	1		T4	18		T5	4
valid_sources[0x32]	853	1			T4	20		T10	6		T35	6
valid_sources[0x33]	679	1			T4	4		T20	16		T19	2
valid_sources[0x34]	646	1			T3	6		T4	13		T5	1
valid_sources[0x35]	618	1			T3	1		T4	12		T34	1
valid_sources[0x36]	615	1			T4	7		T20	17		T19	5
valid_sources[0x37]	658	1			T20	11		T19	4		T42	4
valid_sources[0x38]	735	1			T3	1		T4	5		T5	3
valid_sources[0x39]	650	1			T3	4		T4	8		T20	3
valid_sources[0x3a]	693	1			T4	6		T5	1		T20	5
valid_sources[0x3b]	910	1			T3	6		T4	3		T20	1
valid_sources[0x3c]	899	1			T4	19		T20	20		T19	6
valid_sources[0x3d]	812	1			T4	3		T20	19		T19	8
valid_sources[0x3e]	842	1			T3	1		T4	16		T10	1
valid_sources[0x3f]	592	1			T4	3		T34	2		T20	17
valid_sources[0x40]	843	1			T4	5		T9	6		T10	3
valid_sources[0x41]	667	1			T4	7		T10	7		T20	14
valid_sources[0x42]	570	1			T4	19		T5	1		T20	12
valid_sources[0x43]	661	1			T3	1		T4	7		T20	3
valid_sources[0x44]	699	1			T4	2		T20	17		T19	2
valid_sources[0x45]	779	1			T3	3		T4	3		T75	4
valid_sources[0x46]	511	1			T5	1		T20	14		T19	17
valid_sources[0x47]	689	1			T3	5		T4	9		T20	7
valid_sources[0x48]	676	1			T4	10		T5	1		T20	20
valid_sources[0x49]	618	1			T3	2		T4	11		T20	27
valid_sources[0x4a]	646	1			T3	7		T4	2		T5	1
valid_sources[0x4b]	944	1			T3	12		T4	16		T20	10
valid_sources[0x4c]	764	1			T4	15		T20	13		T19	7
valid_sources[0x4d]	758	1			T3	1		T4	7		T5	1
valid_sources[0x4e]	828	1			T4	8		T10	2		T20	7
valid_sources[0x4f]	1171	1			T3	1		T4	11		T5	3
valid_sources[0x50]	612	1			T4	4		T20	29		T137	1
valid_sources[0x51]	887	1			T20	24		T19	3		T38	26
valid_sources[0x52]	745	1			T4	3		T10	1		T20	6
valid_sources[0x53]	836	1			T4	14		T20	19		T19	16
valid_sources[0x54]	814	1			T4	3		T20	1		T19	20
valid_sources[0x55]	616	1			T3	3		T4	19		T20	17
valid_sources[0x56]	803	1			T4	21		T5	1		T20	12
valid_sources[0x57]	773	1			T4	9		T5	2		T6	5
valid_sources[0x58]	566	1			T4	7		T20	17		T19	18
valid_sources[0x59]	997	1			T4	4		T20	16		T19	13
valid_sources[0x5a]	578	1			T3	5		T4	13		T5	2
valid_sources[0x5b]	619	1			T4	8		T20	16		T137	1
valid_sources[0x5c]	582	1			T5	5		T20	17		T19	11
valid_sources[0x5d]	600	1			T4	20		T5	2		T20	23
valid_sources[0x5e]	544	1			T4	7		T35	1		T20	26
valid_sources[0x5f]	606	1			T4	6		T52	1		T37	1
valid_sources[0x60]	662	1			T3	15		T4	19		T5	1
valid_sources[0x61]	765	1			T3	3		T4	13		T10	6
valid_sources[0x62]	761	1			T4	3		T35	2		T5	3
valid_sources[0x63]	778	1			T3	7		T4	4		T20	10
valid_sources[0x64]	645	1			T3	3		T4	3		T5	1
valid_sources[0x65]	591	1			T3	5		T4	10		T34	1
valid_sources[0x66]	797	1			T3	1		T4	10		T10	1
valid_sources[0x67]	803	1			T4	3		T34	1		T5	3
valid_sources[0x68]	804	1			T3	2		T4	6		T10	1
valid_sources[0x69]	784	1			T4	7		T5	2		T36	1
valid_sources[0x6a]	829	1			T3	3		T4	2		T5	1
valid_sources[0x6b]	952	1			T4	10		T52	1		T20	3
valid_sources[0x6c]	849	1			T4	13		T20	30		T19	14
valid_sources[0x6d]	618	1			T4	23		T20	17		T19	2
valid_sources[0x6e]	676	1			T4	2		T20	8		T19	1
valid_sources[0x6f]	795	1			T3	1		T4	22		T5	5
valid_sources[0x70]	627	1			T3	2		T4	5		T20	8
valid_sources[0x71]	946	1			T4	7		T5	1		T53	1
valid_sources[0x72]	852	1			T3	1		T4	3		T20	14
valid_sources[0x73]	539	1			T3	8		T4	9		T5	1
valid_sources[0x74]	688	1			T4	18		T34	1		T5	1
valid_sources[0x75]	628	1			T3	5		T4	7		T34	5
valid_sources[0x76]	565	1			T3	1		T4	5		T10	4
valid_sources[0x77]	835	1			T3	3		T4	13		T5	1
valid_sources[0x78]	620	1			T4	8		T5	2		T20	23
valid_sources[0x79]	584	1			T3	9		T4	5		T5	3
valid_sources[0x7a]	910	1			T3	4		T4	4		T20	17
valid_sources[0x7b]	692	1			T4	7		T20	1		T19	2
valid_sources[0x7c]	618	1			T4	6		T20	13		T19	26
valid_sources[0x7d]	648	1			T3	10		T4	14		T20	9
valid_sources[0x7e]	692	1			T4	4		T5	3		T20	12
valid_sources[0x7f]	596	1			T4	1		T20	18		T19	10
valid_sources[0x80]	786	1			T3	8		T4	19		T20	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41661

1

T3

53

T4

553

T10

10

values[0x0]

all_enables

biggest_size

56303

1

T1

1

T2

1

T3

61

values[0x1]

all_enables

biggest_size

53731

1

T3

31

T4

837

T7

1