Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14202407

1

T1

180343

T3

97746

T4

3236

full_word

56960157

1

T1

40071

T3

973189

T4

14314

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	71162254	1			T1	220414		T3	107093		T4	17550
auto[TlIntgErrCmd]	101	1			T49	5		T50	2		T51	4
auto[TlIntgErrData]	105	1			T49	9		T50	3		T51	3
auto[TlIntgErrBoth]	104	1			T49	6		T50	5		T51	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32331452

1

T1

110079

T3

428608

T4

7319

auto[1]

38831112

1

T1

110335

T3

642327

T4

10231

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6753965	1			T1	90010		T3	38869		T4	1024
auto[TlIntgErrNone]	partial	auto[1]	7448159	1			T1	90333		T3	58877		T4	2212
auto[TlIntgErrNone]	full_word	auto[0]	25577346	1			T1	20069		T3	389739		T4	6295
auto[TlIntgErrNone]	full_word	auto[1]	31382784	1			T1	20002		T3	583450		T4	8019
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T49	2		T121	4		T122	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T49	3		T50	2		T51	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T128	2		T129	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T51	1		T127	1		T125	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T49	3		T50	3		T51	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T49	5		T51	2		T121	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T49	1		T123	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T130	2		T124	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T49	2		T50	2		T51	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T49	4		T50	3		T51	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T132	1		T124	2		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T127	1		T132	1		T124	2