Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	745167	1			T1	4626		T3	12213		T10	2410
auto[1]	10153960	1			T1	14435		T3	8361		T4	177
auto[2]	625941	1			T1	3349		T3	7873		T10	2100
auto[3]	10040809	1			T1	13265		T3	4135		T4	218

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13726196	1			T1	519		T3	25123		T4	330
auto[1]	2082619	1			T1	3663		T3	3056		T4	33
auto[2]	2107057	1			T1	4942		T3	3966		T4	31
auto[3]	3650005	1			T1	26551		T3	437		T4	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8383518

1

T1

4

T3

32559

T4

394

auto[1]

13182359

1

T1

35671

T3

23

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	307682	1			T3	10057		T10	2010		T12	3
auto[0]	auto[0]	auto[1]	31025	1			T3	979		T10	188		T12	16
auto[0]	auto[0]	auto[2]	31221	1			T3	1057		T10	177		T12	16
auto[0]	auto[0]	auto[3]	6990	1			T3	107		T10	34		T12	48
auto[0]	auto[1]	auto[0]	3138907	1			T3	6386		T4	147		T7	3161
auto[0]	auto[1]	auto[1]	337019	1			T3	1181		T4	13		T7	312
auto[0]	auto[1]	auto[2]	319251	1			T3	673		T4	16		T7	314
auto[0]	auto[1]	auto[3]	69431	1			T1	2		T3	119		T4	1
auto[0]	auto[2]	auto[0]	261448	1			T3	6111		T10	1749		T12	5
auto[0]	auto[2]	auto[1]	26522	1			T3	630		T10	161		T12	4
auto[0]	auto[2]	auto[2]	29165	1			T3	1011		T10	172		T12	14
auto[0]	auto[2]	auto[3]	5937	1			T3	115		T10	13		T12	56
auto[0]	auto[3]	auto[0]	3097811	1			T3	2551		T4	182		T7	3165
auto[0]	auto[3]	auto[1]	314307	1			T3	263		T4	20		T7	319
auto[0]	auto[3]	auto[2]	336359	1			T3	1223		T4	15		T7	314
auto[0]	auto[3]	auto[3]	70443	1			T1	2		T3	96		T7	37
auto[1]	auto[0]	auto[0]	12237	1			T1	157		T3	11		T10	1
auto[1]	auto[0]	auto[1]	54825	1			T1	724		T3	2		T73	3
auto[1]	auto[0]	auto[2]	54765	1			T1	688		T73	1		T135	1
auto[1]	auto[0]	auto[3]	246422	1			T1	3057		T52	1		T81	1
auto[1]	auto[1]	auto[0]	3452565	1			T1	241		T3	1		T7	7
auto[1]	auto[1]	auto[1]	655535	1			T1	2334		T3	1		T9	8420
auto[1]	auto[1]	auto[2]	642213	1			T1	1314		T9	8275		T34	2
auto[1]	auto[1]	auto[3]	1539039	1			T1	10544		T7	1		T9	854
auto[1]	auto[2]	auto[0]	8930	1			T3	5		T10	4		T73	14
auto[1]	auto[2]	auto[1]	38195	1			T135	1		T96	3525		T98	1198
auto[1]	auto[2]	auto[2]	46493	1			T1	597		T3	1		T10	1
auto[1]	auto[2]	auto[3]	209251	1			T1	2752		T96	14385		T98	8390
auto[1]	auto[3]	auto[0]	3446616	1			T1	121		T3	1		T4	1
auto[1]	auto[3]	auto[1]	625191	1			T1	605		T9	8185		T34	10
auto[1]	auto[3]	auto[2]	647590	1			T1	2343		T3	1		T9	8235
auto[1]	auto[3]	auto[3]	1502492	1			T1	10194		T9	872		T34	1