Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	347149381	225285	0	0
ctrl_regwen_rd_A	347149381	3300	0	0
exec_rd_A	347149381	3035	0	0
exec_regwen_rd_A	347149381	3221	0	0
readback_rd_A	347149381	1512	0	0
readback_regwen_rd_A	347149381	1444	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347149381	225285	0	0
T4	38254	2771	0	0
T5	422620	0	0	0
T7	39728	0	0	0
T8	35038	0	0	0
T9	283508	0	0	0
T10	216463	0	0	0
T11	1909	0	0	0
T12	9851	0	0	0
T19	0	3515	0	0
T20	0	5006	0	0
T34	319289	0	0	0
T35	342444	0	0	0
T38	0	1660	0	0
T39	0	3798	0	0
T42	0	1558	0	0
T45	0	8606	0	0
T48	0	1486	0	0
T58	0	3701	0	0
T59	0	1428	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347149381	3300	0	0
T40	0	409	0	0
T50	0	47	0	0
T59	23999	70	0	0
T103	0	91	0	0
T104	0	282	0	0
T105	0	154	0	0
T106	0	240	0	0
T107	0	138	0	0
T108	0	166	0	0
T109	0	169	0	0
T110	130230	0	0	0
T111	1104	0	0	0
T112	495825	0	0	0
T113	29708	0	0	0
T114	48362	0	0	0
T115	71396	0	0	0
T116	14644	0	0	0
T117	1902	0	0	0
T118	199085	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347149381	3035	0	0
T40	0	363	0	0
T50	0	27	0	0
T59	23999	55	0	0
T103	0	54	0	0
T104	0	238	0	0
T105	0	92	0	0
T106	0	214	0	0
T107	0	110	0	0
T108	0	90	0	0
T109	0	165	0	0
T110	130230	0	0	0
T111	1104	0	0	0
T112	495825	0	0	0
T113	29708	0	0	0
T114	48362	0	0	0
T115	71396	0	0	0
T116	14644	0	0	0
T117	1902	0	0	0
T118	199085	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347149381	3221	0	0
T40	0	376	0	0
T50	0	46	0	0
T59	23999	43	0	0
T103	0	61	0	0
T104	0	223	0	0
T105	0	163	0	0
T106	0	287	0	0
T107	0	89	0	0
T108	0	139	0	0
T109	0	229	0	0
T110	130230	0	0	0
T111	1104	0	0	0
T112	495825	0	0	0
T113	29708	0	0	0
T114	48362	0	0	0
T115	71396	0	0	0
T116	14644	0	0	0
T117	1902	0	0	0
T118	199085	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347149381	1512	0	0
T40	0	343	0	0
T59	23999	50	0	0
T103	0	75	0	0
T104	0	193	0	0
T105	0	151	0	0
T106	0	178	0	0
T107	0	93	0	0
T108	0	130	0	0
T109	0	130	0	0
T110	130230	0	0	0
T111	1104	0	0	0
T112	495825	0	0	0
T113	29708	0	0	0
T114	48362	0	0	0
T115	71396	0	0	0
T116	14644	0	0	0
T117	1902	0	0	0
T118	199085	0	0	0
T119	0	13	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347149381	1444	0	0
T40	0	239	0	0
T59	23999	16	0	0
T103	0	46	0	0
T104	0	220	0	0
T105	0	147	0	0
T106	0	211	0	0
T107	0	97	0	0
T108	0	97	0	0
T109	0	141	0	0
T110	130230	0	0	0
T111	1104	0	0	0
T112	495825	0	0	0
T113	29708	0	0	0
T114	48362	0	0	0
T115	71396	0	0	0
T116	14644	0	0	0
T117	1902	0	0	0
T118	199085	0	0	0
T119	0	68	0	0