| T800 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1269450407 |
|
|
Jul 23 06:35:13 PM PDT 24 |
Jul 23 06:42:50 PM PDT 24 |
11044993877 ps |
| T801 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2871814761 |
|
|
Jul 23 06:33:24 PM PDT 24 |
Jul 23 06:47:01 PM PDT 24 |
22791164200 ps |
| T802 |
/workspace/coverage/default/20.sram_ctrl_executable.2719776085 |
|
|
Jul 23 06:32:44 PM PDT 24 |
Jul 23 06:44:26 PM PDT 24 |
5482456553 ps |
| T803 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.701108004 |
|
|
Jul 23 06:32:03 PM PDT 24 |
Jul 23 06:49:34 PM PDT 24 |
2876066620 ps |
| T804 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.969404404 |
|
|
Jul 23 06:33:17 PM PDT 24 |
Jul 23 06:33:24 PM PDT 24 |
651697439 ps |
| T805 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3904478980 |
|
|
Jul 23 06:32:14 PM PDT 24 |
Jul 23 06:34:34 PM PDT 24 |
433241848 ps |
| T806 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3767602146 |
|
|
Jul 23 06:33:23 PM PDT 24 |
Jul 23 06:37:36 PM PDT 24 |
3460098183 ps |
| T807 |
/workspace/coverage/default/32.sram_ctrl_executable.3853271981 |
|
|
Jul 23 06:33:44 PM PDT 24 |
Jul 23 06:47:40 PM PDT 24 |
8019483623 ps |
| T808 |
/workspace/coverage/default/10.sram_ctrl_executable.980277864 |
|
|
Jul 23 06:32:07 PM PDT 24 |
Jul 23 06:58:22 PM PDT 24 |
15390883843 ps |
| T809 |
/workspace/coverage/default/6.sram_ctrl_bijection.1898933335 |
|
|
Jul 23 06:31:50 PM PDT 24 |
Jul 23 06:33:03 PM PDT 24 |
6069929392 ps |
| T810 |
/workspace/coverage/default/29.sram_ctrl_regwen.2546188923 |
|
|
Jul 23 06:33:23 PM PDT 24 |
Jul 23 06:40:54 PM PDT 24 |
8853214327 ps |
| T811 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1261634269 |
|
|
Jul 23 06:34:01 PM PDT 24 |
Jul 23 06:34:08 PM PDT 24 |
193160403 ps |
| T812 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2294514142 |
|
|
Jul 23 06:35:55 PM PDT 24 |
Jul 23 06:38:39 PM PDT 24 |
3729866618 ps |
| T813 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.486431050 |
|
|
Jul 23 06:36:05 PM PDT 24 |
Jul 23 06:42:32 PM PDT 24 |
1468765745 ps |
| T814 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.107728523 |
|
|
Jul 23 06:33:38 PM PDT 24 |
Jul 23 06:33:42 PM PDT 24 |
2142125344 ps |
| T815 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.233583617 |
|
|
Jul 23 06:33:23 PM PDT 24 |
Jul 23 06:33:30 PM PDT 24 |
728681138 ps |
| T107 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1173470269 |
|
|
Jul 23 06:33:20 PM PDT 24 |
Jul 23 06:33:31 PM PDT 24 |
1111660896 ps |
| T816 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2859954967 |
|
|
Jul 23 06:33:16 PM PDT 24 |
Jul 23 06:33:41 PM PDT 24 |
317696022 ps |
| T817 |
/workspace/coverage/default/22.sram_ctrl_bijection.1708521040 |
|
|
Jul 23 06:32:44 PM PDT 24 |
Jul 23 06:34:00 PM PDT 24 |
28950727194 ps |
| T818 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3640167198 |
|
|
Jul 23 06:31:57 PM PDT 24 |
Jul 23 06:32:09 PM PDT 24 |
135208733 ps |
| T819 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.4257054633 |
|
|
Jul 23 06:34:27 PM PDT 24 |
Jul 23 06:34:30 PM PDT 24 |
27239378 ps |
| T820 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2615579248 |
|
|
Jul 23 06:32:14 PM PDT 24 |
Jul 23 07:10:30 PM PDT 24 |
37826119852 ps |
| T821 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.902049391 |
|
|
Jul 23 06:31:59 PM PDT 24 |
Jul 23 06:43:36 PM PDT 24 |
13188273634 ps |
| T822 |
/workspace/coverage/default/44.sram_ctrl_alert_test.915819189 |
|
|
Jul 23 06:35:16 PM PDT 24 |
Jul 23 06:35:18 PM PDT 24 |
31589880 ps |
| T823 |
/workspace/coverage/default/27.sram_ctrl_executable.2223922210 |
|
|
Jul 23 06:33:17 PM PDT 24 |
Jul 23 06:54:41 PM PDT 24 |
15682065682 ps |
| T824 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2671051211 |
|
|
Jul 23 06:32:17 PM PDT 24 |
Jul 23 06:32:30 PM PDT 24 |
188465482 ps |
| T825 |
/workspace/coverage/default/14.sram_ctrl_smoke.515751991 |
|
|
Jul 23 06:32:18 PM PDT 24 |
Jul 23 06:32:33 PM PDT 24 |
99576854 ps |
| T108 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3513479181 |
|
|
Jul 23 06:32:28 PM PDT 24 |
Jul 23 06:33:27 PM PDT 24 |
676959013 ps |
| T826 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2741631404 |
|
|
Jul 23 06:31:52 PM PDT 24 |
Jul 23 06:32:10 PM PDT 24 |
715509101 ps |
| T827 |
/workspace/coverage/default/6.sram_ctrl_smoke.745061931 |
|
|
Jul 23 06:31:54 PM PDT 24 |
Jul 23 06:32:27 PM PDT 24 |
1043896866 ps |
| T828 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.435001180 |
|
|
Jul 23 06:32:44 PM PDT 24 |
Jul 23 06:32:57 PM PDT 24 |
452435196 ps |
| T829 |
/workspace/coverage/default/43.sram_ctrl_stress_all.2180629632 |
|
|
Jul 23 06:35:05 PM PDT 24 |
Jul 23 07:01:43 PM PDT 24 |
22684218512 ps |
| T830 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.2965197383 |
|
|
Jul 23 06:33:22 PM PDT 24 |
Jul 23 06:33:29 PM PDT 24 |
1061437392 ps |
| T831 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.4107729021 |
|
|
Jul 23 06:34:38 PM PDT 24 |
Jul 23 06:37:41 PM PDT 24 |
1953701578 ps |
| T832 |
/workspace/coverage/default/2.sram_ctrl_alert_test.3144057362 |
|
|
Jul 23 06:31:46 PM PDT 24 |
Jul 23 06:31:57 PM PDT 24 |
51434711 ps |
| T833 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2172339422 |
|
|
Jul 23 06:31:41 PM PDT 24 |
Jul 23 06:31:53 PM PDT 24 |
27733154 ps |
| T834 |
/workspace/coverage/default/36.sram_ctrl_bijection.1774672847 |
|
|
Jul 23 06:34:13 PM PDT 24 |
Jul 23 06:34:48 PM PDT 24 |
6836730802 ps |
| T835 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.767943135 |
|
|
Jul 23 06:31:36 PM PDT 24 |
Jul 23 06:38:43 PM PDT 24 |
16206946500 ps |
| T836 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1625651792 |
|
|
Jul 23 06:32:34 PM PDT 24 |
Jul 23 06:33:22 PM PDT 24 |
1210063673 ps |
| T837 |
/workspace/coverage/default/31.sram_ctrl_bijection.2394325715 |
|
|
Jul 23 06:33:35 PM PDT 24 |
Jul 23 06:33:58 PM PDT 24 |
1416429161 ps |
| T838 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.2263084197 |
|
|
Jul 23 06:31:41 PM PDT 24 |
Jul 23 06:34:10 PM PDT 24 |
542400187 ps |
| T839 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1101169079 |
|
|
Jul 23 06:31:43 PM PDT 24 |
Jul 23 06:31:59 PM PDT 24 |
236342098 ps |
| T840 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.2744968586 |
|
|
Jul 23 06:32:10 PM PDT 24 |
Jul 23 06:32:49 PM PDT 24 |
80430654 ps |
| T841 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3505035526 |
|
|
Jul 23 06:31:54 PM PDT 24 |
Jul 23 06:33:31 PM PDT 24 |
627718744 ps |
| T842 |
/workspace/coverage/default/43.sram_ctrl_partial_access.493042743 |
|
|
Jul 23 06:35:05 PM PDT 24 |
Jul 23 06:35:14 PM PDT 24 |
288525687 ps |
| T843 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1655029926 |
|
|
Jul 23 06:32:30 PM PDT 24 |
Jul 23 06:32:42 PM PDT 24 |
449977970 ps |
| T844 |
/workspace/coverage/default/42.sram_ctrl_regwen.675989404 |
|
|
Jul 23 06:34:58 PM PDT 24 |
Jul 23 06:51:00 PM PDT 24 |
124928960498 ps |
| T845 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4133827055 |
|
|
Jul 23 06:33:52 PM PDT 24 |
Jul 23 06:38:37 PM PDT 24 |
5956128565 ps |
| T846 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1235946263 |
|
|
Jul 23 06:34:14 PM PDT 24 |
Jul 23 07:46:25 PM PDT 24 |
484911613782 ps |
| T847 |
/workspace/coverage/default/18.sram_ctrl_regwen.1888259678 |
|
|
Jul 23 06:32:31 PM PDT 24 |
Jul 23 06:40:27 PM PDT 24 |
20385465094 ps |
| T848 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.626361970 |
|
|
Jul 23 06:34:49 PM PDT 24 |
Jul 23 06:50:13 PM PDT 24 |
36973916677 ps |
| T849 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1019603756 |
|
|
Jul 23 06:33:13 PM PDT 24 |
Jul 23 06:38:07 PM PDT 24 |
22587533679 ps |
| T850 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3466704253 |
|
|
Jul 23 06:32:23 PM PDT 24 |
Jul 23 06:32:44 PM PDT 24 |
406914618 ps |
| T851 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.806757826 |
|
|
Jul 23 06:33:06 PM PDT 24 |
Jul 23 06:33:18 PM PDT 24 |
930494567 ps |
| T852 |
/workspace/coverage/default/30.sram_ctrl_regwen.2733061948 |
|
|
Jul 23 06:33:29 PM PDT 24 |
Jul 23 06:47:38 PM PDT 24 |
41992767178 ps |
| T853 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.1961569648 |
|
|
Jul 23 06:32:42 PM PDT 24 |
Jul 23 06:35:47 PM PDT 24 |
1952121967 ps |
| T854 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.4264266413 |
|
|
Jul 23 06:33:16 PM PDT 24 |
Jul 23 06:33:25 PM PDT 24 |
147136713 ps |
| T855 |
/workspace/coverage/default/37.sram_ctrl_partial_access.1630539986 |
|
|
Jul 23 06:34:19 PM PDT 24 |
Jul 23 06:34:39 PM PDT 24 |
4269904782 ps |
| T856 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.478453090 |
|
|
Jul 23 06:34:12 PM PDT 24 |
Jul 23 06:34:26 PM PDT 24 |
276117415 ps |
| T857 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.4240629845 |
|
|
Jul 23 06:32:27 PM PDT 24 |
Jul 23 06:36:06 PM PDT 24 |
8253030188 ps |
| T858 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1210226393 |
|
|
Jul 23 06:32:42 PM PDT 24 |
Jul 23 06:40:09 PM PDT 24 |
27298650087 ps |
| T859 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3976755673 |
|
|
Jul 23 06:35:52 PM PDT 24 |
Jul 23 06:36:00 PM PDT 24 |
726818438 ps |
| T860 |
/workspace/coverage/default/24.sram_ctrl_bijection.536169181 |
|
|
Jul 23 06:32:55 PM PDT 24 |
Jul 23 06:33:52 PM PDT 24 |
934485849 ps |
| T861 |
/workspace/coverage/default/21.sram_ctrl_regwen.1686736157 |
|
|
Jul 23 06:32:48 PM PDT 24 |
Jul 23 06:44:24 PM PDT 24 |
10320321956 ps |
| T862 |
/workspace/coverage/default/44.sram_ctrl_bijection.816244796 |
|
|
Jul 23 06:35:10 PM PDT 24 |
Jul 23 06:36:14 PM PDT 24 |
7524722653 ps |
| T863 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.3044956000 |
|
|
Jul 23 06:31:48 PM PDT 24 |
Jul 23 06:32:11 PM PDT 24 |
1342177899 ps |
| T864 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3348070065 |
|
|
Jul 23 06:34:21 PM PDT 24 |
Jul 23 06:34:29 PM PDT 24 |
633971552 ps |
| T865 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1530955586 |
|
|
Jul 23 06:34:25 PM PDT 24 |
Jul 23 06:34:30 PM PDT 24 |
264130329 ps |
| T866 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.2599746237 |
|
|
Jul 23 06:32:03 PM PDT 24 |
Jul 23 06:32:21 PM PDT 24 |
890919027 ps |
| T867 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2872971185 |
|
|
Jul 23 06:31:47 PM PDT 24 |
Jul 23 06:35:49 PM PDT 24 |
3663925791 ps |
| T868 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1235915358 |
|
|
Jul 23 06:36:01 PM PDT 24 |
Jul 23 06:38:20 PM PDT 24 |
324769220 ps |
| T869 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2294077545 |
|
|
Jul 23 06:32:38 PM PDT 24 |
Jul 23 06:32:44 PM PDT 24 |
664031683 ps |
| T870 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.897429304 |
|
|
Jul 23 06:31:57 PM PDT 24 |
Jul 23 06:33:08 PM PDT 24 |
702358176 ps |
| T871 |
/workspace/coverage/default/45.sram_ctrl_bijection.2901916487 |
|
|
Jul 23 06:35:15 PM PDT 24 |
Jul 23 06:36:28 PM PDT 24 |
1297879742 ps |
| T872 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2943904100 |
|
|
Jul 23 06:32:54 PM PDT 24 |
Jul 23 06:33:06 PM PDT 24 |
278669087 ps |
| T873 |
/workspace/coverage/default/29.sram_ctrl_executable.3696449044 |
|
|
Jul 23 06:33:26 PM PDT 24 |
Jul 23 06:56:13 PM PDT 24 |
7917242932 ps |
| T874 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2468261215 |
|
|
Jul 23 06:31:41 PM PDT 24 |
Jul 23 06:33:43 PM PDT 24 |
1109409845 ps |
| T875 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.681197129 |
|
|
Jul 23 06:31:41 PM PDT 24 |
Jul 23 07:10:09 PM PDT 24 |
68329444819 ps |
| T876 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.3674948518 |
|
|
Jul 23 06:32:20 PM PDT 24 |
Jul 23 06:42:35 PM PDT 24 |
2011690385 ps |
| T877 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.2850196580 |
|
|
Jul 23 06:35:05 PM PDT 24 |
Jul 23 06:35:09 PM PDT 24 |
174261258 ps |
| T878 |
/workspace/coverage/default/23.sram_ctrl_executable.3389136959 |
|
|
Jul 23 06:32:51 PM PDT 24 |
Jul 23 06:43:47 PM PDT 24 |
2334668286 ps |
| T879 |
/workspace/coverage/default/25.sram_ctrl_executable.4168109149 |
|
|
Jul 23 06:33:07 PM PDT 24 |
Jul 23 06:55:00 PM PDT 24 |
71288125319 ps |
| T880 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1370268072 |
|
|
Jul 23 06:32:16 PM PDT 24 |
Jul 23 06:32:33 PM PDT 24 |
2079182064 ps |
| T881 |
/workspace/coverage/default/27.sram_ctrl_alert_test.4054937227 |
|
|
Jul 23 06:33:25 PM PDT 24 |
Jul 23 06:33:27 PM PDT 24 |
14065972 ps |
| T882 |
/workspace/coverage/default/49.sram_ctrl_alert_test.3949598006 |
|
|
Jul 23 06:36:06 PM PDT 24 |
Jul 23 06:36:07 PM PDT 24 |
11989090 ps |
| T883 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2400262983 |
|
|
Jul 23 06:34:49 PM PDT 24 |
Jul 23 06:34:58 PM PDT 24 |
215768941 ps |
| T884 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.1120881977 |
|
|
Jul 23 06:32:31 PM PDT 24 |
Jul 23 06:34:33 PM PDT 24 |
487701438 ps |
| T885 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1407481517 |
|
|
Jul 23 06:34:58 PM PDT 24 |
Jul 23 06:38:11 PM PDT 24 |
4674699962 ps |
| T886 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.3071956798 |
|
|
Jul 23 06:34:27 PM PDT 24 |
Jul 23 06:52:19 PM PDT 24 |
4288411741 ps |
| T887 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3190323336 |
|
|
Jul 23 06:31:46 PM PDT 24 |
Jul 23 06:32:04 PM PDT 24 |
732462471 ps |
| T888 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2329258214 |
|
|
Jul 23 06:35:31 PM PDT 24 |
Jul 23 06:35:33 PM PDT 24 |
28642013 ps |
| T889 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.1373950459 |
|
|
Jul 23 06:33:05 PM PDT 24 |
Jul 23 06:33:07 PM PDT 24 |
28631100 ps |
| T890 |
/workspace/coverage/default/44.sram_ctrl_executable.2728155357 |
|
|
Jul 23 06:35:12 PM PDT 24 |
Jul 23 06:56:16 PM PDT 24 |
55861235830 ps |
| T891 |
/workspace/coverage/default/40.sram_ctrl_alert_test.3110198537 |
|
|
Jul 23 06:34:49 PM PDT 24 |
Jul 23 06:34:52 PM PDT 24 |
17542184 ps |
| T892 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2402920408 |
|
|
Jul 23 06:32:54 PM PDT 24 |
Jul 23 06:32:58 PM PDT 24 |
472971282 ps |
| T893 |
/workspace/coverage/default/35.sram_ctrl_bijection.1423005513 |
|
|
Jul 23 06:34:01 PM PDT 24 |
Jul 23 06:34:23 PM PDT 24 |
3800900272 ps |
| T894 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2157190262 |
|
|
Jul 23 06:33:45 PM PDT 24 |
Jul 23 06:39:15 PM PDT 24 |
3218325036 ps |
| T895 |
/workspace/coverage/default/12.sram_ctrl_smoke.2338766004 |
|
|
Jul 23 06:32:09 PM PDT 24 |
Jul 23 06:32:27 PM PDT 24 |
288454341 ps |
| T896 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.951515482 |
|
|
Jul 23 06:34:12 PM PDT 24 |
Jul 23 06:44:52 PM PDT 24 |
33258997164 ps |
| T897 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.4224661639 |
|
|
Jul 23 06:34:55 PM PDT 24 |
Jul 23 06:35:00 PM PDT 24 |
1875398057 ps |
| T898 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3316006186 |
|
|
Jul 23 06:33:21 PM PDT 24 |
Jul 23 06:33:42 PM PDT 24 |
104726764 ps |
| T899 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2912017843 |
|
|
Jul 23 06:32:47 PM PDT 24 |
Jul 23 06:34:54 PM PDT 24 |
139539540 ps |
| T900 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2465230264 |
|
|
Jul 23 06:36:01 PM PDT 24 |
Jul 23 06:36:04 PM PDT 24 |
65773654 ps |
| T901 |
/workspace/coverage/default/38.sram_ctrl_bijection.3183589078 |
|
|
Jul 23 06:34:22 PM PDT 24 |
Jul 23 06:35:04 PM PDT 24 |
1822163906 ps |
| T902 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.127886673 |
|
|
Jul 23 06:31:59 PM PDT 24 |
Jul 23 06:32:07 PM PDT 24 |
85662680 ps |
| T903 |
/workspace/coverage/default/18.sram_ctrl_smoke.1145805343 |
|
|
Jul 23 06:32:23 PM PDT 24 |
Jul 23 06:32:45 PM PDT 24 |
828505003 ps |
| T904 |
/workspace/coverage/default/23.sram_ctrl_stress_all.3246295837 |
|
|
Jul 23 06:32:49 PM PDT 24 |
Jul 23 07:15:00 PM PDT 24 |
39681857881 ps |
| T905 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1930784345 |
|
|
Jul 23 06:35:54 PM PDT 24 |
Jul 23 06:35:56 PM PDT 24 |
51772881 ps |
| T906 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.4130984925 |
|
|
Jul 23 06:32:02 PM PDT 24 |
Jul 23 06:32:13 PM PDT 24 |
75750279 ps |
| T907 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.1992119914 |
|
|
Jul 23 06:33:17 PM PDT 24 |
Jul 23 06:33:30 PM PDT 24 |
1123905137 ps |
| T908 |
/workspace/coverage/default/27.sram_ctrl_stress_all.3501844870 |
|
|
Jul 23 06:33:17 PM PDT 24 |
Jul 23 06:44:13 PM PDT 24 |
43348595898 ps |
| T909 |
/workspace/coverage/default/47.sram_ctrl_regwen.2157446658 |
|
|
Jul 23 06:35:46 PM PDT 24 |
Jul 23 06:53:16 PM PDT 24 |
53134141187 ps |
| T910 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.4248260072 |
|
|
Jul 23 06:33:34 PM PDT 24 |
Jul 23 06:33:37 PM PDT 24 |
189784594 ps |
| T911 |
/workspace/coverage/default/16.sram_ctrl_bijection.331946526 |
|
|
Jul 23 06:32:24 PM PDT 24 |
Jul 23 06:33:27 PM PDT 24 |
4698683055 ps |
| T912 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2500622954 |
|
|
Jul 23 06:34:53 PM PDT 24 |
Jul 23 06:52:49 PM PDT 24 |
85297365646 ps |
| T913 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.799641948 |
|
|
Jul 23 06:31:46 PM PDT 24 |
Jul 23 06:32:07 PM PDT 24 |
453793891 ps |
| T914 |
/workspace/coverage/default/34.sram_ctrl_regwen.2242337576 |
|
|
Jul 23 06:33:55 PM PDT 24 |
Jul 23 06:42:49 PM PDT 24 |
31797285942 ps |
| T915 |
/workspace/coverage/default/22.sram_ctrl_smoke.626359243 |
|
|
Jul 23 06:32:48 PM PDT 24 |
Jul 23 06:32:58 PM PDT 24 |
329580284 ps |
| T916 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.2816004541 |
|
|
Jul 23 06:31:50 PM PDT 24 |
Jul 23 06:32:01 PM PDT 24 |
26179127 ps |
| T23 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.1740843715 |
|
|
Jul 23 06:31:44 PM PDT 24 |
Jul 23 06:31:58 PM PDT 24 |
449931826 ps |
| T917 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.676591918 |
|
|
Jul 23 06:35:49 PM PDT 24 |
Jul 23 06:35:58 PM PDT 24 |
647339501 ps |
| T918 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3478662940 |
|
|
Jul 23 06:32:16 PM PDT 24 |
Jul 23 06:32:28 PM PDT 24 |
47174308 ps |
| T919 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.3332056101 |
|
|
Jul 23 06:33:40 PM PDT 24 |
Jul 23 06:33:49 PM PDT 24 |
1715560247 ps |
| T920 |
/workspace/coverage/default/0.sram_ctrl_smoke.4054955514 |
|
|
Jul 23 06:31:35 PM PDT 24 |
Jul 23 06:31:52 PM PDT 24 |
152724051 ps |
| T921 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3449803820 |
|
|
Jul 23 06:33:11 PM PDT 24 |
Jul 23 06:33:18 PM PDT 24 |
190129812 ps |
| T922 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.290860182 |
|
|
Jul 23 06:33:13 PM PDT 24 |
Jul 23 06:37:24 PM PDT 24 |
16497925505 ps |
| T923 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1466048438 |
|
|
Jul 23 06:31:46 PM PDT 24 |
Jul 23 06:31:59 PM PDT 24 |
91851085 ps |
| T924 |
/workspace/coverage/default/49.sram_ctrl_regwen.2760072099 |
|
|
Jul 23 06:36:04 PM PDT 24 |
Jul 23 06:43:31 PM PDT 24 |
15429102082 ps |
| T925 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.4191642547 |
|
|
Jul 23 06:31:56 PM PDT 24 |
Jul 23 06:32:07 PM PDT 24 |
104176090 ps |
| T926 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4233690217 |
|
|
Jul 23 06:31:45 PM PDT 24 |
Jul 23 06:37:13 PM PDT 24 |
4288764740 ps |
| T109 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1903041724 |
|
|
Jul 23 06:32:31 PM PDT 24 |
Jul 23 06:33:09 PM PDT 24 |
3036087841 ps |
| T927 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1222842834 |
|
|
Jul 23 06:33:52 PM PDT 24 |
Jul 23 06:52:12 PM PDT 24 |
16759765888 ps |
| T928 |
/workspace/coverage/default/47.sram_ctrl_alert_test.658246343 |
|
|
Jul 23 06:35:46 PM PDT 24 |
Jul 23 06:35:49 PM PDT 24 |
49823148 ps |
| T929 |
/workspace/coverage/default/8.sram_ctrl_regwen.3229021154 |
|
|
Jul 23 06:31:57 PM PDT 24 |
Jul 23 06:37:02 PM PDT 24 |
1159792048 ps |
| T930 |
/workspace/coverage/default/20.sram_ctrl_bijection.889230739 |
|
|
Jul 23 06:32:36 PM PDT 24 |
Jul 23 06:33:26 PM PDT 24 |
4841119643 ps |
| T931 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3061953358 |
|
|
Jul 23 06:32:08 PM PDT 24 |
Jul 23 06:32:39 PM PDT 24 |
822279948 ps |
| T24 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.2381694060 |
|
|
Jul 23 06:31:52 PM PDT 24 |
Jul 23 06:32:04 PM PDT 24 |
381532773 ps |
| T932 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.507418610 |
|
|
Jul 23 06:35:28 PM PDT 24 |
Jul 23 06:50:54 PM PDT 24 |
36654836121 ps |
| T933 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1804547663 |
|
|
Jul 23 06:34:36 PM PDT 24 |
Jul 23 06:34:38 PM PDT 24 |
17424564 ps |
| T934 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.3234194065 |
|
|
Jul 23 06:32:56 PM PDT 24 |
Jul 23 06:36:36 PM PDT 24 |
3403816979 ps |
| T935 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1734356748 |
|
|
Jul 23 06:32:09 PM PDT 24 |
Jul 23 06:38:12 PM PDT 24 |
7347972954 ps |
| T936 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3666803059 |
|
|
Jul 23 06:31:44 PM PDT 24 |
Jul 23 06:34:30 PM PDT 24 |
3158520282 ps |
| T937 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1345033000 |
|
|
Jul 23 06:31:54 PM PDT 24 |
Jul 23 06:32:07 PM PDT 24 |
253628280 ps |
| T938 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3359452448 |
|
|
Jul 23 06:32:33 PM PDT 24 |
Jul 23 06:40:21 PM PDT 24 |
9821657517 ps |
| T939 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1823778767 |
|
|
Jul 23 06:34:30 PM PDT 24 |
Jul 23 06:39:09 PM PDT 24 |
35617078945 ps |
| T940 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2098545140 |
|
|
Jul 23 06:31:45 PM PDT 24 |
Jul 23 06:34:28 PM PDT 24 |
1617829449 ps |
| T941 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2765712404 |
|
|
Jul 23 06:34:14 PM PDT 24 |
Jul 23 06:47:29 PM PDT 24 |
13517177932 ps |
| T942 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4032186387 |
|
|
Jul 23 05:58:22 PM PDT 24 |
Jul 23 05:58:24 PM PDT 24 |
28270877 ps |
| T54 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4182232100 |
|
|
Jul 23 05:58:05 PM PDT 24 |
Jul 23 05:58:07 PM PDT 24 |
21852050 ps |
| T49 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3297579474 |
|
|
Jul 23 05:58:40 PM PDT 24 |
Jul 23 05:58:43 PM PDT 24 |
148046075 ps |
| T55 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2138187854 |
|
|
Jul 23 05:58:38 PM PDT 24 |
Jul 23 05:58:40 PM PDT 24 |
68220031 ps |
| T943 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.572120788 |
|
|
Jul 23 05:58:36 PM PDT 24 |
Jul 23 05:58:39 PM PDT 24 |
43654652 ps |
| T50 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.290206652 |
|
|
Jul 23 05:58:03 PM PDT 24 |
Jul 23 05:58:05 PM PDT 24 |
101926675 ps |
| T91 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3345451913 |
|
|
Jul 23 05:58:35 PM PDT 24 |
Jul 23 05:58:37 PM PDT 24 |
42672127 ps |
| T944 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3179764241 |
|
|
Jul 23 05:58:43 PM PDT 24 |
Jul 23 05:58:47 PM PDT 24 |
83464246 ps |
| T51 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1556099553 |
|
|
Jul 23 05:58:17 PM PDT 24 |
Jul 23 05:58:19 PM PDT 24 |
1040336066 ps |
| T101 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.960012739 |
|
|
Jul 23 05:58:21 PM PDT 24 |
Jul 23 05:58:22 PM PDT 24 |
67884900 ps |
| T121 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1861586317 |
|
|
Jul 23 05:58:36 PM PDT 24 |
Jul 23 05:58:39 PM PDT 24 |
250552604 ps |
| T945 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1652368528 |
|
|
Jul 23 05:58:48 PM PDT 24 |
Jul 23 05:58:50 PM PDT 24 |
38276153 ps |
| T63 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2406652067 |
|
|
Jul 23 05:58:12 PM PDT 24 |
Jul 23 05:58:16 PM PDT 24 |
418467093 ps |
| T64 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2701637453 |
|
|
Jul 23 05:58:25 PM PDT 24 |
Jul 23 05:58:29 PM PDT 24 |
836626680 ps |
| T102 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4156235938 |
|
|
Jul 23 05:58:27 PM PDT 24 |
Jul 23 05:58:28 PM PDT 24 |
13196232 ps |
| T946 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.920273451 |
|
|
Jul 23 05:58:17 PM PDT 24 |
Jul 23 05:58:20 PM PDT 24 |
59781613 ps |
| T65 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1296173053 |
|
|
Jul 23 05:58:20 PM PDT 24 |
Jul 23 05:58:23 PM PDT 24 |
379189118 ps |
| T92 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1211872072 |
|
|
Jul 23 05:58:34 PM PDT 24 |
Jul 23 05:58:35 PM PDT 24 |
116901575 ps |
| T66 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4021570497 |
|
|
Jul 23 05:58:40 PM PDT 24 |
Jul 23 05:58:43 PM PDT 24 |
350853277 ps |
| T947 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1352575165 |
|
|
Jul 23 05:58:50 PM PDT 24 |
Jul 23 05:58:54 PM PDT 24 |
116690006 ps |
| T119 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.757512598 |
|
|
Jul 23 05:58:11 PM PDT 24 |
Jul 23 05:58:16 PM PDT 24 |
221418043 ps |
| T948 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1745279195 |
|
|
Jul 23 05:58:50 PM PDT 24 |
Jul 23 05:58:53 PM PDT 24 |
58694136 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2911943420 |
|
|
Jul 23 05:58:18 PM PDT 24 |
Jul 23 05:58:20 PM PDT 24 |
58259838 ps |
| T122 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.110815301 |
|
|
Jul 23 05:58:18 PM PDT 24 |
Jul 23 05:58:20 PM PDT 24 |
608612646 ps |
| T123 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3924273003 |
|
|
Jul 23 05:58:44 PM PDT 24 |
Jul 23 05:58:47 PM PDT 24 |
495860901 ps |
| T950 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4013404969 |
|
|
Jul 23 05:58:16 PM PDT 24 |
Jul 23 05:58:19 PM PDT 24 |
32520499 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1510323167 |
|
|
Jul 23 05:58:07 PM PDT 24 |
Jul 23 05:58:11 PM PDT 24 |
36858187 ps |
| T952 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4004321302 |
|
|
Jul 23 05:58:28 PM PDT 24 |
Jul 23 05:58:30 PM PDT 24 |
227534892 ps |
| T953 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2732227902 |
|
|
Jul 23 05:58:20 PM PDT 24 |
Jul 23 05:58:26 PM PDT 24 |
129170538 ps |
| T67 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3510096156 |
|
|
Jul 23 05:58:10 PM PDT 24 |
Jul 23 05:58:12 PM PDT 24 |
42336197 ps |
| T68 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.38388654 |
|
|
Jul 23 05:58:11 PM PDT 24 |
Jul 23 05:58:14 PM PDT 24 |
79464080 ps |
| T93 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3868675484 |
|
|
Jul 23 05:58:34 PM PDT 24 |
Jul 23 05:58:36 PM PDT 24 |
134430690 ps |
| T69 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.268817722 |
|
|
Jul 23 05:58:45 PM PDT 24 |
Jul 23 05:58:46 PM PDT 24 |
34637895 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1353025043 |
|
|
Jul 23 05:58:35 PM PDT 24 |
Jul 23 05:58:37 PM PDT 24 |
32660038 ps |
| T955 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3727550505 |
|
|
Jul 23 05:58:43 PM PDT 24 |
Jul 23 05:58:44 PM PDT 24 |
17827600 ps |
| T70 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3704071593 |
|
|
Jul 23 05:58:28 PM PDT 24 |
Jul 23 05:58:30 PM PDT 24 |
11508333 ps |
| T71 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3700742292 |
|
|
Jul 23 05:58:41 PM PDT 24 |
Jul 23 05:58:43 PM PDT 24 |
30336611 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2635758137 |
|
|
Jul 23 05:58:03 PM PDT 24 |
Jul 23 05:58:04 PM PDT 24 |
53975575 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.640228922 |
|
|
Jul 23 05:58:10 PM PDT 24 |
Jul 23 05:58:12 PM PDT 24 |
12122837 ps |
| T957 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3599670316 |
|
|
Jul 23 05:58:08 PM PDT 24 |
Jul 23 05:58:10 PM PDT 24 |
38107267 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2377644913 |
|
|
Jul 23 05:58:24 PM PDT 24 |
Jul 23 05:58:26 PM PDT 24 |
50583695 ps |
| T127 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1143149296 |
|
|
Jul 23 05:58:41 PM PDT 24 |
Jul 23 05:58:45 PM PDT 24 |
277310035 ps |
| T76 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.633968031 |
|
|
Jul 23 05:58:38 PM PDT 24 |
Jul 23 05:58:42 PM PDT 24 |
1560721252 ps |
| T959 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4085477587 |
|
|
Jul 23 05:58:40 PM PDT 24 |
Jul 23 05:58:41 PM PDT 24 |
50225421 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3232886935 |
|
|
Jul 23 05:58:06 PM PDT 24 |
Jul 23 05:58:09 PM PDT 24 |
140608409 ps |
| T130 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3284189509 |
|
|
Jul 23 05:58:23 PM PDT 24 |
Jul 23 05:58:26 PM PDT 24 |
234655881 ps |
| T960 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4215626288 |
|
|
Jul 23 05:58:07 PM PDT 24 |
Jul 23 05:58:08 PM PDT 24 |
35427745 ps |
| T961 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3281022268 |
|
|
Jul 23 05:58:41 PM PDT 24 |
Jul 23 05:58:44 PM PDT 24 |
336611758 ps |
| T962 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2098586443 |
|
|
Jul 23 05:58:26 PM PDT 24 |
Jul 23 05:58:28 PM PDT 24 |
52932272 ps |
| T77 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.207954201 |
|
|
Jul 23 05:58:05 PM PDT 24 |
Jul 23 05:58:08 PM PDT 24 |
868528708 ps |
| T963 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1484043587 |
|
|
Jul 23 05:58:02 PM PDT 24 |
Jul 23 05:58:07 PM PDT 24 |
85415746 ps |
| T78 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.141847467 |
|
|
Jul 23 05:58:23 PM PDT 24 |
Jul 23 05:58:27 PM PDT 24 |
400236399 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1248406424 |
|
|
Jul 23 05:58:08 PM PDT 24 |
Jul 23 05:58:11 PM PDT 24 |
85198633 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2715086617 |
|
|
Jul 23 05:58:08 PM PDT 24 |
Jul 23 05:58:12 PM PDT 24 |
1825210660 ps |
| T966 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2907148989 |
|
|
Jul 23 05:58:06 PM PDT 24 |
Jul 23 05:58:07 PM PDT 24 |
14454126 ps |
| T967 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3558001365 |
|
|
Jul 23 05:58:29 PM PDT 24 |
Jul 23 05:58:31 PM PDT 24 |
105080114 ps |
| T968 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2547811694 |
|
|
Jul 23 05:58:18 PM PDT 24 |
Jul 23 05:58:20 PM PDT 24 |
320377256 ps |
| T969 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2192964116 |
|
|
Jul 23 05:58:40 PM PDT 24 |
Jul 23 05:58:42 PM PDT 24 |
47573309 ps |
| T79 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2976280634 |
|
|
Jul 23 05:58:52 PM PDT 24 |
Jul 23 05:58:55 PM PDT 24 |
873435220 ps |
| T80 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2003926244 |
|
|
Jul 23 05:58:25 PM PDT 24 |
Jul 23 05:58:26 PM PDT 24 |
22880327 ps |
| T970 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2854423950 |
|
|
Jul 23 05:58:43 PM PDT 24 |
Jul 23 05:58:45 PM PDT 24 |
39344358 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2324544316 |
|
|
Jul 23 05:58:37 PM PDT 24 |
Jul 23 05:58:44 PM PDT 24 |
149433207 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.845901777 |
|
|
Jul 23 05:58:07 PM PDT 24 |
Jul 23 05:58:08 PM PDT 24 |
46615195 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.980345377 |
|
|
Jul 23 05:58:13 PM PDT 24 |
Jul 23 05:58:14 PM PDT 24 |
75286954 ps |
| T974 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3204993110 |
|
|
Jul 23 05:58:42 PM PDT 24 |
Jul 23 05:58:45 PM PDT 24 |
142579788 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2657287820 |
|
|
Jul 23 05:58:20 PM PDT 24 |
Jul 23 05:58:25 PM PDT 24 |
753871402 ps |
| T976 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2139198852 |
|
|
Jul 23 05:58:22 PM PDT 24 |
Jul 23 05:58:24 PM PDT 24 |
14003722 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2760855906 |
|
|
Jul 23 05:58:24 PM PDT 24 |
Jul 23 05:58:26 PM PDT 24 |
224456990 ps |
| T978 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3137469724 |
|
|
Jul 23 05:58:41 PM PDT 24 |
Jul 23 05:58:43 PM PDT 24 |
48465520 ps |
| T85 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2974523835 |
|
|
Jul 23 05:58:17 PM PDT 24 |
Jul 23 05:58:18 PM PDT 24 |
34442924 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.837889608 |
|
|
Jul 23 05:58:23 PM PDT 24 |
Jul 23 05:58:24 PM PDT 24 |
12399523 ps |
| T979 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1322195346 |
|
|
Jul 23 05:58:47 PM PDT 24 |
Jul 23 05:58:48 PM PDT 24 |
48568632 ps |
| T980 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3794229970 |
|
|
Jul 23 05:58:17 PM PDT 24 |
Jul 23 05:58:18 PM PDT 24 |
39556784 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3623239133 |
|
|
Jul 23 05:58:27 PM PDT 24 |
Jul 23 05:58:29 PM PDT 24 |
25444294 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3895822520 |
|
|
Jul 23 05:58:37 PM PDT 24 |
Jul 23 05:58:38 PM PDT 24 |
20858088 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4178450924 |
|
|
Jul 23 05:58:26 PM PDT 24 |
Jul 23 05:58:28 PM PDT 24 |
20656551 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1142714913 |
|
|
Jul 23 05:58:04 PM PDT 24 |
Jul 23 05:58:07 PM PDT 24 |
397225758 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.54831520 |
|
|
Jul 23 05:58:19 PM PDT 24 |
Jul 23 05:58:22 PM PDT 24 |
170480459 ps |
| T985 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2021141304 |
|
|
Jul 23 05:58:36 PM PDT 24 |
Jul 23 05:58:40 PM PDT 24 |
63562957 ps |
| T986 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2674429423 |
|
|
Jul 23 05:58:15 PM PDT 24 |
Jul 23 05:58:20 PM PDT 24 |
548532117 ps |
| T987 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3376510742 |
|
|
Jul 23 05:58:29 PM PDT 24 |
Jul 23 05:58:31 PM PDT 24 |
212755632 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4050331044 |
|
|
Jul 23 05:58:24 PM PDT 24 |
Jul 23 05:58:28 PM PDT 24 |
1625035644 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.794479912 |
|
|
Jul 23 05:58:34 PM PDT 24 |
Jul 23 05:58:36 PM PDT 24 |
11638570 ps |
| T132 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1998321389 |
|
|
Jul 23 05:58:31 PM PDT 24 |
Jul 23 05:58:33 PM PDT 24 |
729642635 ps |
| T90 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.810248837 |
|
|
Jul 23 05:58:12 PM PDT 24 |
Jul 23 05:58:13 PM PDT 24 |
88559001 ps |
| T124 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1442890284 |
|
|
Jul 23 05:58:12 PM PDT 24 |
Jul 23 05:58:15 PM PDT 24 |
603134418 ps |
| T89 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.16548510 |
|
|
Jul 23 05:58:27 PM PDT 24 |
Jul 23 05:58:31 PM PDT 24 |
756980905 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1235764551 |
|
|
Jul 23 05:58:32 PM PDT 24 |
Jul 23 05:58:34 PM PDT 24 |
57718434 ps |
| T131 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2566099161 |
|
|
Jul 23 05:58:06 PM PDT 24 |
Jul 23 05:58:09 PM PDT 24 |
301368105 ps |
| T990 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3739642224 |
|
|
Jul 23 05:58:16 PM PDT 24 |
Jul 23 05:58:20 PM PDT 24 |
106780442 ps |
| T991 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2215156393 |
|
|
Jul 23 05:58:39 PM PDT 24 |
Jul 23 05:58:43 PM PDT 24 |
274014508 ps |
| T992 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1128309622 |
|
|
Jul 23 05:58:16 PM PDT 24 |
Jul 23 05:58:17 PM PDT 24 |
22915907 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2374465098 |
|
|
Jul 23 05:58:22 PM PDT 24 |
Jul 23 05:58:25 PM PDT 24 |
73214154 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3087666698 |
|
|
Jul 23 05:58:53 PM PDT 24 |
Jul 23 05:58:55 PM PDT 24 |
20644024 ps |
| T995 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1890626143 |
|
|
Jul 23 05:58:34 PM PDT 24 |
Jul 23 05:58:37 PM PDT 24 |
48477857 ps |
| T996 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2876604150 |
|
|
Jul 23 05:58:11 PM PDT 24 |
Jul 23 05:58:12 PM PDT 24 |
13839800 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1665693417 |
|
|
Jul 23 05:58:15 PM PDT 24 |
Jul 23 05:58:17 PM PDT 24 |
1228285711 ps |
| T998 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2815605140 |
|
|
Jul 23 05:58:18 PM PDT 24 |
Jul 23 05:58:19 PM PDT 24 |
91331642 ps |
| T999 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1598821393 |
|
|
Jul 23 05:58:37 PM PDT 24 |
Jul 23 05:58:41 PM PDT 24 |
146260760 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.625375174 |
|
|
Jul 23 05:58:28 PM PDT 24 |
Jul 23 05:58:30 PM PDT 24 |
764248075 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2153104255 |
|
|
Jul 23 05:58:11 PM PDT 24 |
Jul 23 05:58:15 PM PDT 24 |
543611951 ps |
| T126 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.556269342 |
|
|
Jul 23 05:58:40 PM PDT 24 |
Jul 23 05:58:42 PM PDT 24 |
148135918 ps |
| T1002 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1105856460 |
|
|
Jul 23 05:58:23 PM PDT 24 |
Jul 23 05:58:25 PM PDT 24 |
23057245 ps |