Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13987485	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58921668

1

T1

36090

T2

1398

T3

94571

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36351079	1			T1	98975		T2	3789		T3	47731
values[0x0]	16879857	1			T1	33082		T2	1286		T3	25518
values[0x1]	19678217	1			T1	65448		T2	2390		T3	26352

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6969083	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65940070

1

T1

117162

T2

4350

T3

97136

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	289487	1			T1	760		T2	29		T4	15
valid_sources[0x01]	259030	1			T1	692		T2	40		T4	21
valid_sources[0x02]	295664	1			T1	800		T2	24		T4	14
valid_sources[0x03]	297403	1			T1	868		T2	22		T4	21
valid_sources[0x04]	286282	1			T1	701		T2	21		T4	24
valid_sources[0x05]	284785	1			T1	812		T2	28		T4	28
valid_sources[0x06]	272923	1			T1	713		T2	22		T4	27
valid_sources[0x07]	283015	1			T1	766		T2	34		T4	21
valid_sources[0x08]	258422	1			T1	738		T2	34		T4	15
valid_sources[0x09]	252334	1			T1	798		T2	36		T4	18
valid_sources[0x0a]	296653	1			T1	823		T2	24		T4	25
valid_sources[0x0b]	274678	1			T1	809		T2	16		T4	22
valid_sources[0x0c]	311428	1			T1	816		T2	26		T4	23
valid_sources[0x0d]	265837	1			T1	785		T2	22		T3	10806
valid_sources[0x0e]	308234	1			T1	816		T2	18		T3	16132
valid_sources[0x0f]	270236	1			T1	784		T2	34		T4	21
valid_sources[0x10]	288566	1			T1	812		T2	28		T4	15
valid_sources[0x11]	296049	1			T1	755		T2	38		T4	16
valid_sources[0x12]	253777	1			T1	760		T2	20		T4	12
valid_sources[0x13]	291734	1			T1	725		T2	28		T3	302
valid_sources[0x14]	296391	1			T1	816		T2	36		T4	33
valid_sources[0x15]	289108	1			T1	742		T2	16		T4	24
valid_sources[0x16]	311623	1			T1	771		T2	32		T4	18
valid_sources[0x17]	254442	1			T1	779		T2	15		T4	23
valid_sources[0x18]	320538	1			T1	816		T2	30		T4	29
valid_sources[0x19]	309008	1			T1	868		T2	21		T4	19
valid_sources[0x1a]	266844	1			T1	857		T2	25		T3	8059
valid_sources[0x1b]	348172	1			T1	790		T2	28		T4	16
valid_sources[0x1c]	258577	1			T1	674		T2	44		T3	145
valid_sources[0x1d]	312867	1			T1	741		T2	25		T4	33
valid_sources[0x1e]	278090	1			T1	796		T2	28		T4	23
valid_sources[0x1f]	321176	1			T1	846		T2	26		T4	27
valid_sources[0x20]	261718	1			T1	815		T2	30		T4	12
valid_sources[0x21]	398467	1			T1	738		T2	28		T4	32
valid_sources[0x22]	303905	1			T1	723		T2	17		T4	25
valid_sources[0x23]	303353	1			T1	784		T2	22		T4	16
valid_sources[0x24]	257706	1			T1	727		T2	32		T4	20
valid_sources[0x25]	277307	1			T1	716		T2	32		T3	219
valid_sources[0x26]	287524	1			T1	712		T2	18		T4	14
valid_sources[0x27]	274670	1			T1	731		T2	24		T4	30
valid_sources[0x28]	255373	1			T1	813		T2	26		T4	19
valid_sources[0x29]	339262	1			T1	776		T2	13		T4	20
valid_sources[0x2a]	293908	1			T1	776		T2	22		T4	23
valid_sources[0x2b]	260947	1			T1	825		T2	27		T4	25
valid_sources[0x2c]	323159	1			T1	735		T2	23		T4	28
valid_sources[0x2d]	280416	1			T1	872		T2	24		T4	21
valid_sources[0x2e]	254854	1			T1	733		T2	42		T4	20
valid_sources[0x2f]	255514	1			T1	788		T2	21		T4	24
valid_sources[0x30]	277076	1			T1	791		T2	26		T4	17
valid_sources[0x31]	269392	1			T1	774		T2	26		T4	20
valid_sources[0x32]	281407	1			T1	757		T2	28		T3	363
valid_sources[0x33]	262889	1			T1	745		T2	39		T4	19
valid_sources[0x34]	293766	1			T1	732		T2	36		T4	27
valid_sources[0x35]	278735	1			T1	731		T2	18		T4	20
valid_sources[0x36]	283150	1			T1	725		T2	38		T3	226
valid_sources[0x37]	270105	1			T1	765		T2	36		T4	25
valid_sources[0x38]	266039	1			T1	791		T2	31		T4	15
valid_sources[0x39]	311698	1			T1	760		T2	36		T4	20
valid_sources[0x3a]	300469	1			T1	841		T2	21		T4	23
valid_sources[0x3b]	336628	1			T1	754		T2	43		T4	13
valid_sources[0x3c]	262978	1			T1	819		T2	29		T4	12
valid_sources[0x3d]	287813	1			T1	832		T2	50		T4	18
valid_sources[0x3e]	289893	1			T1	785		T2	32		T4	12
valid_sources[0x3f]	291535	1			T1	806		T2	23		T4	19
valid_sources[0x40]	256950	1			T1	766		T2	25		T4	19
valid_sources[0x41]	275021	1			T1	806		T2	34		T3	6906
valid_sources[0x42]	293881	1			T1	686		T2	18		T4	13
valid_sources[0x43]	313943	1			T1	820		T2	31		T4	16
valid_sources[0x44]	282364	1			T1	795		T2	36		T3	195
valid_sources[0x45]	259841	1			T1	768		T2	18		T4	24
valid_sources[0x46]	297854	1			T1	816		T2	34		T4	23
valid_sources[0x47]	313863	1			T1	705		T2	19		T4	24
valid_sources[0x48]	303326	1			T1	807		T2	41		T4	18
valid_sources[0x49]	278165	1			T1	737		T2	32		T4	25
valid_sources[0x4a]	277267	1			T1	849		T2	18		T4	10
valid_sources[0x4b]	339364	1			T1	821		T2	10		T4	27
valid_sources[0x4c]	286095	1			T1	774		T2	41		T4	26
valid_sources[0x4d]	299170	1			T1	754		T2	28		T4	24
valid_sources[0x4e]	280822	1			T1	769		T2	45		T4	28
valid_sources[0x4f]	337690	1			T1	773		T2	32		T3	4256
valid_sources[0x50]	281214	1			T1	706		T2	28		T4	19
valid_sources[0x51]	273264	1			T1	797		T2	27		T4	19
valid_sources[0x52]	286422	1			T1	815		T2	20		T4	21
valid_sources[0x53]	308683	1			T1	774		T2	31		T4	21
valid_sources[0x54]	275225	1			T1	707		T2	36		T3	1602
valid_sources[0x55]	284951	1			T1	742		T2	28		T4	24
valid_sources[0x56]	255474	1			T1	821		T2	22		T4	27
valid_sources[0x57]	271575	1			T1	740		T2	33		T4	30
valid_sources[0x58]	288771	1			T1	760		T2	46		T4	23
valid_sources[0x59]	278841	1			T1	779		T2	33		T4	26
valid_sources[0x5a]	277413	1			T1	789		T2	28		T4	23
valid_sources[0x5b]	252758	1			T1	684		T2	17		T4	40
valid_sources[0x5c]	301531	1			T1	697		T2	39		T4	21
valid_sources[0x5d]	285643	1			T1	726		T2	30		T3	200
valid_sources[0x5e]	272764	1			T1	814		T2	20		T4	16
valid_sources[0x5f]	302915	1			T1	779		T2	28		T4	19
valid_sources[0x60]	286591	1			T1	874		T2	36		T4	10
valid_sources[0x61]	276872	1			T1	729		T2	34		T4	21
valid_sources[0x62]	254484	1			T1	768		T2	35		T4	26
valid_sources[0x63]	283262	1			T1	717		T2	29		T4	26
valid_sources[0x64]	257121	1			T1	743		T2	25		T4	13
valid_sources[0x65]	305142	1			T1	764		T2	23		T4	21
valid_sources[0x66]	257701	1			T1	776		T2	41		T4	23
valid_sources[0x67]	260337	1			T1	794		T2	32		T4	19
valid_sources[0x68]	270748	1			T1	831		T2	62		T4	15
valid_sources[0x69]	263955	1			T1	787		T2	35		T4	17
valid_sources[0x6a]	284947	1			T1	788		T2	32		T4	20
valid_sources[0x6b]	289523	1			T1	718		T2	28		T3	203
valid_sources[0x6c]	309624	1			T1	730		T2	47		T4	26
valid_sources[0x6d]	258070	1			T1	815		T2	50		T3	3247
valid_sources[0x6e]	271118	1			T1	727		T2	18		T4	12
valid_sources[0x6f]	263473	1			T1	751		T2	45		T4	18
valid_sources[0x70]	364808	1			T1	693		T2	41		T3	9111
valid_sources[0x71]	269305	1			T1	730		T2	20		T4	27
valid_sources[0x72]	342383	1			T1	779		T2	38		T4	27
valid_sources[0x73]	258162	1			T1	815		T2	50		T4	18
valid_sources[0x74]	266974	1			T1	872		T2	18		T3	2171
valid_sources[0x75]	260851	1			T1	767		T2	29		T4	15
valid_sources[0x76]	268097	1			T1	763		T2	48		T4	34
valid_sources[0x77]	259905	1			T1	794		T2	19		T4	28
valid_sources[0x78]	263063	1			T1	729		T2	24		T4	18
valid_sources[0x79]	296419	1			T1	716		T2	21		T3	12
valid_sources[0x7a]	292302	1			T1	731		T2	24		T4	23
valid_sources[0x7b]	326784	1			T1	716		T2	16		T4	16
valid_sources[0x7c]	270466	1			T1	823		T2	15		T4	20
valid_sources[0x7d]	278117	1			T1	682		T2	26		T4	14
valid_sources[0x7e]	301977	1			T1	756		T2	34		T4	15
valid_sources[0x7f]	252441	1			T1	873		T2	31		T4	17
valid_sources[0x80]	262636	1			T1	827		T2	17		T4	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29360964

1

T1

18013

T2

714

T3

45154

values[0x0]

all_enables

biggest_size

14781171

1

T1

8965

T2

349

T3

24784

values[0x1]

all_enables

biggest_size

14779533

1

T1

9112

T2

335

T3

24633

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34648	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

126616

1

T2

1

T3

4963

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47014	1			T3	1435		T10	5		T11	19
values[0x0]	55196	1			T2	1		T3	1836		T4	1
values[0x1]	59054	1			T1	2		T2	1		T3	2113

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

134884

1

T2

1

T3

5166

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	797	1			T3	25		T22	1		T73	1
valid_sources[0x01]	703	1			T3	23		T38	1		T148	1
valid_sources[0x02]	781	1			T3	28		T38	1		T24	4
valid_sources[0x03]	686	1			T3	24		T11	1		T22	2
valid_sources[0x04]	537	1			T3	26		T11	1		T64	7
valid_sources[0x05]	490	1			T3	27		T148	2		T21	1
valid_sources[0x06]	506	1			T3	22		T24	5		T45	20
valid_sources[0x07]	443	1			T3	15		T11	1		T38	1
valid_sources[0x08]	952	1			T3	15		T11	1		T19	6
valid_sources[0x09]	568	1			T3	26		T148	2		T134	1
valid_sources[0x0a]	588	1			T3	14		T134	1		T46	4
valid_sources[0x0b]	711	1			T3	21		T148	1		T21	1
valid_sources[0x0c]	623	1			T3	15		T4	1		T63	1
valid_sources[0x0d]	883	1			T3	12		T11	1		T22	2
valid_sources[0x0e]	564	1			T3	8		T64	1		T24	1
valid_sources[0x0f]	769	1			T3	24		T19	4		T22	1
valid_sources[0x10]	530	1			T3	27		T11	1		T22	1
valid_sources[0x11]	669	1			T3	25		T141	28		T64	1
valid_sources[0x12]	618	1			T3	28		T22	2		T134	1
valid_sources[0x13]	530	1			T3	27		T64	1		T24	3
valid_sources[0x14]	570	1			T3	31		T11	1		T22	1
valid_sources[0x15]	657	1			T3	14		T21	3		T24	2
valid_sources[0x16]	556	1			T3	31		T11	1		T58	1
valid_sources[0x17]	537	1			T3	12		T134	1		T40	1
valid_sources[0x18]	512	1			T3	17		T73	1		T134	1
valid_sources[0x19]	630	1			T3	10		T22	1		T134	1
valid_sources[0x1a]	553	1			T3	11		T22	1		T57	3
valid_sources[0x1b]	752	1			T3	17		T11	1		T24	6
valid_sources[0x1c]	646	1			T3	15		T19	1		T24	2
valid_sources[0x1d]	618	1			T3	26		T11	1		T22	3
valid_sources[0x1e]	572	1			T3	20		T11	1		T148	1
valid_sources[0x1f]	560	1			T3	17		T11	1		T64	3
valid_sources[0x20]	597	1			T3	32		T134	2		T24	4
valid_sources[0x21]	579	1			T3	20		T64	7		T21	1
valid_sources[0x22]	606	1			T3	15		T22	1		T58	1
valid_sources[0x23]	585	1			T3	27		T11	1		T148	1
valid_sources[0x24]	702	1			T3	19		T22	1		T46	1
valid_sources[0x25]	599	1			T3	20		T11	1		T149	1
valid_sources[0x26]	688	1			T3	19		T9	3		T148	1
valid_sources[0x27]	619	1			T3	24		T22	1		T21	2
valid_sources[0x28]	573	1			T3	18		T19	2		T22	2
valid_sources[0x29]	595	1			T3	25		T64	2		T24	5
valid_sources[0x2a]	780	1			T3	16		T11	1		T22	1
valid_sources[0x2b]	577	1			T3	41		T21	1		T24	2
valid_sources[0x2c]	499	1			T3	20		T148	1		T24	7
valid_sources[0x2d]	896	1			T3	25		T21	2		T24	2
valid_sources[0x2e]	568	1			T3	23		T24	6		T45	6
valid_sources[0x2f]	536	1			T3	25		T11	1		T64	3
valid_sources[0x30]	525	1			T3	25		T22	1		T144	4
valid_sources[0x31]	611	1			T3	11		T11	1		T24	5
valid_sources[0x32]	892	1			T3	18		T11	1		T22	1
valid_sources[0x33]	769	1			T3	32		T24	4		T49	40
valid_sources[0x34]	525	1			T3	13		T73	1		T148	1
valid_sources[0x35]	576	1			T3	21		T63	1		T22	1
valid_sources[0x36]	456	1			T3	15		T38	1		T73	1
valid_sources[0x37]	547	1			T3	30		T134	1		T24	4
valid_sources[0x38]	626	1			T3	6		T11	2		T22	6
valid_sources[0x39]	590	1			T3	23		T24	9		T45	17
valid_sources[0x3a]	492	1			T3	17		T38	2		T24	2
valid_sources[0x3b]	611	1			T3	26		T19	1		T22	1
valid_sources[0x3c]	504	1			T3	14		T20	47		T134	1
valid_sources[0x3d]	639	1			T3	20		T22	1		T64	4
valid_sources[0x3e]	1031	1			T3	15		T11	1		T64	4
valid_sources[0x3f]	1004	1			T3	32		T11	1		T38	2
valid_sources[0x40]	810	1			T3	21		T11	1		T22	2
valid_sources[0x41]	624	1			T3	28		T64	6		T134	3
valid_sources[0x42]	535	1			T3	32		T5	34		T134	1
valid_sources[0x43]	476	1			T3	21		T11	1		T96	1
valid_sources[0x44]	512	1			T3	14		T11	1		T134	1
valid_sources[0x45]	661	1			T3	21		T22	1		T73	1
valid_sources[0x46]	805	1			T3	23		T22	1		T58	1
valid_sources[0x47]	529	1			T3	22		T148	1		T24	3
valid_sources[0x48]	621	1			T2	2		T3	20		T11	1
valid_sources[0x49]	525	1			T3	33		T22	3		T64	1
valid_sources[0x4a]	515	1			T3	23		T11	1		T148	1
valid_sources[0x4b]	523	1			T3	19		T11	1		T25	1
valid_sources[0x4c]	754	1			T3	41		T19	3		T38	2
valid_sources[0x4d]	639	1			T3	24		T11	1		T140	38
valid_sources[0x4e]	681	1			T3	22		T24	7		T45	46
valid_sources[0x4f]	463	1			T3	12		T11	1		T24	1
valid_sources[0x50]	441	1			T3	24		T63	1		T148	1
valid_sources[0x51]	544	1			T3	20		T11	1		T38	1
valid_sources[0x52]	799	1			T3	16		T19	1		T22	2
valid_sources[0x53]	482	1			T3	24		T24	1		T45	21
valid_sources[0x54]	1107	1			T3	30		T24	4		T45	19
valid_sources[0x55]	511	1			T3	20		T8	11		T38	1
valid_sources[0x56]	806	1			T3	18		T148	1		T24	5
valid_sources[0x57]	1049	1			T3	42		T22	1		T144	5
valid_sources[0x58]	502	1			T3	22		T24	1		T16	2
valid_sources[0x59]	837	1			T3	18		T19	1		T150	1
valid_sources[0x5a]	546	1			T3	18		T64	1		T24	3
valid_sources[0x5b]	883	1			T3	31		T9	1		T64	2
valid_sources[0x5c]	652	1			T3	16		T22	1		T38	1
valid_sources[0x5d]	610	1			T3	32		T11	3		T58	2
valid_sources[0x5e]	727	1			T3	12		T11	2		T22	1
valid_sources[0x5f]	595	1			T3	17		T22	1		T38	1
valid_sources[0x60]	861	1			T3	15		T11	1		T38	1
valid_sources[0x61]	627	1			T3	31		T64	8		T151	1
valid_sources[0x62]	513	1			T3	24		T11	1		T24	2
valid_sources[0x63]	463	1			T3	28		T12	1		T22	1
valid_sources[0x64]	878	1			T3	30		T23	3		T21	1
valid_sources[0x65]	648	1			T3	17		T64	2		T24	2
valid_sources[0x66]	562	1			T3	31		T38	1		T24	2
valid_sources[0x67]	499	1			T3	21		T11	1		T19	3
valid_sources[0x68]	570	1			T3	28		T11	2		T19	2
valid_sources[0x69]	575	1			T3	25		T9	2		T22	1
valid_sources[0x6a]	518	1			T3	22		T22	1		T24	3
valid_sources[0x6b]	785	1			T3	11		T22	2		T134	1
valid_sources[0x6c]	652	1			T3	24		T64	5		T23	150
valid_sources[0x6d]	493	1			T3	20		T22	2		T134	1
valid_sources[0x6e]	780	1			T3	14		T11	1		T96	1
valid_sources[0x6f]	509	1			T3	21		T11	1		T22	1
valid_sources[0x70]	658	1			T3	18		T11	1		T13	2
valid_sources[0x71]	518	1			T3	18		T11	1		T22	2
valid_sources[0x72]	517	1			T3	13		T19	1		T22	1
valid_sources[0x73]	557	1			T3	21		T64	2		T24	2
valid_sources[0x74]	727	1			T3	12		T134	1		T40	1
valid_sources[0x75]	690	1			T3	17		T8	10		T134	1
valid_sources[0x76]	553	1			T3	24		T22	2		T134	2
valid_sources[0x77]	717	1			T3	20		T22	1		T134	2
valid_sources[0x78]	540	1			T3	27		T22	1		T38	2
valid_sources[0x79]	494	1			T3	17		T22	1		T64	5
valid_sources[0x7a]	647	1			T3	26		T63	1		T22	1
valid_sources[0x7b]	447	1			T3	15		T64	1		T40	1
valid_sources[0x7c]	450	1			T3	24		T144	2		T134	1
valid_sources[0x7d]	510	1			T3	20		T64	1		T148	1
valid_sources[0x7e]	502	1			T3	31		T40	1		T24	5
valid_sources[0x7f]	476	1			T3	17		T19	8		T144	3
valid_sources[0x80]	492	1			T3	19		T11	2		T96	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

34892

1

T3

1322

T10

4

T11

8

values[0x0]

all_enables

biggest_size

46877

1

T2

1

T3

1799

T4

1

values[0x1]

all_enables

biggest_size

44847

1

T3

1842

T9

1

T5

2