Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13687734

1

T1

161415

T2

6067

T3

12059

full_word

54098437

1

T1

36090

T2

1398

T3

87927

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67785881	1			T1	197505		T2	7465		T3	99986
auto[TlIntgErrCmd]	114	1			T54	1		T55	9		T56	4
auto[TlIntgErrData]	83	1			T54	2		T55	7		T56	3
auto[TlIntgErrBoth]	93	1			T54	7		T55	4		T56	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31170610

1

T1

98975

T2

3789

T3

41276

auto[1]

36615561

1

T1

98530

T2

3676

T3

58710

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6553422	1			T1	80962		T2	3075		T3	3475
auto[TlIntgErrNone]	partial	auto[1]	7134047	1			T1	80453		T2	2992		T3	8584
auto[TlIntgErrNone]	full_word	auto[0]	24617061	1			T1	18013		T2	714		T3	37801
auto[TlIntgErrNone]	full_word	auto[1]	29481351	1			T1	18077		T2	684		T3	50126
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T54	1		T55	4		T124	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T55	5		T56	4		T124	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T121	1		T125	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T125	1		T130	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T55	3		T56	2		T124	3
auto[TlIntgErrData]	partial	auto[1]	37	1			T54	2		T55	3		T56	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T127	1		T132	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T55	1		T133	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T54	1		T55	1		T124	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T54	4		T55	3		T56	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T127	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T54	2		T121	1		T133	1