Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	678436	1			T2	217		T4	3		T10	7
auto[1]	10385899	1			T1	83480		T2	582		T3	7670
auto[2]	553895	1			T2	123		T10	8		T6	5550
auto[3]	10265030	1			T1	82802		T2	482		T3	7520

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14055246	1			T1	5468		T2	21		T3	12403
auto[1]	2103375	1			T1	24938		T2	146		T3	1329
auto[2]	2118561	1			T1	25072		T2	185		T3	1322
auto[3]	3606078	1			T1	110804		T2	1052		T3	136

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8392062

1

T2

1403

T3

15174

T4

11

auto[1]

13491198

1

T1

166282

T2

1

T3

16

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	294635	1			T2	5		T4	1		T10	6
auto[0]	auto[0]	auto[1]	30352	1			T2	31		T10	1		T6	518
auto[0]	auto[0]	auto[2]	30401	1			T2	36		T4	1		T6	481
auto[0]	auto[0]	auto[3]	8656	1			T2	145		T4	1		T6	46
auto[0]	auto[1]	auto[0]	3171199	1			T2	11		T3	6237		T9	48967
auto[0]	auto[1]	auto[1]	331684	1			T2	85		T3	685		T4	1
auto[0]	auto[1]	auto[2]	316022	1			T2	50		T3	668		T9	4828
auto[0]	auto[1]	auto[3]	65661	1			T2	436		T3	73		T4	5
auto[0]	auto[2]	auto[0]	248914	1			T6	4644		T38	809		T138	940
auto[0]	auto[2]	auto[1]	25645	1			T6	485		T38	87		T138	88
auto[0]	auto[2]	auto[2]	28328	1			T2	21		T10	8		T6	382
auto[0]	auto[2]	auto[3]	7051	1			T2	102		T6	34		T19	1
auto[0]	auto[3]	auto[0]	3123210	1			T2	5		T3	6151		T9	48793
auto[0]	auto[3]	auto[1]	312459	1			T2	30		T3	644		T9	4965
auto[0]	auto[3]	auto[2]	330420	1			T2	77		T3	653		T4	1
auto[0]	auto[3]	auto[3]	67425	1			T2	369		T3	63		T4	1
auto[1]	auto[0]	auto[0]	10825	1			T6	5		T38	1		T73	1
auto[1]	auto[0]	auto[1]	46475	1			T144	1		T145	1		T31	1
auto[1]	auto[0]	auto[2]	46604	1			T6	1		T31	1		T142	4836
auto[1]	auto[0]	auto[3]	210488	1			T57	2		T142	21753		T143	15777
auto[1]	auto[1]	auto[0]	3602181	1			T1	2715		T3	7		T9	39
auto[1]	auto[1]	auto[1]	678050	1			T1	12467		T9	3		T5	7
auto[1]	auto[1]	auto[2]	660322	1			T1	12661		T9	2		T5	6
auto[1]	auto[1]	auto[3]	1560780	1			T1	55637		T9	1		T95	594
auto[1]	auto[2]	auto[0]	7240	1			T6	5		T144	2		T145	6
auto[1]	auto[2]	auto[1]	31885	1			T31	2		T146	1		T142	4501
auto[1]	auto[2]	auto[2]	37451	1			T38	1		T145	2		T142	3974
auto[1]	auto[2]	auto[3]	167381	1			T142	18260		T143	10701		T147	2865
auto[1]	auto[3]	auto[0]	3597042	1			T1	2753		T3	8		T9	46
auto[1]	auto[3]	auto[1]	646825	1			T1	12471		T9	7		T5	6
auto[1]	auto[3]	auto[2]	669013	1			T1	12411		T2	1		T3	1
auto[1]	auto[3]	auto[3]	1518636	1			T1	55167		T9	1		T5	2