Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	340380240	182130	0	0
ctrl_regwen_rd_A	340380240	4352	0	0
exec_rd_A	340380240	3974	0	0
exec_regwen_rd_A	340380240	4222	0	0
readback_rd_A	340380240	2690	0	0
readback_regwen_rd_A	340380240	2295	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340380240	182130	0	0
T3	185736	8747	0	0
T4	64457	0	0	0
T5	365277	0	0	0
T6	588954	0	0	0
T7	20877	0	0	0
T9	298151	0	0	0
T10	362526	0	0	0
T11	239319	0	0	0
T12	3265	0	0	0
T23	0	1044	0	0
T24	0	854	0	0
T42	0	2730	0	0
T45	0	6495	0	0
T46	0	2259	0	0
T49	0	10839	0	0
T50	0	5384	0	0
T51	6883	0	0	0
T52	0	920	0	0
T62	0	3959	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340380240	4352	0	0
T44	0	267	0	0
T102	303819	566	0	0
T103	0	107	0	0
T104	0	252	0	0
T105	0	208	0	0
T106	0	362	0	0
T107	0	217	0	0
T108	0	124	0	0
T109	0	219	0	0
T110	0	60	0	0
T111	45240	0	0	0
T112	127276	0	0	0
T113	3515	0	0	0
T114	1829	0	0	0
T115	14362	0	0	0
T116	752837	0	0	0
T117	8903	0	0	0
T118	265784	0	0	0
T119	324590	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340380240	3974	0	0
T44	0	154	0	0
T102	303819	556	0	0
T103	0	127	0	0
T104	0	168	0	0
T105	0	145	0	0
T106	0	226	0	0
T107	0	203	0	0
T108	0	83	0	0
T109	0	241	0	0
T110	0	101	0	0
T111	45240	0	0	0
T112	127276	0	0	0
T113	3515	0	0	0
T114	1829	0	0	0
T115	14362	0	0	0
T116	752837	0	0	0
T117	8903	0	0	0
T118	265784	0	0	0
T119	324590	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340380240	4222	0	0
T44	0	266	0	0
T102	303819	579	0	0
T103	0	122	0	0
T104	0	235	0	0
T105	0	203	0	0
T106	0	298	0	0
T107	0	241	0	0
T108	0	114	0	0
T109	0	179	0	0
T110	0	138	0	0
T111	45240	0	0	0
T112	127276	0	0	0
T113	3515	0	0	0
T114	1829	0	0	0
T115	14362	0	0	0
T116	752837	0	0	0
T117	8903	0	0	0
T118	265784	0	0	0
T119	324590	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340380240	2690	0	0
T44	0	256	0	0
T102	303819	576	0	0
T103	0	125	0	0
T104	0	217	0	0
T105	0	130	0	0
T106	0	324	0	0
T107	0	207	0	0
T108	0	97	0	0
T109	0	126	0	0
T110	0	84	0	0
T111	45240	0	0	0
T112	127276	0	0	0
T113	3515	0	0	0
T114	1829	0	0	0
T115	14362	0	0	0
T116	752837	0	0	0
T117	8903	0	0	0
T118	265784	0	0	0
T119	324590	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340380240	2295	0	0
T44	0	218	0	0
T102	303819	494	0	0
T103	0	103	0	0
T104	0	155	0	0
T105	0	142	0	0
T106	0	195	0	0
T107	0	184	0	0
T108	0	110	0	0
T109	0	156	0	0
T110	0	83	0	0
T111	45240	0	0	0
T112	127276	0	0	0
T113	3515	0	0	0
T114	1829	0	0	0
T115	14362	0	0	0
T116	752837	0	0	0
T117	8903	0	0	0
T118	265784	0	0	0
T119	324590	0	0	0