Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14719307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59823194

1

T1

137901

T2

6262

T3

4295

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37154564	1			T1	76010		T2	3843		T3	2117
values[0x0]	17221074	1			T1	36460		T2	1783		T3	1068
values[0x1]	20166863	1			T1	39163		T2	2062		T3	1110

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7335982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67206519

1

T1

144651

T2

6994

T3

4295

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	273878	1			T1	573		T3	24		T4	810
valid_sources[0x01]	274847	1			T1	574		T3	68		T4	779
valid_sources[0x02]	268573	1			T1	570		T3	32		T4	780
valid_sources[0x03]	304684	1			T1	597		T3	22		T4	781
valid_sources[0x04]	286640	1			T1	598		T3	26		T4	791
valid_sources[0x05]	278001	1			T1	568		T3	2		T4	790
valid_sources[0x06]	274415	1			T1	576		T3	40		T4	760
valid_sources[0x07]	276569	1			T1	569		T3	31		T4	799
valid_sources[0x08]	246244	1			T1	575		T3	22		T4	753
valid_sources[0x09]	247331	1			T1	578		T3	13		T4	750
valid_sources[0x0a]	281279	1			T1	588		T3	10		T4	757
valid_sources[0x0b]	319437	1			T1	633		T3	15		T4	746
valid_sources[0x0c]	314696	1			T1	550		T3	21		T4	750
valid_sources[0x0d]	274164	1			T1	636		T3	24		T4	770
valid_sources[0x0e]	288495	1			T1	609		T3	14		T4	747
valid_sources[0x0f]	252880	1			T1	560		T3	17		T4	844
valid_sources[0x10]	283579	1			T1	587		T3	4		T4	798
valid_sources[0x11]	285456	1			T1	615		T3	10		T4	785
valid_sources[0x12]	284552	1			T1	600		T3	6		T4	816
valid_sources[0x13]	279607	1			T1	588		T3	2		T4	773
valid_sources[0x14]	340514	1			T1	589		T3	14		T4	810
valid_sources[0x15]	347295	1			T1	590		T3	38		T4	732
valid_sources[0x16]	270312	1			T1	559		T3	3		T4	789
valid_sources[0x17]	296011	1			T1	629		T3	4		T4	799
valid_sources[0x18]	265007	1			T1	588		T3	7		T4	807
valid_sources[0x19]	324564	1			T1	590		T3	21		T4	750
valid_sources[0x1a]	324396	1			T1	541		T3	9		T4	759
valid_sources[0x1b]	320737	1			T1	620		T3	1		T4	743
valid_sources[0x1c]	261015	1			T1	593		T3	14		T4	777
valid_sources[0x1d]	336076	1			T1	598		T3	14		T4	821
valid_sources[0x1e]	271729	1			T1	565		T4	808		T7	14
valid_sources[0x1f]	266298	1			T1	600		T3	13		T4	802
valid_sources[0x20]	332125	1			T1	566		T3	11		T4	748
valid_sources[0x21]	276061	1			T1	594		T3	15		T4	762
valid_sources[0x22]	263109	1			T1	578		T3	8		T4	807
valid_sources[0x23]	299594	1			T1	610		T3	23		T4	760
valid_sources[0x24]	246782	1			T1	598		T3	22		T4	753
valid_sources[0x25]	278431	1			T1	556		T3	37		T4	758
valid_sources[0x26]	278500	1			T1	582		T3	11		T4	791
valid_sources[0x27]	329565	1			T1	605		T3	1		T4	755
valid_sources[0x28]	250724	1			T1	604		T3	10		T4	742
valid_sources[0x29]	263095	1			T1	590		T3	14		T4	733
valid_sources[0x2a]	301841	1			T1	637		T3	7		T4	801
valid_sources[0x2b]	289145	1			T1	583		T3	23		T4	735
valid_sources[0x2c]	261524	1			T1	568		T3	1		T4	771
valid_sources[0x2d]	293795	1			T1	597		T3	19		T4	778
valid_sources[0x2e]	304385	1			T1	603		T3	17		T4	711
valid_sources[0x2f]	295138	1			T1	622		T3	26		T4	820
valid_sources[0x30]	278630	1			T1	635		T3	3		T4	815
valid_sources[0x31]	308329	1			T1	589		T3	42		T4	761
valid_sources[0x32]	278320	1			T1	590		T3	5		T4	751
valid_sources[0x33]	317242	1			T1	645		T4	759		T7	18
valid_sources[0x34]	302002	1			T1	645		T3	17		T4	809
valid_sources[0x35]	264694	1			T1	587		T3	11		T4	759
valid_sources[0x36]	262471	1			T1	581		T3	21		T4	770
valid_sources[0x37]	306204	1			T1	519		T3	13		T4	706
valid_sources[0x38]	295517	1			T1	604		T3	19		T4	740
valid_sources[0x39]	320148	1			T1	572		T3	32		T4	794
valid_sources[0x3a]	253983	1			T1	618		T3	25		T4	749
valid_sources[0x3b]	292874	1			T1	575		T3	11		T4	727
valid_sources[0x3c]	296249	1			T1	587		T3	18		T4	775
valid_sources[0x3d]	285968	1			T1	599		T3	8		T4	779
valid_sources[0x3e]	261021	1			T1	566		T3	9		T4	721
valid_sources[0x3f]	311729	1			T1	575		T3	52		T4	793
valid_sources[0x40]	326729	1			T1	589		T3	7		T4	727
valid_sources[0x41]	271039	1			T1	600		T3	39		T4	749
valid_sources[0x42]	264324	1			T1	543		T3	13		T4	785
valid_sources[0x43]	297076	1			T1	626		T3	17		T4	779
valid_sources[0x44]	298214	1			T1	623		T3	10		T4	755
valid_sources[0x45]	283940	1			T1	644		T3	10		T4	749
valid_sources[0x46]	314154	1			T1	599		T3	2		T4	812
valid_sources[0x47]	294662	1			T1	622		T3	19		T4	748
valid_sources[0x48]	262010	1			T1	606		T3	3		T4	759
valid_sources[0x49]	288863	1			T1	608		T3	2		T4	789
valid_sources[0x4a]	258309	1			T1	557		T3	30		T4	852
valid_sources[0x4b]	369470	1			T1	554		T3	14		T4	767
valid_sources[0x4c]	275777	1			T1	559		T3	26		T4	749
valid_sources[0x4d]	310675	1			T1	593		T3	29		T4	793
valid_sources[0x4e]	310301	1			T1	561		T3	34		T4	742
valid_sources[0x4f]	254067	1			T1	589		T3	5		T4	732
valid_sources[0x50]	276956	1			T1	623		T3	29		T4	744
valid_sources[0x51]	317192	1			T1	580		T2	3844		T3	2
valid_sources[0x52]	258111	1			T1	605		T3	7		T4	774
valid_sources[0x53]	329782	1			T1	523		T3	11		T4	747
valid_sources[0x54]	340167	1			T1	576		T3	2		T4	805
valid_sources[0x55]	376095	1			T1	626		T3	6		T4	713
valid_sources[0x56]	327202	1			T1	595		T3	6		T4	767
valid_sources[0x57]	318633	1			T1	605		T3	7		T4	795
valid_sources[0x58]	287425	1			T1	627		T3	11		T4	717
valid_sources[0x59]	301353	1			T1	608		T3	34		T4	749
valid_sources[0x5a]	311103	1			T1	559		T3	18		T4	800
valid_sources[0x5b]	304499	1			T1	566		T3	6		T4	736
valid_sources[0x5c]	293047	1			T1	607		T3	27		T4	713
valid_sources[0x5d]	299433	1			T1	593		T3	27		T4	778
valid_sources[0x5e]	284475	1			T1	621		T2	3844		T3	28
valid_sources[0x5f]	270118	1			T1	578		T3	22		T4	772
valid_sources[0x60]	342331	1			T1	596		T3	15		T4	767
valid_sources[0x61]	347238	1			T1	563		T3	18		T4	790
valid_sources[0x62]	318397	1			T1	617		T3	14		T4	712
valid_sources[0x63]	295343	1			T1	624		T3	27		T4	772
valid_sources[0x64]	258390	1			T1	622		T3	19		T4	800
valid_sources[0x65]	260557	1			T1	600		T3	14		T4	811
valid_sources[0x66]	271444	1			T1	589		T3	25		T4	755
valid_sources[0x67]	263685	1			T1	590		T3	18		T4	850
valid_sources[0x68]	285112	1			T1	608		T4	714		T7	7
valid_sources[0x69]	293206	1			T1	576		T3	7		T4	769
valid_sources[0x6a]	303148	1			T1	618		T3	10		T4	706
valid_sources[0x6b]	276384	1			T1	596		T3	17		T4	748
valid_sources[0x6c]	256596	1			T1	597		T3	25		T4	791
valid_sources[0x6d]	346181	1			T1	581		T3	19		T4	808
valid_sources[0x6e]	333330	1			T1	622		T3	27		T4	801
valid_sources[0x6f]	285374	1			T1	639		T3	41		T4	752
valid_sources[0x70]	316638	1			T1	591		T3	9		T4	811
valid_sources[0x71]	294471	1			T1	576		T3	20		T4	715
valid_sources[0x72]	275487	1			T1	600		T4	751		T7	11
valid_sources[0x73]	262174	1			T1	603		T3	41		T4	783
valid_sources[0x74]	271812	1			T1	566		T3	12		T4	799
valid_sources[0x75]	320287	1			T1	562		T3	12		T4	752
valid_sources[0x76]	334047	1			T1	569		T3	23		T4	738
valid_sources[0x77]	269800	1			T1	621		T3	9		T4	726
valid_sources[0x78]	333929	1			T1	557		T3	34		T4	740
valid_sources[0x79]	268196	1			T1	624		T3	19		T4	777
valid_sources[0x7a]	272931	1			T1	599		T3	26		T4	757
valid_sources[0x7b]	300973	1			T1	622		T3	6		T4	819
valid_sources[0x7c]	323106	1			T1	567		T3	9		T4	759
valid_sources[0x7d]	323596	1			T1	553		T3	48		T4	709
valid_sources[0x7e]	271466	1			T1	570		T3	10		T4	768
valid_sources[0x7f]	248935	1			T1	640		T3	22		T4	765
valid_sources[0x80]	262039	1			T1	575		T3	5		T4	780

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29798640

1

T1

69097

T2

3146

T3

2117

values[0x0]

all_enables

biggest_size

15011720

1

T1

34362

T2

1598

T3

1068

values[0x1]

all_enables

biggest_size

15012834

1

T1

34442

T2

1518

T3

1110

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37198	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

144548

1

T1

1

T2

1

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52479	1			T7	30		T8	21		T9	44
values[0x0]	62232	1			T1	1		T2	2		T3	1
values[0x1]	67035	1			T1	1		T3	1		T4	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28059	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

153687

1

T1

1

T2

1

T10

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	681	1			T18	13		T56	2		T23	17
valid_sources[0x01]	715	1			T61	1		T23	9		T69	1
valid_sources[0x02]	932	1			T8	1		T18	18		T23	4
valid_sources[0x03]	571	1			T18	25		T61	1		T23	10
valid_sources[0x04]	1076	1			T7	3		T11	7		T8	2
valid_sources[0x05]	501	1			T8	1		T18	4		T150	5
valid_sources[0x06]	550	1			T18	10		T23	6		T85	2
valid_sources[0x07]	587	1			T7	1		T18	23		T43	2
valid_sources[0x08]	574	1			T40	1		T23	9		T153	2
valid_sources[0x09]	1042	1			T2	1		T8	1		T18	3
valid_sources[0x0a]	643	1			T8	2		T18	19		T44	2
valid_sources[0x0b]	564	1			T18	17		T23	22		T14	1
valid_sources[0x0c]	663	1			T18	32		T61	1		T23	34
valid_sources[0x0d]	927	1			T18	43		T21	2		T23	9
valid_sources[0x0e]	823	1			T40	2		T18	13		T61	1
valid_sources[0x0f]	613	1			T18	7		T23	2		T14	1
valid_sources[0x10]	524	1			T18	5		T23	11		T19	11
valid_sources[0x11]	502	1			T18	5		T23	21		T85	1
valid_sources[0x12]	804	1			T18	9		T23	20		T85	1
valid_sources[0x13]	837	1			T11	2		T18	22		T23	5
valid_sources[0x14]	833	1			T18	23		T56	1		T23	4
valid_sources[0x15]	776	1			T7	3		T18	2		T23	17
valid_sources[0x16]	842	1			T18	12		T78	2		T23	22
valid_sources[0x17]	833	1			T23	33		T129	1		T24	16
valid_sources[0x18]	771	1			T18	5		T23	13		T85	1
valid_sources[0x19]	804	1			T18	5		T23	8		T154	1
valid_sources[0x1a]	597	1			T18	2		T43	1		T23	12
valid_sources[0x1b]	851	1			T23	28		T24	2		T19	20
valid_sources[0x1c]	676	1			T7	2		T8	1		T18	41
valid_sources[0x1d]	615	1			T18	8		T56	1		T23	28
valid_sources[0x1e]	1194	1			T18	20		T96	1		T21	7
valid_sources[0x1f]	601	1			T8	1		T18	2		T84	3
valid_sources[0x20]	654	1			T18	15		T23	1		T146	1
valid_sources[0x21]	705	1			T2	1		T18	7		T23	30
valid_sources[0x22]	638	1			T7	1		T8	1		T18	8
valid_sources[0x23]	574	1			T18	26		T23	7		T24	1
valid_sources[0x24]	606	1			T8	1		T9	1		T70	24
valid_sources[0x25]	1384	1			T18	21		T61	1		T23	23
valid_sources[0x26]	605	1			T39	4		T23	18		T45	1
valid_sources[0x27]	919	1			T7	2		T40	1		T23	16
valid_sources[0x28]	757	1			T4	10		T9	1		T18	3
valid_sources[0x29]	713	1			T18	16		T56	5		T23	14
valid_sources[0x2a]	1029	1			T18	13		T78	4		T56	1
valid_sources[0x2b]	586	1			T18	10		T61	1		T23	16
valid_sources[0x2c]	686	1			T9	1		T18	8		T23	18
valid_sources[0x2d]	485	1			T18	2		T23	6		T154	1
valid_sources[0x2e]	1180	1			T11	1		T18	11		T43	1
valid_sources[0x2f]	770	1			T18	16		T23	21		T155	1
valid_sources[0x30]	882	1			T8	1		T18	4		T56	1
valid_sources[0x31]	641	1			T18	3		T23	6		T69	2
valid_sources[0x32]	577	1			T40	1		T18	3		T84	1
valid_sources[0x33]	508	1			T18	9		T84	2		T23	7
valid_sources[0x34]	770	1			T18	10		T23	6		T154	4
valid_sources[0x35]	705	1			T3	1		T18	15		T23	10
valid_sources[0x36]	795	1			T11	4		T18	14		T78	1
valid_sources[0x37]	707	1			T18	13		T96	1		T56	1
valid_sources[0x38]	742	1			T78	1		T23	23		T85	1
valid_sources[0x39]	668	1			T18	13		T56	2		T23	6
valid_sources[0x3a]	524	1			T7	2		T8	1		T18	11
valid_sources[0x3b]	760	1			T7	2		T9	3		T18	12
valid_sources[0x3c]	656	1			T18	9		T56	3		T61	1
valid_sources[0x3d]	543	1			T18	5		T43	1		T23	7
valid_sources[0x3e]	456	1			T11	1		T40	2		T18	13
valid_sources[0x3f]	500	1			T18	16		T81	5		T23	6
valid_sources[0x40]	594	1			T18	2		T61	1		T23	20
valid_sources[0x41]	775	1			T8	1		T18	10		T23	30
valid_sources[0x42]	602	1			T7	3		T18	23		T78	1
valid_sources[0x43]	615	1			T56	1		T23	4		T154	2
valid_sources[0x44]	640	1			T18	3		T83	2		T23	4
valid_sources[0x45]	533	1			T18	4		T150	4		T56	1
valid_sources[0x46]	1184	1			T4	5		T7	1		T18	2
valid_sources[0x47]	641	1			T18	24		T78	2		T23	12
valid_sources[0x48]	512	1			T11	1		T9	2		T18	3
valid_sources[0x49]	840	1			T21	1		T23	9		T69	1
valid_sources[0x4a]	685	1			T12	5		T9	1		T18	16
valid_sources[0x4b]	693	1			T4	2		T11	1		T18	14
valid_sources[0x4c]	1272	1			T8	1		T18	32		T61	1
valid_sources[0x4d]	571	1			T18	4		T23	3		T85	1
valid_sources[0x4e]	779	1			T18	6		T23	16		T24	2
valid_sources[0x4f]	714	1			T18	18		T23	16		T146	1
valid_sources[0x50]	470	1			T8	1		T18	2		T56	1
valid_sources[0x51]	646	1			T7	1		T40	1		T23	18
valid_sources[0x52]	985	1			T18	2		T23	2		T129	1
valid_sources[0x53]	986	1			T11	3		T23	6		T14	1
valid_sources[0x54]	530	1			T7	2		T8	1		T18	3
valid_sources[0x55]	1063	1			T18	16		T56	1		T23	18
valid_sources[0x56]	681	1			T18	15		T23	14		T24	3
valid_sources[0x57]	881	1			T18	21		T23	5		T69	2
valid_sources[0x58]	695	1			T8	1		T18	5		T21	7
valid_sources[0x59]	563	1			T18	7		T78	1		T61	1
valid_sources[0x5a]	831	1			T9	11		T43	1		T61	1
valid_sources[0x5b]	870	1			T8	1		T18	19		T56	1
valid_sources[0x5c]	646	1			T4	2		T18	58		T96	1
valid_sources[0x5d]	566	1			T8	1		T18	14		T23	13
valid_sources[0x5e]	632	1			T12	4		T18	34		T25	1
valid_sources[0x5f]	636	1			T4	2		T18	2		T23	23
valid_sources[0x60]	585	1			T18	9		T23	21		T85	2
valid_sources[0x61]	903	1			T8	1		T18	15		T56	1
valid_sources[0x62]	562	1			T18	5		T23	6		T14	1
valid_sources[0x63]	651	1			T18	36		T23	23		T14	1
valid_sources[0x64]	766	1			T18	21		T56	1		T23	26
valid_sources[0x65]	1173	1			T9	5		T18	11		T23	9
valid_sources[0x66]	515	1			T7	2		T9	1		T18	6
valid_sources[0x67]	906	1			T6	2		T18	1		T113	5
valid_sources[0x68]	805	1			T18	12		T56	2		T61	1
valid_sources[0x69]	662	1			T18	19		T23	15		T85	2
valid_sources[0x6a]	527	1			T8	1		T23	22		T24	9
valid_sources[0x6b]	529	1			T18	24		T56	2		T24	6
valid_sources[0x6c]	1056	1			T18	13		T23	23		T13	1
valid_sources[0x6d]	685	1			T8	1		T40	1		T18	3
valid_sources[0x6e]	659	1			T18	4		T156	1		T61	1
valid_sources[0x6f]	536	1			T18	7		T58	2		T61	1
valid_sources[0x70]	806	1			T18	21		T55	2		T56	2
valid_sources[0x71]	610	1			T18	41		T23	7		T157	1
valid_sources[0x72]	577	1			T7	10		T18	2		T23	7
valid_sources[0x73]	945	1			T18	50		T21	2		T23	15
valid_sources[0x74]	606	1			T18	5		T23	2		T85	1
valid_sources[0x75]	559	1			T18	12		T23	23		T85	1
valid_sources[0x76]	786	1			T18	23		T21	1		T23	8
valid_sources[0x77]	569	1			T9	7		T18	16		T23	19
valid_sources[0x78]	833	1			T3	1		T18	1		T55	1
valid_sources[0x79]	554	1			T18	4		T21	1		T23	18
valid_sources[0x7a]	618	1			T18	15		T61	1		T23	6
valid_sources[0x7b]	744	1			T8	1		T18	6		T23	13
valid_sources[0x7c]	653	1			T11	1		T18	33		T23	10
valid_sources[0x7d]	905	1			T23	17		T14	1		T69	1
valid_sources[0x7e]	857	1			T18	13		T56	3		T23	5
valid_sources[0x7f]	539	1			T18	5		T43	1		T23	12
valid_sources[0x80]	654	1			T18	8		T158	1		T61	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39464

1

T7

15

T8

10

T9

17

values[0x0]

all_enables

biggest_size

53702

1

T1

1

T2

1

T10

1

values[0x1]

all_enables

biggest_size

51382

1

T4

5

T7

2

T11

3