Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14416120

1

T1

13732

T2

1426

T4

14457

full_word

54796794

1

T1

137901

T2

6262

T3

4295

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69212634	1			T1	151633		T2	7688		T3	4295
auto[TlIntgErrCmd]	105	1			T66	3		T67	3		T68	4
auto[TlIntgErrData]	95	1			T66	9		T67	6		T68	3
auto[TlIntgErrBoth]	80	1			T66	8		T67	1		T68	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31751158

1

T1

76010

T2

3843

T3

2117

auto[1]

37461756

1

T1

75623

T2

3845

T3

2178

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6901541	1			T1	6913		T2	697		T4	5443
auto[TlIntgErrNone]	partial	auto[1]	7514320	1			T1	6819		T2	729		T4	9014
auto[TlIntgErrNone]	full_word	auto[0]	24849495	1			T1	69097		T2	3146		T3	2117
auto[TlIntgErrNone]	full_word	auto[1]	29947278	1			T1	68804		T2	3116		T3	2178
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T67	2		T68	1		T130	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T66	2		T68	3		T130	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T138	1		T139	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T66	1		T67	1		T140	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T66	6		T67	2		T68	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T66	3		T67	3		T68	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T134	1		T141	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T67	1		T130	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T66	1		T67	1		T68	2
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T66	6		T68	1		T130	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T137	1		T140	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T66	1		T131	1		T142	1