Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	738526	1			T4	897		T11	2831		T9	33
auto[1]	11210026	1			T1	63909		T2	3843		T3	2115
auto[2]	617683	1			T4	580		T11	2558		T9	34
auto[3]	11096703	1			T1	63450		T2	3844		T3	2177

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15164381	1			T1	105297		T2	5094		T3	4292
auto[1]	2262837	1			T1	10534		T2	1168		T4	209
auto[2]	2275598	1			T1	10465		T2	1157		T4	277
auto[3]	3960122	1			T1	1063		T2	268		T4	29

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9547593

1

T1

40

T2

7681

T3

4291

auto[1]

14115345

1

T1

127319

T2

6

T3

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	263554	1			T4	757		T11	2341		T9	28
auto[0]	auto[0]	auto[1]	27491	1			T4	59		T11	225		T9	1
auto[0]	auto[0]	auto[2]	27159	1			T4	73		T11	232		T9	4
auto[0]	auto[0]	auto[3]	9034	1			T4	8		T11	29		T43	11
auto[0]	auto[1]	auto[0]	3685929	1			T1	13		T2	2578		T3	2114
auto[0]	auto[1]	auto[1]	366915	1			T1	2		T2	566		T4	81
auto[0]	auto[1]	auto[2]	367141	1			T1	3		T2	556		T4	43
auto[0]	auto[1]	auto[3]	66331	1			T2	140		T4	5		T7	3
auto[0]	auto[2]	auto[0]	231159	1			T4	438		T11	2152		T9	29
auto[0]	auto[2]	auto[1]	23928	1			T4	54		T11	220		T9	4
auto[0]	auto[2]	auto[2]	24283	1			T4	78		T11	157		T9	1
auto[0]	auto[2]	auto[3]	7601	1			T4	9		T11	22		T43	5
auto[0]	auto[3]	auto[0]	3651371	1			T1	18		T2	2512		T3	2177
auto[0]	auto[3]	auto[1]	363393	1			T1	1		T2	601		T4	15
auto[0]	auto[3]	auto[2]	365589	1			T1	2		T2	601		T4	82
auto[0]	auto[3]	auto[3]	66715	1			T1	1		T2	127		T4	7
auto[1]	auto[0]	auto[0]	13902	1			T11	4		T43	1		T96	5
auto[1]	auto[0]	auto[1]	60971	1			T43	1		T149	1		T55	2784
auto[1]	auto[0]	auto[2]	61204	1			T96	1		T55	2779		T113	2097
auto[1]	auto[0]	auto[3]	275211	1			T150	1		T55	12708		T113	9760
auto[1]	auto[1]	auto[0]	3653880	1			T1	52714		T2	2		T3	1
auto[1]	auto[1]	auto[1]	706462	1			T1	5337		T11	1		T38	1
auto[1]	auto[1]	auto[2]	684094	1			T1	5313		T39	6767		T40	2
auto[1]	auto[1]	auto[3]	1679274	1			T1	527		T2	1		T39	600
auto[1]	auto[2]	auto[0]	10200	1			T11	5		T43	1		T96	3
auto[1]	auto[2]	auto[1]	45110	1			T11	1		T96	1		T55	2619
auto[1]	auto[2]	auto[2]	50376	1			T4	1		T11	1		T55	1877
auto[1]	auto[2]	auto[3]	225026	1			T55	8544		T113	9154		T148	18030
auto[1]	auto[3]	auto[0]	3654386	1			T1	52552		T2	2		T5	3
auto[1]	auto[3]	auto[1]	668567	1			T1	5194		T2	1		T39	6836
auto[1]	auto[3]	auto[2]	695752	1			T1	5147		T39	6236		T40	1
auto[1]	auto[3]	auto[3]	1630930	1			T1	535		T39	616		T82	440