Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	310153773	214876	0	0
ctrl_regwen_rd_A	310153773	3907	0	0
exec_rd_A	310153773	3431	0	0
exec_regwen_rd_A	310153773	3620	0	0
readback_rd_A	310153773	2451	0	0
readback_regwen_rd_A	310153773	2134	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310153773	214876	0	0
T18	110669	4166	0	0
T19	0	6481	0	0
T23	0	4162	0	0
T24	0	1004	0	0
T25	2063	0	0	0
T43	117275	0	0	0
T50	0	2315	0	0
T54	0	3536	0	0
T63	0	10122	0	0
T75	0	2635	0	0
T76	0	4122	0	0
T77	0	3230	0	0
T78	376662	0	0	0
T79	39495	0	0	0
T80	4887	0	0	0
T81	133911	0	0	0
T82	131372	0	0	0
T83	14771	0	0	0
T84	260739	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310153773	3907	0	0
T19	117498	0	0	0
T20	773685	0	0	0
T24	21083	118	0	0
T47	0	475	0	0
T48	0	277	0	0
T53	17402	0	0	0
T77	0	140	0	0
T117	0	115	0	0
T118	0	317	0	0
T119	0	283	0	0
T120	0	269	0	0
T121	0	110	0	0
T122	0	251	0	0
T123	7261	0	0	0
T124	19369	0	0	0
T125	310279	0	0	0
T126	55113	0	0	0
T127	5586	0	0	0
T128	168510	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310153773	3431	0	0
T19	117498	0	0	0
T20	773685	0	0	0
T24	21083	55	0	0
T47	0	425	0	0
T48	0	312	0	0
T53	17402	0	0	0
T77	0	101	0	0
T117	0	81	0	0
T118	0	208	0	0
T119	0	218	0	0
T120	0	289	0	0
T121	0	117	0	0
T122	0	102	0	0
T123	7261	0	0	0
T124	19369	0	0	0
T125	310279	0	0	0
T126	55113	0	0	0
T127	5586	0	0	0
T128	168510	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310153773	3620	0	0
T19	117498	0	0	0
T20	773685	0	0	0
T24	21083	78	0	0
T47	0	470	0	0
T48	0	263	0	0
T53	17402	0	0	0
T77	0	112	0	0
T117	0	73	0	0
T118	0	299	0	0
T119	0	277	0	0
T120	0	286	0	0
T121	0	92	0	0
T122	0	163	0	0
T123	7261	0	0	0
T124	19369	0	0	0
T125	310279	0	0	0
T126	55113	0	0	0
T127	5586	0	0	0
T128	168510	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310153773	2451	0	0
T19	117498	0	0	0
T20	773685	0	0	0
T24	21083	119	0	0
T47	0	473	0	0
T48	0	301	0	0
T53	17402	0	0	0
T77	0	119	0	0
T117	0	82	0	0
T118	0	234	0	0
T119	0	296	0	0
T120	0	255	0	0
T121	0	126	0	0
T122	0	139	0	0
T123	7261	0	0	0
T124	19369	0	0	0
T125	310279	0	0	0
T126	55113	0	0	0
T127	5586	0	0	0
T128	168510	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310153773	2134	0	0
T19	117498	0	0	0
T20	773685	0	0	0
T24	21083	71	0	0
T47	0	373	0	0
T48	0	241	0	0
T53	17402	0	0	0
T77	0	117	0	0
T117	0	81	0	0
T118	0	152	0	0
T119	0	344	0	0
T120	0	320	0	0
T121	0	70	0	0
T122	0	136	0	0
T123	7261	0	0	0
T124	19369	0	0	0
T125	310279	0	0	0
T126	55113	0	0	0
T127	5586	0	0	0
T128	168510	0	0	0