Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13644085	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57018749

1

T1

43267

T2

6142

T3

74596

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35226638	1			T1	21764		T2	2048		T3	41204
values[0x0]	16355892	1			T1	12146		T2	1999		T3	19796
values[0x1]	19080304	1			T1	12856		T2	2095		T3	21129

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6802392	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63860442

1

T1

45037

T2

6142

T3

78376

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	298096	1			T5	12		T10	2		T4	531
valid_sources[0x01]	268523	1			T3	247		T5	4		T10	2
valid_sources[0x02]	252595	1			T5	5		T10	2		T4	521
valid_sources[0x03]	259269	1			T3	228		T5	6		T4	530
valid_sources[0x04]	285749	1			T3	716		T5	4		T4	546
valid_sources[0x05]	280472	1			T3	523		T5	11		T10	11
valid_sources[0x06]	271766	1			T3	575		T5	2		T10	11
valid_sources[0x07]	252323	1			T3	360		T5	3		T10	3
valid_sources[0x08]	285450	1			T3	296		T5	11		T10	2
valid_sources[0x09]	271207	1			T3	182		T5	6		T10	2
valid_sources[0x0a]	277574	1			T3	330		T5	2		T4	538
valid_sources[0x0b]	275276	1			T3	111		T5	1		T10	10
valid_sources[0x0c]	272703	1			T3	482		T5	7		T4	506
valid_sources[0x0d]	266053	1			T3	480		T5	8		T10	7
valid_sources[0x0e]	286640	1			T3	261		T5	9		T10	5
valid_sources[0x0f]	258598	1			T3	82		T5	11		T10	7
valid_sources[0x10]	287617	1			T3	137		T5	7		T10	1
valid_sources[0x11]	267469	1			T3	29		T5	2		T10	9
valid_sources[0x12]	254300	1			T3	449		T5	1		T10	9
valid_sources[0x13]	245574	1			T1	141		T5	3		T10	6
valid_sources[0x14]	251883	1			T3	614		T5	11		T10	5
valid_sources[0x15]	280957	1			T3	94		T5	7		T4	534
valid_sources[0x16]	278621	1			T5	11		T10	4		T4	531
valid_sources[0x17]	290932	1			T3	668		T5	2		T10	4
valid_sources[0x18]	272727	1			T3	858		T5	4		T4	552
valid_sources[0x19]	258349	1			T1	9		T3	223		T5	2
valid_sources[0x1a]	267216	1			T3	381		T5	11		T4	583
valid_sources[0x1b]	257687	1			T3	31		T5	2		T10	9
valid_sources[0x1c]	263733	1			T3	153		T5	13		T10	1
valid_sources[0x1d]	276125	1			T3	189		T5	15		T4	571
valid_sources[0x1e]	306781	1			T3	66		T10	3		T4	556
valid_sources[0x1f]	253981	1			T3	204		T5	7		T10	4
valid_sources[0x20]	277492	1			T3	125		T5	20		T10	1
valid_sources[0x21]	244585	1			T3	518		T5	1		T10	6
valid_sources[0x22]	274347	1			T3	141		T5	7		T10	3
valid_sources[0x23]	336213	1			T3	190		T5	5		T4	552
valid_sources[0x24]	280753	1			T3	680		T5	15		T10	1
valid_sources[0x25]	270664	1			T3	78		T5	9		T10	2
valid_sources[0x26]	254182	1			T3	729		T5	8		T10	9
valid_sources[0x27]	259436	1			T3	273		T5	26		T10	6
valid_sources[0x28]	281815	1			T3	47		T5	1		T10	13
valid_sources[0x29]	260038	1			T3	324		T5	8		T10	6
valid_sources[0x2a]	327368	1			T1	887		T10	5		T4	549
valid_sources[0x2b]	308630	1			T3	683		T5	6		T10	4
valid_sources[0x2c]	354528	1			T3	44		T5	9		T10	2
valid_sources[0x2d]	256149	1			T1	876		T3	345		T5	19
valid_sources[0x2e]	252739	1			T2	6142		T3	172		T5	6
valid_sources[0x2f]	295856	1			T1	114		T3	234		T5	2
valid_sources[0x30]	310275	1			T3	394		T5	7		T10	7
valid_sources[0x31]	266120	1			T5	5		T4	523		T12	990
valid_sources[0x32]	248272	1			T10	21		T4	542		T12	961
valid_sources[0x33]	322032	1			T3	288		T5	9		T10	5
valid_sources[0x34]	276111	1			T3	393		T5	5		T10	4
valid_sources[0x35]	272522	1			T3	6		T5	2		T10	10
valid_sources[0x36]	274928	1			T3	103		T5	16		T10	1
valid_sources[0x37]	255627	1			T3	417		T5	10		T10	3
valid_sources[0x38]	288760	1			T3	189		T5	8		T10	1
valid_sources[0x39]	259849	1			T3	31		T5	10		T10	1
valid_sources[0x3a]	273383	1			T1	13		T3	653		T5	6
valid_sources[0x3b]	277608	1			T3	714		T5	11		T4	556
valid_sources[0x3c]	252769	1			T3	52		T5	3		T4	523
valid_sources[0x3d]	333837	1			T3	574		T5	6		T4	541
valid_sources[0x3e]	306980	1			T1	458		T5	9		T10	3
valid_sources[0x3f]	252557	1			T3	483		T5	16		T10	4
valid_sources[0x40]	255491	1			T3	152		T5	3		T10	5
valid_sources[0x41]	245073	1			T3	206		T5	4		T10	1
valid_sources[0x42]	254184	1			T3	75		T5	5		T10	11
valid_sources[0x43]	320385	1			T5	4		T10	2		T4	524
valid_sources[0x44]	297519	1			T3	259		T5	8		T10	14
valid_sources[0x45]	324170	1			T3	686		T5	7		T10	2
valid_sources[0x46]	261040	1			T3	433		T5	6		T10	3
valid_sources[0x47]	284077	1			T3	1		T5	9		T4	566
valid_sources[0x48]	256513	1			T3	63		T5	3		T10	16
valid_sources[0x49]	304878	1			T3	719		T5	10		T10	3
valid_sources[0x4a]	258055	1			T3	145		T5	5		T10	6
valid_sources[0x4b]	246227	1			T3	224		T5	10		T10	2
valid_sources[0x4c]	250639	1			T3	148		T5	7		T10	24
valid_sources[0x4d]	298805	1			T3	1		T5	2		T10	6
valid_sources[0x4e]	298050	1			T5	10		T10	2		T4	549
valid_sources[0x4f]	253881	1			T3	96		T5	1		T10	1
valid_sources[0x50]	264426	1			T3	283		T5	5		T10	7
valid_sources[0x51]	249718	1			T3	56		T5	11		T10	8
valid_sources[0x52]	250232	1			T3	809		T5	5		T10	2
valid_sources[0x53]	263477	1			T5	5		T10	3		T4	589
valid_sources[0x54]	260265	1			T3	344		T5	3		T10	7
valid_sources[0x55]	271187	1			T3	14		T5	4		T10	4
valid_sources[0x56]	253138	1			T3	518		T5	7		T10	4
valid_sources[0x57]	318443	1			T5	3		T4	537		T12	1003
valid_sources[0x58]	273460	1			T3	163		T5	17		T10	3
valid_sources[0x59]	244330	1			T3	129		T5	11		T10	6
valid_sources[0x5a]	254654	1			T1	269		T3	264		T5	5
valid_sources[0x5b]	255450	1			T3	244		T5	2		T10	2
valid_sources[0x5c]	319775	1			T1	115		T3	341		T5	21
valid_sources[0x5d]	369775	1			T3	2560		T5	5		T10	2
valid_sources[0x5e]	271210	1			T3	547		T5	12		T4	590
valid_sources[0x5f]	283556	1			T3	439		T5	15		T4	576
valid_sources[0x60]	254041	1			T3	456		T5	9		T10	2
valid_sources[0x61]	314288	1			T5	5		T10	7		T4	523
valid_sources[0x62]	280840	1			T3	486		T5	5		T10	3
valid_sources[0x63]	248324	1			T3	694		T5	15		T4	569
valid_sources[0x64]	265138	1			T3	341		T5	4		T10	8
valid_sources[0x65]	280500	1			T1	118		T3	167		T5	7
valid_sources[0x66]	262497	1			T3	123		T5	7		T10	10
valid_sources[0x67]	275980	1			T3	1195		T5	3		T10	9
valid_sources[0x68]	261993	1			T3	940		T5	15		T10	3
valid_sources[0x69]	296665	1			T3	167		T5	7		T10	5
valid_sources[0x6a]	289964	1			T3	764		T5	3		T10	1
valid_sources[0x6b]	282311	1			T3	394		T5	3		T10	1
valid_sources[0x6c]	256556	1			T1	3029		T3	174		T5	8
valid_sources[0x6d]	307728	1			T3	628		T5	7		T10	2
valid_sources[0x6e]	276444	1			T3	35		T5	6		T10	3
valid_sources[0x6f]	270716	1			T5	6		T10	11		T4	539
valid_sources[0x70]	282652	1			T1	1541		T3	433		T5	8
valid_sources[0x71]	271079	1			T3	21		T5	8		T10	2
valid_sources[0x72]	297424	1			T3	285		T5	28		T10	7
valid_sources[0x73]	245294	1			T3	757		T5	3		T10	1
valid_sources[0x74]	249266	1			T5	9		T4	557		T12	886
valid_sources[0x75]	262309	1			T3	626		T5	8		T10	5
valid_sources[0x76]	314946	1			T3	482		T10	3		T4	534
valid_sources[0x77]	251319	1			T3	40		T5	8		T10	6
valid_sources[0x78]	247343	1			T3	146		T5	1		T10	5
valid_sources[0x79]	289845	1			T3	159		T5	12		T10	12
valid_sources[0x7a]	263416	1			T3	1		T5	5		T4	548
valid_sources[0x7b]	354280	1			T3	131		T5	7		T10	6
valid_sources[0x7c]	280752	1			T3	110		T5	3		T10	7
valid_sources[0x7d]	256130	1			T3	1		T5	10		T10	6
valid_sources[0x7e]	253946	1			T3	865		T5	3		T10	2
valid_sources[0x7f]	330141	1			T3	318		T5	8		T10	2
valid_sources[0x80]	323301	1			T3	2195		T5	11		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28407145

1

T1

20013

T2

2048

T3

37453

values[0x0]

all_enables

biggest_size

14306980

1

T1

11600

T2

1999

T3

18653

values[0x1]

all_enables

biggest_size

14304624

1

T1

11654

T2

2095

T3

18490

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34385	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123934

1

T1

3196

T2

3

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46193	1			T1	933		T13	19		T6	22
values[0x0]	53969	1			T1	1209		T2	4		T3	7
values[0x1]	58157	1			T1	1358		T2	5		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

132199

1

T1

3313

T2

4

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	767	1			T38	4		T21	1		T26	5
valid_sources[0x01]	562	1			T1	20		T127	2		T21	1
valid_sources[0x02]	458	1			T6	4		T25	12		T26	2
valid_sources[0x03]	765	1			T1	144		T25	19		T43	1
valid_sources[0x04]	620	1			T8	1		T25	11		T108	1
valid_sources[0x05]	481	1			T1	6		T8	1		T25	17
valid_sources[0x06]	888	1			T25	3		T108	1		T26	10
valid_sources[0x07]	489	1			T25	5		T21	1		T26	3
valid_sources[0x08]	552	1			T1	3		T26	27		T123	2
valid_sources[0x09]	545	1			T1	3		T25	86		T21	1
valid_sources[0x0a]	497	1			T14	3		T21	1		T51	27
valid_sources[0x0b]	535	1			T25	3		T26	25		T17	2
valid_sources[0x0c]	464	1			T31	1		T25	2		T21	1
valid_sources[0x0d]	751	1			T25	1		T26	12		T50	1
valid_sources[0x0e]	607	1			T1	3		T15	1		T108	1
valid_sources[0x0f]	552	1			T4	1		T108	1		T26	2
valid_sources[0x10]	752	1			T1	4		T8	1		T21	1
valid_sources[0x11]	903	1			T10	2		T15	1		T108	1
valid_sources[0x12]	735	1			T5	1		T25	35		T26	3
valid_sources[0x13]	612	1			T13	104		T25	118		T21	3
valid_sources[0x14]	890	1			T31	1		T8	1		T26	8
valid_sources[0x15]	452	1			T7	1		T108	1		T26	3
valid_sources[0x16]	703	1			T1	145		T36	2		T26	20
valid_sources[0x17]	426	1			T1	28		T25	2		T21	1
valid_sources[0x18]	477	1			T1	6		T26	3		T44	1
valid_sources[0x19]	455	1			T4	2		T26	1		T17	1
valid_sources[0x1a]	579	1			T46	2		T128	1		T51	11
valid_sources[0x1b]	491	1			T25	2		T26	1		T46	3
valid_sources[0x1c]	447	1			T8	1		T25	41		T21	1
valid_sources[0x1d]	786	1			T14	1		T15	1		T47	2
valid_sources[0x1e]	659	1			T1	112		T37	2		T26	12
valid_sources[0x1f]	397	1			T26	7		T50	2		T46	4
valid_sources[0x20]	415	1			T6	3		T26	13		T46	1
valid_sources[0x21]	667	1			T14	2		T8	1		T25	56
valid_sources[0x22]	710	1			T1	8		T7	1		T26	9
valid_sources[0x23]	542	1			T14	2		T34	1		T26	4
valid_sources[0x24]	452	1			T1	1		T4	1		T21	1
valid_sources[0x25]	403	1			T15	1		T32	1		T26	17
valid_sources[0x26]	722	1			T1	2		T15	1		T108	1
valid_sources[0x27]	830	1			T1	6		T25	1		T108	2
valid_sources[0x28]	551	1			T26	13		T50	1		T51	16
valid_sources[0x29]	428	1			T6	1		T108	1		T26	9
valid_sources[0x2a]	582	1			T7	1		T95	1		T106	1
valid_sources[0x2b]	917	1			T7	1		T36	2		T25	10
valid_sources[0x2c]	582	1			T1	1		T14	2		T32	1
valid_sources[0x2d]	494	1			T108	2		T21	1		T26	4
valid_sources[0x2e]	678	1			T1	5		T14	2		T25	56
valid_sources[0x2f]	500	1			T1	82		T26	5		T50	5
valid_sources[0x30]	457	1			T4	1		T26	5		T46	5
valid_sources[0x31]	422	1			T25	2		T108	1		T26	18
valid_sources[0x32]	570	1			T8	1		T25	1		T26	5
valid_sources[0x33]	642	1			T1	112		T8	1		T21	2
valid_sources[0x34]	522	1			T129	23		T25	19		T26	3
valid_sources[0x35]	678	1			T1	2		T26	3		T46	139
valid_sources[0x36]	511	1			T1	1		T37	1		T26	3
valid_sources[0x37]	762	1			T4	1		T21	1		T26	2
valid_sources[0x38]	571	1			T8	1		T21	2		T26	14
valid_sources[0x39]	749	1			T25	3		T21	1		T26	8
valid_sources[0x3a]	636	1			T1	1		T21	1		T26	2
valid_sources[0x3b]	657	1			T8	1		T26	19		T123	1
valid_sources[0x3c]	621	1			T37	1		T25	24		T26	3
valid_sources[0x3d]	530	1			T4	1		T6	1		T25	48
valid_sources[0x3e]	731	1			T7	1		T25	3		T26	14
valid_sources[0x3f]	703	1			T25	57		T21	3		T26	8
valid_sources[0x40]	487	1			T51	10		T59	13		T52	15
valid_sources[0x41]	712	1			T1	126		T8	1		T108	1
valid_sources[0x42]	661	1			T26	1		T50	1		T51	7
valid_sources[0x43]	484	1			T8	1		T26	7		T46	3
valid_sources[0x44]	594	1			T1	1		T6	2		T8	1
valid_sources[0x45]	617	1			T25	13		T26	16		T50	2
valid_sources[0x46]	767	1			T1	1		T4	2		T25	30
valid_sources[0x47]	523	1			T1	2		T25	3		T26	6
valid_sources[0x48]	676	1			T21	1		T26	11		T51	14
valid_sources[0x49]	480	1			T6	1		T25	1		T47	1
valid_sources[0x4a]	566	1			T1	57		T4	1		T33	2
valid_sources[0x4b]	489	1			T25	2		T108	1		T26	12
valid_sources[0x4c]	549	1			T8	1		T21	1		T26	17
valid_sources[0x4d]	416	1			T1	2		T37	1		T21	1
valid_sources[0x4e]	566	1			T1	1		T130	7		T25	1
valid_sources[0x4f]	605	1			T1	1		T37	1		T7	1
valid_sources[0x50]	509	1			T108	1		T26	11		T123	1
valid_sources[0x51]	689	1			T1	177		T25	2		T47	1
valid_sources[0x52]	811	1			T130	5		T26	11		T17	1
valid_sources[0x53]	485	1			T8	1		T25	3		T21	1
valid_sources[0x54]	529	1			T4	1		T25	1		T21	2
valid_sources[0x55]	503	1			T28	1		T25	3		T26	5
valid_sources[0x56]	494	1			T1	1		T25	80		T21	1
valid_sources[0x57]	502	1			T21	2		T26	5		T50	1
valid_sources[0x58]	525	1			T1	2		T131	1		T96	1
valid_sources[0x59]	670	1			T47	1		T26	12		T50	98
valid_sources[0x5a]	783	1			T37	1		T8	2		T21	1
valid_sources[0x5b]	634	1			T20	89		T26	3		T50	1
valid_sources[0x5c]	611	1			T25	1		T26	13		T50	1
valid_sources[0x5d]	558	1			T1	5		T8	1		T21	1
valid_sources[0x5e]	538	1			T1	3		T7	1		T48	1
valid_sources[0x5f]	483	1			T6	3		T130	5		T25	52
valid_sources[0x60]	1025	1			T1	5		T25	27		T131	1
valid_sources[0x61]	567	1			T1	3		T4	1		T14	2
valid_sources[0x62]	589	1			T1	1		T25	4		T21	1
valid_sources[0x63]	665	1			T5	2		T8	1		T25	1
valid_sources[0x64]	626	1			T21	1		T26	3		T50	146
valid_sources[0x65]	660	1			T1	1		T6	2		T25	34
valid_sources[0x66]	426	1			T25	3		T26	8		T123	1
valid_sources[0x67]	459	1			T37	1		T36	1		T21	1
valid_sources[0x68]	595	1			T6	3		T21	2		T26	7
valid_sources[0x69]	744	1			T26	6		T46	1		T51	18
valid_sources[0x6a]	519	1			T43	2		T26	6		T51	14
valid_sources[0x6b]	980	1			T15	1		T25	113		T108	1
valid_sources[0x6c]	761	1			T4	1		T26	2		T123	1
valid_sources[0x6d]	577	1			T108	1		T123	1		T46	4
valid_sources[0x6e]	522	1			T4	1		T108	1		T21	2
valid_sources[0x6f]	425	1			T8	2		T26	7		T50	2
valid_sources[0x70]	568	1			T1	105		T8	1		T21	1
valid_sources[0x71]	636	1			T1	15		T15	1		T132	1
valid_sources[0x72]	757	1			T1	1		T15	1		T25	1
valid_sources[0x73]	750	1			T21	1		T26	7		T51	11
valid_sources[0x74]	595	1			T1	3		T133	1		T50	103
valid_sources[0x75]	447	1			T26	3		T51	24		T59	10
valid_sources[0x76]	976	1			T1	88		T25	2		T21	1
valid_sources[0x77]	758	1			T1	18		T132	1		T26	11
valid_sources[0x78]	640	1			T1	32		T25	32		T26	3
valid_sources[0x79]	465	1			T1	2		T6	1		T25	1
valid_sources[0x7a]	866	1			T1	205		T25	1		T46	2
valid_sources[0x7b]	735	1			T6	2		T78	2		T26	11
valid_sources[0x7c]	605	1			T6	1		T8	1		T21	1
valid_sources[0x7d]	908	1			T46	147		T51	11		T134	2
valid_sources[0x7e]	730	1			T1	2		T25	25		T26	6
valid_sources[0x7f]	716	1			T4	2		T25	32		T21	1
valid_sources[0x80]	701	1			T14	5		T21	1		T26	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

34148

1

T1

856

T13

9

T6

11

values[0x0]

all_enables

biggest_size

45846

1

T1

1161

T2

1

T3

1

values[0x1]

all_enables

biggest_size

43940

1

T1

1179

T2

2

T3

2