Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13351047

1

T1

7290

T3

6066

T5

1861

full_word

52372591

1

T1

39945

T2

6142

T3

59757

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65723398	1			T1	47235		T2	6142		T3	65823
auto[TlIntgErrCmd]	84	1			T53	10		T54	3		T55	4
auto[TlIntgErrData]	75	1			T53	6		T54	4		T55	4
auto[TlIntgErrBoth]	81	1			T53	4		T54	3		T55	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30234128

1

T1

18483

T2

2048

T3

24898

auto[1]

35489510

1

T1

28752

T2

4094

T3

40925

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6396498	1			T1	2199		T3	2284		T5	853
auto[TlIntgErrNone]	partial	auto[1]	6954333	1			T1	5091		T3	3782		T5	1008
auto[TlIntgErrNone]	full_word	auto[0]	23837523	1			T1	16284		T2	2048		T3	22614
auto[TlIntgErrNone]	full_word	auto[1]	28535044	1			T1	23661		T2	4094		T3	37143
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T53	3		T54	2		T55	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T53	7		T54	1		T55	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T115	1		T120	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T55	1		T118	1		T121	2
auto[TlIntgErrData]	partial	auto[0]	33	1			T53	2		T54	2		T55	1
auto[TlIntgErrData]	partial	auto[1]	32	1			T53	4		T54	2		T55	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T116	2		T120	1		T118	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T55	1		T117	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T53	1		T54	1		T55	2
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T53	3		T54	2		T110	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T119	1		T122	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T111	1		T112	1		T120	2