Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	701052	1			T3	24		T4	897		T13	36
auto[1]	10391714	1			T1	3264		T3	290		T5	762
auto[2]	568018	1			T3	29		T4	566		T13	48
auto[3]	10263180	1			T1	3211		T3	266		T5	987

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14144285	1			T1	5373		T3	441		T5	13
auto[1]	2088155	1			T1	514		T3	50		T5	104
auto[2]	2111809	1			T1	549		T3	105		T5	171
auto[3]	3579715	1			T1	39		T3	13		T5	1461

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8370418

1

T1

6469

T3

609

T5

1746

auto[1]

13553546

1

T1

6

T5

3

T4

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	268638	1			T3	23		T4	747		T13	28
auto[0]	auto[0]	auto[1]	27484	1			T4	79		T13	3		T14	71
auto[0]	auto[0]	auto[2]	27737	1			T3	1		T4	65		T13	5
auto[0]	auto[0]	auto[3]	9129	1			T4	4		T14	4		T38	254
auto[0]	auto[1]	auto[0]	3196434	1			T1	2687		T3	231		T5	1
auto[0]	auto[1]	auto[1]	325279	1			T1	257		T3	32		T5	7
auto[0]	auto[1]	auto[2]	321484	1			T1	291		T3	24		T5	91
auto[0]	auto[1]	auto[3]	65722	1			T1	26		T3	3		T5	662
auto[0]	auto[2]	auto[0]	219057	1			T4	436		T14	462		T108	1825
auto[0]	auto[2]	auto[1]	22599	1			T4	48		T14	42		T38	17
auto[0]	auto[2]	auto[2]	26934	1			T3	26		T4	75		T13	44
auto[0]	auto[2]	auto[3]	7815	1			T3	3		T4	7		T13	4
auto[0]	auto[3]	auto[0]	3143456	1			T1	2680		T3	187		T5	12
auto[0]	auto[3]	auto[1]	314831	1			T1	257		T3	18		T5	97
auto[0]	auto[3]	auto[2]	326972	1			T1	258		T3	54		T5	80
auto[0]	auto[3]	auto[3]	66847	1			T1	13		T3	7		T5	796
auto[1]	auto[0]	auto[0]	12493	1			T4	1		T36	127		T94	154
auto[1]	auto[0]	auto[1]	54732	1			T4	1		T36	569		T94	726
auto[1]	auto[0]	auto[2]	54682	1			T14	1		T36	573		T94	777
auto[1]	auto[0]	auto[3]	246157	1			T36	2501		T94	3444		T96	4376
auto[1]	auto[1]	auto[0]	3648405	1			T1	3		T12	3247		T14	1
auto[1]	auto[1]	auto[1]	669227	1			T12	15067		T37	1		T36	1953
auto[1]	auto[1]	auto[2]	649907	1			T12	15259		T37	4		T33	1
auto[1]	auto[1]	auto[3]	1515256	1			T5	1		T12	67983		T36	8781
auto[1]	auto[2]	auto[0]	9272	1			T14	1		T108	1		T96	138
auto[1]	auto[2]	auto[1]	40013	1			T108	1		T96	617		T125	3032
auto[1]	auto[2]	auto[2]	44130	1			T36	495		T94	663		T96	1053
auto[1]	auto[2]	auto[3]	198198	1			T36	2317		T94	3071		T96	4796
auto[1]	auto[3]	auto[0]	3646530	1			T1	3		T12	3469		T37	25
auto[1]	auto[3]	auto[1]	633990	1			T12	15066		T37	3		T33	2
auto[1]	auto[3]	auto[2]	659963	1			T12	15209		T33	1		T36	1919
auto[1]	auto[3]	auto[3]	1470591	1			T5	2		T12	68789		T37	1