Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	310928544	184593	0	0
ctrl_regwen_rd_A	310928544	3649	0	0
exec_rd_A	310928544	3495	0	0
exec_regwen_rd_A	310928544	3735	0	0
readback_rd_A	310928544	2577	0	0
readback_regwen_rd_A	310928544	2044	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310928544	184593	0	0
T1	102780	5156	0	0
T2	44094	0	0	0
T3	517526	0	0	0
T4	104136	0	0	0
T5	6797	0	0	0
T10	3940	0	0	0
T11	3004	0	0	0
T12	470688	0	0	0
T13	162260	0	0	0
T14	122194	0	0	0
T25	0	3436	0	0
T26	0	3212	0	0
T46	0	9532	0	0
T50	0	7094	0	0
T51	0	5924	0	0
T52	0	9179	0	0
T59	0	6206	0	0
T60	0	1233	0	0
T61	0	3538	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310928544	3649	0	0
T25	106524	151	0	0
T47	45324	0	0	0
T48	9183	0	0	0
T60	0	111	0	0
T78	4388	0	0	0
T94	160060	0	0	0
T95	185591	0	0	0
T97	0	65	0	0
T98	0	261	0	0
T99	0	44	0	0
T100	0	99	0	0
T101	0	351	0	0
T102	0	233	0	0
T103	0	198	0	0
T104	0	47	0	0
T105	13502	0	0	0
T106	2245	0	0	0
T107	29804	0	0	0
T108	182670	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310928544	3495	0	0
T25	106524	124	0	0
T47	45324	0	0	0
T48	9183	0	0	0
T60	0	119	0	0
T78	4388	0	0	0
T94	160060	0	0	0
T95	185591	0	0	0
T97	0	104	0	0
T98	0	259	0	0
T99	0	70	0	0
T100	0	142	0	0
T101	0	226	0	0
T102	0	163	0	0
T103	0	181	0	0
T104	0	67	0	0
T105	13502	0	0	0
T106	2245	0	0	0
T107	29804	0	0	0
T108	182670	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310928544	3735	0	0
T25	106524	148	0	0
T47	45324	0	0	0
T48	9183	0	0	0
T60	0	137	0	0
T78	4388	0	0	0
T94	160060	0	0	0
T95	185591	0	0	0
T97	0	97	0	0
T98	0	288	0	0
T99	0	50	0	0
T100	0	146	0	0
T101	0	255	0	0
T102	0	255	0	0
T103	0	227	0	0
T104	0	85	0	0
T105	13502	0	0	0
T106	2245	0	0	0
T107	29804	0	0	0
T108	182670	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310928544	2577	0	0
T25	106524	226	0	0
T47	45324	0	0	0
T48	9183	0	0	0
T60	0	75	0	0
T78	4388	0	0	0
T94	160060	0	0	0
T95	185591	0	0	0
T97	0	57	0	0
T98	0	218	0	0
T99	0	60	0	0
T100	0	102	0	0
T101	0	228	0	0
T102	0	225	0	0
T103	0	153	0	0
T104	0	67	0	0
T105	13502	0	0	0
T106	2245	0	0	0
T107	29804	0	0	0
T108	182670	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310928544	2044	0	0
T25	106524	74	0	0
T47	45324	0	0	0
T48	9183	0	0	0
T60	0	86	0	0
T78	4388	0	0	0
T94	160060	0	0	0
T95	185591	0	0	0
T97	0	34	0	0
T98	0	206	0	0
T99	0	54	0	0
T100	0	133	0	0
T101	0	202	0	0
T102	0	198	0	0
T103	0	131	0	0
T104	0	36	0	0
T105	13502	0	0	0
T106	2245	0	0	0
T107	29804	0	0	0
T108	182670	0	0	0