| T800 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3290915576 |
|
|
Jul 27 05:01:05 PM PDT 24 |
Jul 27 05:24:21 PM PDT 24 |
3063541238 ps |
| T801 |
/workspace/coverage/default/2.sram_ctrl_smoke.487733180 |
|
|
Jul 27 04:59:37 PM PDT 24 |
Jul 27 04:59:41 PM PDT 24 |
668848292 ps |
| T802 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1321145816 |
|
|
Jul 27 05:01:07 PM PDT 24 |
Jul 27 05:01:10 PM PDT 24 |
59176464 ps |
| T803 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2762931893 |
|
|
Jul 27 04:59:47 PM PDT 24 |
Jul 27 05:03:43 PM PDT 24 |
7980021928 ps |
| T804 |
/workspace/coverage/default/28.sram_ctrl_stress_all.2201157357 |
|
|
Jul 27 05:00:32 PM PDT 24 |
Jul 27 05:03:31 PM PDT 24 |
12295561756 ps |
| T805 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1948512003 |
|
|
Jul 27 05:00:06 PM PDT 24 |
Jul 27 05:00:07 PM PDT 24 |
14540214 ps |
| T806 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.874727632 |
|
|
Jul 27 05:01:48 PM PDT 24 |
Jul 27 05:11:08 PM PDT 24 |
1793277460 ps |
| T807 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3184667311 |
|
|
Jul 27 05:01:56 PM PDT 24 |
Jul 27 05:08:57 PM PDT 24 |
94621841724 ps |
| T808 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.4259404058 |
|
|
Jul 27 05:01:37 PM PDT 24 |
Jul 27 05:01:38 PM PDT 24 |
178396411 ps |
| T809 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.205402016 |
|
|
Jul 27 04:59:45 PM PDT 24 |
Jul 27 05:10:53 PM PDT 24 |
20123879879 ps |
| T810 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3869631223 |
|
|
Jul 27 04:59:46 PM PDT 24 |
Jul 27 04:59:52 PM PDT 24 |
88468301 ps |
| T811 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1902259818 |
|
|
Jul 27 05:01:06 PM PDT 24 |
Jul 27 05:01:09 PM PDT 24 |
185578290 ps |
| T812 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3996523395 |
|
|
Jul 27 05:00:11 PM PDT 24 |
Jul 27 05:04:58 PM PDT 24 |
5871658619 ps |
| T813 |
/workspace/coverage/default/18.sram_ctrl_regwen.269365572 |
|
|
Jul 27 05:00:18 PM PDT 24 |
Jul 27 05:16:07 PM PDT 24 |
71191733979 ps |
| T814 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2758154075 |
|
|
Jul 27 05:01:28 PM PDT 24 |
Jul 27 05:01:37 PM PDT 24 |
317135792 ps |
| T815 |
/workspace/coverage/default/45.sram_ctrl_partial_access.345858782 |
|
|
Jul 27 05:01:37 PM PDT 24 |
Jul 27 05:01:47 PM PDT 24 |
93290813 ps |
| T816 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1620185273 |
|
|
Jul 27 05:00:52 PM PDT 24 |
Jul 27 05:00:53 PM PDT 24 |
29052147 ps |
| T817 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.168416657 |
|
|
Jul 27 05:01:07 PM PDT 24 |
Jul 27 05:11:44 PM PDT 24 |
22705805440 ps |
| T818 |
/workspace/coverage/default/21.sram_ctrl_partial_access.3944808383 |
|
|
Jul 27 05:00:23 PM PDT 24 |
Jul 27 05:00:31 PM PDT 24 |
1027919335 ps |
| T819 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2194328015 |
|
|
Jul 27 05:00:58 PM PDT 24 |
Jul 27 05:26:20 PM PDT 24 |
14479953534 ps |
| T820 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.542609528 |
|
|
Jul 27 05:00:06 PM PDT 24 |
Jul 27 05:03:28 PM PDT 24 |
17173667114 ps |
| T821 |
/workspace/coverage/default/45.sram_ctrl_stress_all.371467706 |
|
|
Jul 27 05:01:36 PM PDT 24 |
Jul 27 06:39:54 PM PDT 24 |
58324365399 ps |
| T822 |
/workspace/coverage/default/16.sram_ctrl_bijection.3481206773 |
|
|
Jul 27 05:00:09 PM PDT 24 |
Jul 27 05:00:58 PM PDT 24 |
739671463 ps |
| T823 |
/workspace/coverage/default/35.sram_ctrl_smoke.292909581 |
|
|
Jul 27 05:00:51 PM PDT 24 |
Jul 27 05:00:53 PM PDT 24 |
52495539 ps |
| T824 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.3876090253 |
|
|
Jul 27 05:00:29 PM PDT 24 |
Jul 27 05:07:31 PM PDT 24 |
61090765416 ps |
| T825 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3960853910 |
|
|
Jul 27 05:01:02 PM PDT 24 |
Jul 27 05:01:08 PM PDT 24 |
334147727 ps |
| T826 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3919714658 |
|
|
Jul 27 05:01:30 PM PDT 24 |
Jul 27 05:02:59 PM PDT 24 |
250304604 ps |
| T827 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.4058051608 |
|
|
Jul 27 05:01:20 PM PDT 24 |
Jul 27 05:01:37 PM PDT 24 |
72626365 ps |
| T828 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.4041313622 |
|
|
Jul 27 05:01:01 PM PDT 24 |
Jul 27 05:03:05 PM PDT 24 |
275913624 ps |
| T829 |
/workspace/coverage/default/32.sram_ctrl_partial_access.286140730 |
|
|
Jul 27 05:01:01 PM PDT 24 |
Jul 27 05:01:16 PM PDT 24 |
7010144747 ps |
| T830 |
/workspace/coverage/default/16.sram_ctrl_smoke.3253602896 |
|
|
Jul 27 04:59:55 PM PDT 24 |
Jul 27 05:01:59 PM PDT 24 |
412810700 ps |
| T831 |
/workspace/coverage/default/31.sram_ctrl_smoke.3065395844 |
|
|
Jul 27 05:00:53 PM PDT 24 |
Jul 27 05:02:40 PM PDT 24 |
136716333 ps |
| T832 |
/workspace/coverage/default/12.sram_ctrl_partial_access.953204542 |
|
|
Jul 27 04:59:50 PM PDT 24 |
Jul 27 04:59:52 PM PDT 24 |
301769255 ps |
| T833 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3492892444 |
|
|
Jul 27 05:00:04 PM PDT 24 |
Jul 27 05:00:18 PM PDT 24 |
137720758 ps |
| T834 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.938293352 |
|
|
Jul 27 05:00:36 PM PDT 24 |
Jul 27 05:01:06 PM PDT 24 |
318092491 ps |
| T835 |
/workspace/coverage/default/15.sram_ctrl_bijection.1539964251 |
|
|
Jul 27 04:59:56 PM PDT 24 |
Jul 27 05:01:02 PM PDT 24 |
16210150802 ps |
| T836 |
/workspace/coverage/default/37.sram_ctrl_smoke.1313757182 |
|
|
Jul 27 05:00:57 PM PDT 24 |
Jul 27 05:01:06 PM PDT 24 |
2576319227 ps |
| T837 |
/workspace/coverage/default/4.sram_ctrl_bijection.2760870763 |
|
|
Jul 27 04:59:54 PM PDT 24 |
Jul 27 05:00:28 PM PDT 24 |
5813942871 ps |
| T838 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3644619598 |
|
|
Jul 27 05:00:31 PM PDT 24 |
Jul 27 05:00:37 PM PDT 24 |
347438077 ps |
| T42 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1265255251 |
|
|
Jul 27 05:01:58 PM PDT 24 |
Jul 27 05:03:07 PM PDT 24 |
1452098362 ps |
| T839 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3501233147 |
|
|
Jul 27 05:01:26 PM PDT 24 |
Jul 27 05:01:29 PM PDT 24 |
120569325 ps |
| T840 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3370454882 |
|
|
Jul 27 04:59:56 PM PDT 24 |
Jul 27 05:16:16 PM PDT 24 |
3316380808 ps |
| T841 |
/workspace/coverage/default/35.sram_ctrl_executable.1531341293 |
|
|
Jul 27 05:00:58 PM PDT 24 |
Jul 27 05:23:59 PM PDT 24 |
25313519650 ps |
| T842 |
/workspace/coverage/default/8.sram_ctrl_regwen.2565502543 |
|
|
Jul 27 04:59:48 PM PDT 24 |
Jul 27 05:07:02 PM PDT 24 |
32389490641 ps |
| T843 |
/workspace/coverage/default/21.sram_ctrl_smoke.3456582755 |
|
|
Jul 27 05:00:30 PM PDT 24 |
Jul 27 05:01:02 PM PDT 24 |
797112341 ps |
| T844 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.3080003076 |
|
|
Jul 27 05:01:06 PM PDT 24 |
Jul 27 05:01:13 PM PDT 24 |
4586742072 ps |
| T845 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.618140700 |
|
|
Jul 27 05:00:20 PM PDT 24 |
Jul 27 05:01:31 PM PDT 24 |
226354532 ps |
| T846 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3480133016 |
|
|
Jul 27 05:01:15 PM PDT 24 |
Jul 27 05:05:05 PM PDT 24 |
10596906453 ps |
| T847 |
/workspace/coverage/default/20.sram_ctrl_smoke.2306238939 |
|
|
Jul 27 05:00:17 PM PDT 24 |
Jul 27 05:00:28 PM PDT 24 |
488828037 ps |
| T848 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2997390019 |
|
|
Jul 27 05:01:31 PM PDT 24 |
Jul 27 05:02:15 PM PDT 24 |
377974874 ps |
| T849 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.783198046 |
|
|
Jul 27 05:00:39 PM PDT 24 |
Jul 27 05:03:30 PM PDT 24 |
2776525281 ps |
| T850 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.742493465 |
|
|
Jul 27 05:00:52 PM PDT 24 |
Jul 27 05:07:33 PM PDT 24 |
15279159409 ps |
| T851 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.26706855 |
|
|
Jul 27 05:01:50 PM PDT 24 |
Jul 27 05:08:04 PM PDT 24 |
1001182518 ps |
| T852 |
/workspace/coverage/default/49.sram_ctrl_alert_test.2883299130 |
|
|
Jul 27 05:01:56 PM PDT 24 |
Jul 27 05:01:57 PM PDT 24 |
20922021 ps |
| T853 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3145527483 |
|
|
Jul 27 05:01:48 PM PDT 24 |
Jul 27 05:54:30 PM PDT 24 |
221967290443 ps |
| T854 |
/workspace/coverage/default/47.sram_ctrl_bijection.384875923 |
|
|
Jul 27 05:01:50 PM PDT 24 |
Jul 27 05:02:08 PM PDT 24 |
6691305122 ps |
| T855 |
/workspace/coverage/default/40.sram_ctrl_bijection.321094862 |
|
|
Jul 27 05:01:20 PM PDT 24 |
Jul 27 05:02:33 PM PDT 24 |
13794300391 ps |
| T856 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2190254545 |
|
|
Jul 27 05:00:22 PM PDT 24 |
Jul 27 05:01:43 PM PDT 24 |
269957964 ps |
| T857 |
/workspace/coverage/default/21.sram_ctrl_stress_all.1900187923 |
|
|
Jul 27 05:00:17 PM PDT 24 |
Jul 27 06:06:56 PM PDT 24 |
54282806795 ps |
| T858 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.211940925 |
|
|
Jul 27 04:59:57 PM PDT 24 |
Jul 27 05:00:13 PM PDT 24 |
83488397 ps |
| T859 |
/workspace/coverage/default/17.sram_ctrl_partial_access.2538354478 |
|
|
Jul 27 05:00:27 PM PDT 24 |
Jul 27 05:00:40 PM PDT 24 |
634244318 ps |
| T860 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1547942893 |
|
|
Jul 27 05:00:24 PM PDT 24 |
Jul 27 05:00:30 PM PDT 24 |
668421925 ps |
| T861 |
/workspace/coverage/default/5.sram_ctrl_smoke.1042305351 |
|
|
Jul 27 04:59:48 PM PDT 24 |
Jul 27 04:59:59 PM PDT 24 |
875553780 ps |
| T862 |
/workspace/coverage/default/31.sram_ctrl_bijection.721068378 |
|
|
Jul 27 05:00:51 PM PDT 24 |
Jul 27 05:01:57 PM PDT 24 |
4099780162 ps |
| T863 |
/workspace/coverage/default/47.sram_ctrl_executable.846990903 |
|
|
Jul 27 05:01:51 PM PDT 24 |
Jul 27 05:02:46 PM PDT 24 |
4303162839 ps |
| T864 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.4282836315 |
|
|
Jul 27 05:00:28 PM PDT 24 |
Jul 27 05:00:31 PM PDT 24 |
48134483 ps |
| T865 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1761205397 |
|
|
Jul 27 05:00:58 PM PDT 24 |
Jul 27 05:03:56 PM PDT 24 |
7716149340 ps |
| T866 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2799440976 |
|
|
Jul 27 05:00:58 PM PDT 24 |
Jul 27 05:03:16 PM PDT 24 |
190085831 ps |
| T867 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3385486922 |
|
|
Jul 27 05:01:58 PM PDT 24 |
Jul 27 05:02:05 PM PDT 24 |
2766500704 ps |
| T868 |
/workspace/coverage/default/28.sram_ctrl_smoke.3543699727 |
|
|
Jul 27 05:00:29 PM PDT 24 |
Jul 27 05:00:42 PM PDT 24 |
59183072 ps |
| T869 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3998824360 |
|
|
Jul 27 05:00:55 PM PDT 24 |
Jul 27 05:45:41 PM PDT 24 |
53472916846 ps |
| T870 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2333969189 |
|
|
Jul 27 05:00:59 PM PDT 24 |
Jul 27 05:07:40 PM PDT 24 |
35963697226 ps |
| T871 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2039086257 |
|
|
Jul 27 05:00:54 PM PDT 24 |
Jul 27 05:10:20 PM PDT 24 |
4804372468 ps |
| T872 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3069803769 |
|
|
Jul 27 05:00:43 PM PDT 24 |
Jul 27 05:01:21 PM PDT 24 |
1940175751 ps |
| T873 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1941246121 |
|
|
Jul 27 05:01:08 PM PDT 24 |
Jul 27 05:28:22 PM PDT 24 |
23494566812 ps |
| T874 |
/workspace/coverage/default/39.sram_ctrl_bijection.3685562046 |
|
|
Jul 27 05:01:08 PM PDT 24 |
Jul 27 05:02:09 PM PDT 24 |
1961551757 ps |
| T875 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3909943703 |
|
|
Jul 27 05:00:32 PM PDT 24 |
Jul 27 05:00:37 PM PDT 24 |
293388399 ps |
| T876 |
/workspace/coverage/default/32.sram_ctrl_regwen.1352193895 |
|
|
Jul 27 05:00:37 PM PDT 24 |
Jul 27 05:04:43 PM PDT 24 |
1487323320 ps |
| T877 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3507086126 |
|
|
Jul 27 04:59:50 PM PDT 24 |
Jul 27 04:59:58 PM PDT 24 |
1277891693 ps |
| T878 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2755232294 |
|
|
Jul 27 05:01:00 PM PDT 24 |
Jul 27 05:04:00 PM PDT 24 |
1900262853 ps |
| T879 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.4003578626 |
|
|
Jul 27 05:00:58 PM PDT 24 |
Jul 27 05:04:40 PM PDT 24 |
4815218279 ps |
| T880 |
/workspace/coverage/default/46.sram_ctrl_smoke.2149224954 |
|
|
Jul 27 05:01:37 PM PDT 24 |
Jul 27 05:04:09 PM PDT 24 |
570997005 ps |
| T881 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.135232141 |
|
|
Jul 27 05:01:29 PM PDT 24 |
Jul 27 05:04:02 PM PDT 24 |
163484407 ps |
| T882 |
/workspace/coverage/default/12.sram_ctrl_executable.1246578175 |
|
|
Jul 27 05:00:14 PM PDT 24 |
Jul 27 05:07:18 PM PDT 24 |
12413120375 ps |
| T883 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3777737190 |
|
|
Jul 27 05:01:18 PM PDT 24 |
Jul 27 05:05:10 PM PDT 24 |
2460683890 ps |
| T884 |
/workspace/coverage/default/45.sram_ctrl_regwen.342926470 |
|
|
Jul 27 05:01:39 PM PDT 24 |
Jul 27 05:12:59 PM PDT 24 |
2416441196 ps |
| T885 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1165935840 |
|
|
Jul 27 05:00:12 PM PDT 24 |
Jul 27 05:10:31 PM PDT 24 |
2397669568 ps |
| T886 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.664585807 |
|
|
Jul 27 04:59:57 PM PDT 24 |
Jul 27 05:00:02 PM PDT 24 |
290400918 ps |
| T887 |
/workspace/coverage/default/41.sram_ctrl_smoke.2958567048 |
|
|
Jul 27 05:01:18 PM PDT 24 |
Jul 27 05:02:44 PM PDT 24 |
486998818 ps |
| T888 |
/workspace/coverage/default/38.sram_ctrl_smoke.3289729234 |
|
|
Jul 27 05:01:08 PM PDT 24 |
Jul 27 05:01:36 PM PDT 24 |
398677882 ps |
| T889 |
/workspace/coverage/default/33.sram_ctrl_partial_access.3528088024 |
|
|
Jul 27 05:00:56 PM PDT 24 |
Jul 27 05:01:35 PM PDT 24 |
153334699 ps |
| T890 |
/workspace/coverage/default/13.sram_ctrl_stress_all.413055282 |
|
|
Jul 27 05:00:05 PM PDT 24 |
Jul 27 05:15:20 PM PDT 24 |
36754558766 ps |
| T891 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1027523371 |
|
|
Jul 27 05:01:30 PM PDT 24 |
Jul 27 05:01:35 PM PDT 24 |
555454108 ps |
| T892 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.1782463828 |
|
|
Jul 27 05:00:04 PM PDT 24 |
Jul 27 05:00:17 PM PDT 24 |
2150620924 ps |
| T893 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3361362017 |
|
|
Jul 27 05:01:46 PM PDT 24 |
Jul 27 05:09:23 PM PDT 24 |
1420388495 ps |
| T894 |
/workspace/coverage/default/35.sram_ctrl_regwen.4015696798 |
|
|
Jul 27 05:01:02 PM PDT 24 |
Jul 27 05:23:28 PM PDT 24 |
43527505833 ps |
| T895 |
/workspace/coverage/default/34.sram_ctrl_bijection.2010308867 |
|
|
Jul 27 05:00:47 PM PDT 24 |
Jul 27 05:01:54 PM PDT 24 |
1722279638 ps |
| T896 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.635702802 |
|
|
Jul 27 05:01:35 PM PDT 24 |
Jul 27 05:04:52 PM PDT 24 |
1080201142 ps |
| T897 |
/workspace/coverage/default/40.sram_ctrl_smoke.139638797 |
|
|
Jul 27 05:01:18 PM PDT 24 |
Jul 27 05:01:33 PM PDT 24 |
686467042 ps |
| T898 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.4068548494 |
|
|
Jul 27 05:00:30 PM PDT 24 |
Jul 27 05:14:59 PM PDT 24 |
48774660880 ps |
| T899 |
/workspace/coverage/default/30.sram_ctrl_bijection.1605913908 |
|
|
Jul 27 05:00:44 PM PDT 24 |
Jul 27 05:01:51 PM PDT 24 |
1063828905 ps |
| T900 |
/workspace/coverage/default/32.sram_ctrl_alert_test.394225296 |
|
|
Jul 27 05:00:58 PM PDT 24 |
Jul 27 05:00:58 PM PDT 24 |
17152109 ps |
| T901 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.1790208740 |
|
|
Jul 27 05:00:28 PM PDT 24 |
Jul 27 05:00:29 PM PDT 24 |
29325457 ps |
| T902 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.3446587003 |
|
|
Jul 27 04:59:57 PM PDT 24 |
Jul 27 05:00:01 PM PDT 24 |
220060035 ps |
| T903 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1995440523 |
|
|
Jul 27 04:59:58 PM PDT 24 |
Jul 27 05:06:30 PM PDT 24 |
30653686154 ps |
| T904 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1295027759 |
|
|
Jul 27 04:59:55 PM PDT 24 |
Jul 27 05:00:01 PM PDT 24 |
603995313 ps |
| T905 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3495994577 |
|
|
Jul 27 05:01:45 PM PDT 24 |
Jul 27 05:17:50 PM PDT 24 |
14278902671 ps |
| T906 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1811395543 |
|
|
Jul 27 05:00:28 PM PDT 24 |
Jul 27 05:04:16 PM PDT 24 |
3614783784 ps |
| T907 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3910140158 |
|
|
Jul 27 05:01:19 PM PDT 24 |
Jul 27 05:02:58 PM PDT 24 |
613195276 ps |
| T908 |
/workspace/coverage/default/42.sram_ctrl_bijection.1592118185 |
|
|
Jul 27 05:01:17 PM PDT 24 |
Jul 27 05:02:16 PM PDT 24 |
911249579 ps |
| T909 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3056194230 |
|
|
Jul 27 05:00:27 PM PDT 24 |
Jul 27 05:00:33 PM PDT 24 |
1492992025 ps |
| T910 |
/workspace/coverage/default/5.sram_ctrl_executable.2874396011 |
|
|
Jul 27 04:59:49 PM PDT 24 |
Jul 27 05:07:17 PM PDT 24 |
59396566633 ps |
| T911 |
/workspace/coverage/default/27.sram_ctrl_alert_test.3501818220 |
|
|
Jul 27 05:00:39 PM PDT 24 |
Jul 27 05:00:40 PM PDT 24 |
14390648 ps |
| T912 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1831599966 |
|
|
Jul 27 05:01:39 PM PDT 24 |
Jul 27 05:02:06 PM PDT 24 |
102743973 ps |
| T913 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3897269439 |
|
|
Jul 27 05:01:00 PM PDT 24 |
Jul 27 05:06:03 PM PDT 24 |
4202043437 ps |
| T914 |
/workspace/coverage/default/32.sram_ctrl_bijection.831685318 |
|
|
Jul 27 05:00:47 PM PDT 24 |
Jul 27 05:01:57 PM PDT 24 |
5595224823 ps |
| T915 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2049711496 |
|
|
Jul 27 04:59:55 PM PDT 24 |
Jul 27 05:03:02 PM PDT 24 |
1403788286 ps |
| T916 |
/workspace/coverage/default/29.sram_ctrl_regwen.1801702825 |
|
|
Jul 27 05:00:40 PM PDT 24 |
Jul 27 05:09:03 PM PDT 24 |
10046646209 ps |
| T917 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2396074941 |
|
|
Jul 27 05:00:26 PM PDT 24 |
Jul 27 05:03:35 PM PDT 24 |
15644676019 ps |
| T918 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2687677170 |
|
|
Jul 27 04:59:40 PM PDT 24 |
Jul 27 04:59:45 PM PDT 24 |
97698444 ps |
| T919 |
/workspace/coverage/default/9.sram_ctrl_stress_all.2619047510 |
|
|
Jul 27 05:00:01 PM PDT 24 |
Jul 27 05:22:14 PM PDT 24 |
140745384880 ps |
| T920 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3912182868 |
|
|
Jul 27 05:00:06 PM PDT 24 |
Jul 27 05:00:12 PM PDT 24 |
209067180 ps |
| T921 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1158418076 |
|
|
Jul 27 05:00:39 PM PDT 24 |
Jul 27 05:00:40 PM PDT 24 |
26206463 ps |
| T922 |
/workspace/coverage/default/34.sram_ctrl_smoke.2732207082 |
|
|
Jul 27 05:00:55 PM PDT 24 |
Jul 27 05:01:05 PM PDT 24 |
6659868054 ps |
| T923 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.3673165941 |
|
|
Jul 27 05:01:09 PM PDT 24 |
Jul 27 05:01:18 PM PDT 24 |
658515809 ps |
| T924 |
/workspace/coverage/default/27.sram_ctrl_executable.1444910493 |
|
|
Jul 27 05:00:30 PM PDT 24 |
Jul 27 05:23:00 PM PDT 24 |
7289311262 ps |
| T925 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2722780050 |
|
|
Jul 27 05:00:31 PM PDT 24 |
Jul 27 05:00:32 PM PDT 24 |
28043310 ps |
| T926 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.71353731 |
|
|
Jul 27 04:59:59 PM PDT 24 |
Jul 27 05:15:16 PM PDT 24 |
117888846649 ps |
| T927 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1200768018 |
|
|
Jul 27 05:00:49 PM PDT 24 |
Jul 27 05:07:00 PM PDT 24 |
15885492254 ps |
| T928 |
/workspace/coverage/default/14.sram_ctrl_bijection.242922775 |
|
|
Jul 27 05:00:13 PM PDT 24 |
Jul 27 05:01:09 PM PDT 24 |
11712016460 ps |
| T929 |
/workspace/coverage/default/25.sram_ctrl_executable.52126492 |
|
|
Jul 27 05:00:29 PM PDT 24 |
Jul 27 05:08:24 PM PDT 24 |
110128633624 ps |
| T930 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.35416298 |
|
|
Jul 27 05:01:55 PM PDT 24 |
Jul 27 05:04:27 PM PDT 24 |
1709063128 ps |
| T931 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3697220913 |
|
|
Jul 27 05:00:32 PM PDT 24 |
Jul 27 05:08:17 PM PDT 24 |
24929883661 ps |
| T932 |
/workspace/coverage/default/8.sram_ctrl_executable.1225604141 |
|
|
Jul 27 04:59:38 PM PDT 24 |
Jul 27 05:10:35 PM PDT 24 |
7316059711 ps |
| T933 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2184139515 |
|
|
Jul 27 05:02:00 PM PDT 24 |
Jul 27 05:03:24 PM PDT 24 |
1205447730 ps |
| T934 |
/workspace/coverage/default/33.sram_ctrl_smoke.1411634948 |
|
|
Jul 27 05:00:40 PM PDT 24 |
Jul 27 05:00:47 PM PDT 24 |
2869578328 ps |
| T935 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.674987895 |
|
|
Jul 27 05:01:06 PM PDT 24 |
Jul 27 05:07:04 PM PDT 24 |
31223432206 ps |
| T936 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1459502020 |
|
|
Jul 27 05:01:30 PM PDT 24 |
Jul 27 05:02:12 PM PDT 24 |
1349412103 ps |
| T937 |
/workspace/coverage/default/26.sram_ctrl_executable.3188812655 |
|
|
Jul 27 05:00:31 PM PDT 24 |
Jul 27 05:06:31 PM PDT 24 |
6845902415 ps |
| T56 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4142259794 |
|
|
Jul 27 04:58:20 PM PDT 24 |
Jul 27 04:58:21 PM PDT 24 |
126029762 ps |
| T57 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3625661307 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
74437938 ps |
| T58 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1050248410 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
40301793 ps |
| T90 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.996795767 |
|
|
Jul 27 04:58:38 PM PDT 24 |
Jul 27 04:58:39 PM PDT 24 |
17104518 ps |
| T62 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.363967860 |
|
|
Jul 27 04:58:41 PM PDT 24 |
Jul 27 04:58:42 PM PDT 24 |
32226116 ps |
| T63 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3321436590 |
|
|
Jul 27 04:58:40 PM PDT 24 |
Jul 27 04:58:42 PM PDT 24 |
777003444 ps |
| T91 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1854220563 |
|
|
Jul 27 04:58:37 PM PDT 24 |
Jul 27 04:58:38 PM PDT 24 |
58295825 ps |
| T53 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.135976311 |
|
|
Jul 27 04:58:37 PM PDT 24 |
Jul 27 04:58:39 PM PDT 24 |
260940883 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3965765742 |
|
|
Jul 27 04:58:27 PM PDT 24 |
Jul 27 04:58:28 PM PDT 24 |
38983452 ps |
| T64 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2167026916 |
|
|
Jul 27 04:58:52 PM PDT 24 |
Jul 27 04:58:53 PM PDT 24 |
63180808 ps |
| T938 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2790362649 |
|
|
Jul 27 04:58:39 PM PDT 24 |
Jul 27 04:58:40 PM PDT 24 |
31431593 ps |
| T65 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2841468529 |
|
|
Jul 27 04:58:48 PM PDT 24 |
Jul 27 04:58:49 PM PDT 24 |
14420353 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.972079990 |
|
|
Jul 27 04:58:26 PM PDT 24 |
Jul 27 04:58:27 PM PDT 24 |
33642876 ps |
| T67 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2279192237 |
|
|
Jul 27 04:58:47 PM PDT 24 |
Jul 27 04:58:47 PM PDT 24 |
24081458 ps |
| T93 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.919595204 |
|
|
Jul 27 04:58:54 PM PDT 24 |
Jul 27 04:58:55 PM PDT 24 |
12297282 ps |
| T939 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2766662222 |
|
|
Jul 27 04:58:50 PM PDT 24 |
Jul 27 04:58:52 PM PDT 24 |
49222269 ps |
| T940 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3924385835 |
|
|
Jul 27 04:59:01 PM PDT 24 |
Jul 27 04:59:03 PM PDT 24 |
44892848 ps |
| T941 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3508844561 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
37157399 ps |
| T942 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2136206454 |
|
|
Jul 27 04:58:44 PM PDT 24 |
Jul 27 04:58:47 PM PDT 24 |
164798029 ps |
| T943 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3588683333 |
|
|
Jul 27 04:58:39 PM PDT 24 |
Jul 27 04:58:40 PM PDT 24 |
35292603 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1958970466 |
|
|
Jul 27 04:58:26 PM PDT 24 |
Jul 27 04:58:26 PM PDT 24 |
20397350 ps |
| T68 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2218659238 |
|
|
Jul 27 04:58:39 PM PDT 24 |
Jul 27 04:58:40 PM PDT 24 |
29408021 ps |
| T69 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2985412313 |
|
|
Jul 27 04:58:36 PM PDT 24 |
Jul 27 04:58:37 PM PDT 24 |
19136306 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3290863577 |
|
|
Jul 27 04:58:22 PM PDT 24 |
Jul 27 04:58:23 PM PDT 24 |
41413680 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3561082027 |
|
|
Jul 27 04:58:26 PM PDT 24 |
Jul 27 04:58:27 PM PDT 24 |
48628743 ps |
| T71 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3131937316 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:45 PM PDT 24 |
447003016 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3011090369 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:45 PM PDT 24 |
54778492 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2471829881 |
|
|
Jul 27 04:58:15 PM PDT 24 |
Jul 27 04:58:17 PM PDT 24 |
45929305 ps |
| T948 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.456314202 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
17181017 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.376103675 |
|
|
Jul 27 04:58:45 PM PDT 24 |
Jul 27 04:58:46 PM PDT 24 |
119118155 ps |
| T950 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.239701886 |
|
|
Jul 27 04:58:36 PM PDT 24 |
Jul 27 04:58:41 PM PDT 24 |
226528383 ps |
| T951 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3561592701 |
|
|
Jul 27 04:58:40 PM PDT 24 |
Jul 27 04:58:40 PM PDT 24 |
38609269 ps |
| T72 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.15382156 |
|
|
Jul 27 04:58:46 PM PDT 24 |
Jul 27 04:58:50 PM PDT 24 |
1591167440 ps |
| T73 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3075530704 |
|
|
Jul 27 04:58:41 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
6060757063 ps |
| T54 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.592664941 |
|
|
Jul 27 04:58:39 PM PDT 24 |
Jul 27 04:58:41 PM PDT 24 |
139680584 ps |
| T74 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.673345956 |
|
|
Jul 27 04:58:55 PM PDT 24 |
Jul 27 04:58:59 PM PDT 24 |
1531576966 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.427173002 |
|
|
Jul 27 04:58:35 PM PDT 24 |
Jul 27 04:58:41 PM PDT 24 |
51833343 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2791797413 |
|
|
Jul 27 04:58:40 PM PDT 24 |
Jul 27 04:58:41 PM PDT 24 |
22915179 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1064206345 |
|
|
Jul 27 04:58:37 PM PDT 24 |
Jul 27 04:58:37 PM PDT 24 |
21304887 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.664526571 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
237926261 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3310955576 |
|
|
Jul 27 04:58:38 PM PDT 24 |
Jul 27 04:58:39 PM PDT 24 |
17636091 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2936704034 |
|
|
Jul 27 04:58:40 PM PDT 24 |
Jul 27 04:58:41 PM PDT 24 |
50262090 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.863528265 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
82633503 ps |
| T55 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1450654637 |
|
|
Jul 27 04:58:41 PM PDT 24 |
Jul 27 04:58:42 PM PDT 24 |
514697178 ps |
| T959 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2724509297 |
|
|
Jul 27 04:58:30 PM PDT 24 |
Jul 27 04:58:32 PM PDT 24 |
35284574 ps |
| T960 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3918776771 |
|
|
Jul 27 04:58:53 PM PDT 24 |
Jul 27 04:58:55 PM PDT 24 |
181540796 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1749031227 |
|
|
Jul 27 04:58:38 PM PDT 24 |
Jul 27 04:58:39 PM PDT 24 |
18169366 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4013741969 |
|
|
Jul 27 04:58:46 PM PDT 24 |
Jul 27 04:58:47 PM PDT 24 |
30964044 ps |
| T963 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3452294173 |
|
|
Jul 27 04:58:33 PM PDT 24 |
Jul 27 04:58:33 PM PDT 24 |
14590017 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4251694405 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:46 PM PDT 24 |
419291770 ps |
| T110 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4033602262 |
|
|
Jul 27 04:58:29 PM PDT 24 |
Jul 27 04:58:31 PM PDT 24 |
797236489 ps |
| T111 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3539804499 |
|
|
Jul 27 04:58:54 PM PDT 24 |
Jul 27 04:58:56 PM PDT 24 |
410452075 ps |
| T75 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4076369983 |
|
|
Jul 27 04:58:37 PM PDT 24 |
Jul 27 04:58:39 PM PDT 24 |
218329259 ps |
| T965 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2130094988 |
|
|
Jul 27 04:58:50 PM PDT 24 |
Jul 27 04:58:50 PM PDT 24 |
13763088 ps |
| T966 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.397561149 |
|
|
Jul 27 04:58:41 PM PDT 24 |
Jul 27 04:58:42 PM PDT 24 |
160419956 ps |
| T967 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2926971515 |
|
|
Jul 27 04:58:46 PM PDT 24 |
Jul 27 04:58:50 PM PDT 24 |
212928451 ps |
| T114 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.822030842 |
|
|
Jul 27 04:58:49 PM PDT 24 |
Jul 27 04:58:51 PM PDT 24 |
333195181 ps |
| T115 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3873600436 |
|
|
Jul 27 04:58:23 PM PDT 24 |
Jul 27 04:58:24 PM PDT 24 |
138496794 ps |
| T76 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3766814154 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
15191287 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3245724227 |
|
|
Jul 27 04:58:48 PM PDT 24 |
Jul 27 04:58:49 PM PDT 24 |
63439047 ps |
| T969 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1325813006 |
|
|
Jul 27 04:58:51 PM PDT 24 |
Jul 27 04:58:53 PM PDT 24 |
80367968 ps |
| T77 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1986520769 |
|
|
Jul 27 04:58:26 PM PDT 24 |
Jul 27 04:58:29 PM PDT 24 |
3801364315 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3769719049 |
|
|
Jul 27 04:58:38 PM PDT 24 |
Jul 27 04:58:39 PM PDT 24 |
173029615 ps |
| T81 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.122013663 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
435644192 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2707165170 |
|
|
Jul 27 04:58:13 PM PDT 24 |
Jul 27 04:58:15 PM PDT 24 |
80808040 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.436642998 |
|
|
Jul 27 04:58:39 PM PDT 24 |
Jul 27 04:58:42 PM PDT 24 |
336471477 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1325916479 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:46 PM PDT 24 |
105704816 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.283661147 |
|
|
Jul 27 04:58:34 PM PDT 24 |
Jul 27 04:58:36 PM PDT 24 |
44715899 ps |
| T82 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.918909970 |
|
|
Jul 27 04:58:41 PM PDT 24 |
Jul 27 04:58:42 PM PDT 24 |
13575301 ps |
| T112 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3471920651 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:43 PM PDT 24 |
96707331 ps |
| T83 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3217707936 |
|
|
Jul 27 04:58:25 PM PDT 24 |
Jul 27 04:58:28 PM PDT 24 |
430135608 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.289369119 |
|
|
Jul 27 04:58:35 PM PDT 24 |
Jul 27 04:58:38 PM PDT 24 |
203190715 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.510398885 |
|
|
Jul 27 04:58:25 PM PDT 24 |
Jul 27 04:58:27 PM PDT 24 |
453659207 ps |
| T977 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2300942048 |
|
|
Jul 27 04:58:45 PM PDT 24 |
Jul 27 04:58:47 PM PDT 24 |
256192542 ps |
| T116 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3085720807 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:45 PM PDT 24 |
97261087 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1043845497 |
|
|
Jul 27 04:58:18 PM PDT 24 |
Jul 27 04:58:20 PM PDT 24 |
244000078 ps |
| T89 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1618969139 |
|
|
Jul 27 04:58:38 PM PDT 24 |
Jul 27 04:58:40 PM PDT 24 |
202552573 ps |
| T978 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.418835010 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
109120654 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3142863055 |
|
|
Jul 27 04:58:45 PM PDT 24 |
Jul 27 04:58:46 PM PDT 24 |
25943727 ps |
| T980 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1334627695 |
|
|
Jul 27 04:58:35 PM PDT 24 |
Jul 27 04:58:38 PM PDT 24 |
3427602008 ps |
| T981 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3487999018 |
|
|
Jul 27 04:58:50 PM PDT 24 |
Jul 27 04:58:51 PM PDT 24 |
37825606 ps |
| T982 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3722010056 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:46 PM PDT 24 |
93766355 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.403840726 |
|
|
Jul 27 04:58:41 PM PDT 24 |
Jul 27 04:58:43 PM PDT 24 |
149649435 ps |
| T983 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2182801991 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:45 PM PDT 24 |
107277658 ps |
| T85 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3214716559 |
|
|
Jul 27 04:58:41 PM PDT 24 |
Jul 27 04:58:42 PM PDT 24 |
12298332 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1946125176 |
|
|
Jul 27 04:58:19 PM PDT 24 |
Jul 27 04:58:23 PM PDT 24 |
540394488 ps |
| T984 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4150699952 |
|
|
Jul 27 04:58:51 PM PDT 24 |
Jul 27 04:58:54 PM PDT 24 |
249322247 ps |
| T117 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.506069604 |
|
|
Jul 27 04:58:41 PM PDT 24 |
Jul 27 04:58:43 PM PDT 24 |
827180042 ps |
| T120 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1429079045 |
|
|
Jul 27 04:58:47 PM PDT 24 |
Jul 27 04:58:51 PM PDT 24 |
758889139 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3533625457 |
|
|
Jul 27 04:58:40 PM PDT 24 |
Jul 27 04:58:41 PM PDT 24 |
125495165 ps |
| T118 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.784410383 |
|
|
Jul 27 04:58:45 PM PDT 24 |
Jul 27 04:58:48 PM PDT 24 |
904990933 ps |
| T87 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3724916504 |
|
|
Jul 27 04:58:35 PM PDT 24 |
Jul 27 04:58:37 PM PDT 24 |
245810807 ps |
| T986 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.356541206 |
|
|
Jul 27 04:58:51 PM PDT 24 |
Jul 27 04:58:54 PM PDT 24 |
73238417 ps |
| T987 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2940234513 |
|
|
Jul 27 04:58:53 PM PDT 24 |
Jul 27 04:58:54 PM PDT 24 |
14440716 ps |
| T121 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.697057388 |
|
|
Jul 27 04:58:44 PM PDT 24 |
Jul 27 04:58:46 PM PDT 24 |
131753960 ps |
| T988 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2019884452 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:46 PM PDT 24 |
3914089156 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2575656554 |
|
|
Jul 27 04:58:45 PM PDT 24 |
Jul 27 04:58:48 PM PDT 24 |
47701342 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.635235755 |
|
|
Jul 27 04:58:28 PM PDT 24 |
Jul 27 04:58:30 PM PDT 24 |
23315277 ps |
| T991 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2540565138 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
38097422 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1444080352 |
|
|
Jul 27 04:58:57 PM PDT 24 |
Jul 27 04:59:00 PM PDT 24 |
1621239715 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2957738779 |
|
|
Jul 27 04:58:36 PM PDT 24 |
Jul 27 04:58:40 PM PDT 24 |
40921620 ps |
| T993 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1624350145 |
|
|
Jul 27 04:58:40 PM PDT 24 |
Jul 27 04:58:41 PM PDT 24 |
23009801 ps |
| T119 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.152906886 |
|
|
Jul 27 04:58:17 PM PDT 24 |
Jul 27 04:58:20 PM PDT 24 |
670654016 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.30560526 |
|
|
Jul 27 04:58:35 PM PDT 24 |
Jul 27 04:58:36 PM PDT 24 |
139189655 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3923631648 |
|
|
Jul 27 04:58:18 PM PDT 24 |
Jul 27 04:58:20 PM PDT 24 |
79794849 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3642559209 |
|
|
Jul 27 04:58:45 PM PDT 24 |
Jul 27 04:58:46 PM PDT 24 |
21872179 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2237044132 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
23274001 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2547710832 |
|
|
Jul 27 04:58:39 PM PDT 24 |
Jul 27 04:58:48 PM PDT 24 |
512641814 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2791880176 |
|
|
Jul 27 04:58:42 PM PDT 24 |
Jul 27 04:58:44 PM PDT 24 |
87915399 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2414913849 |
|
|
Jul 27 04:58:32 PM PDT 24 |
Jul 27 04:58:33 PM PDT 24 |
60606420 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3955857835 |
|
|
Jul 27 04:58:43 PM PDT 24 |
Jul 27 04:58:45 PM PDT 24 |
68106577 ps |